Output Stages for Integrated DC-DC Convertersand Power ICs

Wai Tung Ng', Olivier Trescases2, and Guowen Wei3

Abstract - Integrated switched mode power supplies VDD VDDand incorporate large amount of complex mixed-signal V S DDcontrol circuits as well as the power transistors on the VBDDstrap S SI

LKL n-MOS VDD -Osame die. CMOS compatibility is a very important GND L GND fL-J7 p-MOSconsideration when designing monolithic DC-DC VOUT VOUTconverters. This paper examines the different power S2 VDD 2

output stage designs and identifies the key device GND Y n-MOS C GNDLFLY n-MOS Ccharacteristics such as on-resistance, gate capacitance,switching speed that ensure optimized power conversionefficiencies. An integrated 1W, 4MHz multi-mode (a) (b)DC-DC converter with Segmented Output Stage and apeak power conversion efficiency of 88% is used to Fig. 1. Two common output stage circuit configurations: (a)illustrate various design trade-offs. Totem pole output stage with two n-MOS transistors, (b)

push-pull output stage with CMOS transistors.I. POWER OUTPUT STAGES

The output stage configuration in smart power Bootstrapping Circuitintegrated circuit (PIC) is highly dependent on theavailability of the power devices and choice of fabricationprocess. The key design issues are the device breakdown HPM - B

voltage, current handling capability, switching speed andprocess compatibility. Once these initial requirements aresatisfied, the attention should be turned to the optimizationof the perfornance of the output stage(s) and the overall L Protection Circuit:system. Over-temperature

1 _ ~~~~Over-current _

Most smart PICs are designed for switched modeoperation. With the power devices operating in fully on or Fig. 2 A pair ofn-MOS/n-MOS totem pole output stagesfully off modes, on-chip power dissipation can be used to form an H-bridge for class D audio amplifier.minimized. The half and full or H-bridges (Fig. 1 and 2) are Bootstrap circuits are needed to provide gate drive voltagesthe most common switching output configurations in smart that are higher than VDDPICs. In both cases, the output transistors are called the high driverside (HS) driver or the low side (LS) driver, depending on its odr The higher electron surface and bulk mobilitiesplacement with respect to the power supply rail. The LS would lead to a smaller device area when compared to adriver is normally an n-channel power MOSFET (n-MOS) p-MOS for a given on-resistance. However, the drawbackwith both its source and body connected to ground potential. using an n-MOS as the HS driver is due to fact that a floatingThe HS driver can be either another n-MOS (Totem pole source n-MOS is required. In addition, in order to turn theoutput stage) or ap-MOS (push-pull output stage). HS driver on and off properly, a gate drive voltage that is

higher than the supply rail (VDD) is required. This voltage isnormally generated using an on-chip bootstrap circuit (with

II. N-MOS HIGH-SIDE DRIVER integrated diode as seen in Fig. 2.).

The choice on which configuration to use is normally Since the power devices are required to support highdetermined by the output power level. For high voltage and supply voltage, the extended drain MOSFET (EDMOS)high current applications (e.g. 10's of volts and several structure is normally employed [1]. An integrated H-bridgeamperes) it is more advantages to use n-MOS as the HS fabricated using a 40V CMOS compatible process [2] with

floating source n-type EDMOS transistors for the HS and

1. ai ungNgs wth lecricl ad Cmpuer ngieerng LS drivers is as shown in Fig. 3. This output stage wasDepartment, University of Toronto, Toronto, Ontario, Canada designed for a 40W Class D power amplifier. The used ofM5S 3G4. Tel: (416) 978-6249, Fax: (416) 971-22861 n-type EDMOS as the power transistors allowed an area

e-mail: nwarguooocaeffi1cient design with on-chip protection circuits, gate drivers,2. Olivier Trescases is currently working in theAutomotive Power and bootstrap circuits. Both the HS and LS drivers have

Department at Infineon Technologies AG, Siemenstrasse 2, on-resistances of220mQ. With asupply voltage of25V, theVillach, A9500, Austria. maximum efficiency achieved was 8800.

3. Guowen Wei is currently working on his PhD degree at UC SanDiego, Electrical and Computer Engineering.

1-4244-0637-4/07/$20.OO ©C2007 IEEE 91

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the best conduction loss versus efficient use of area theon-resistance of the p-MOS can be approximately three

4 times higher (76/24 3) Therefore, the device areas forboth the n-MOS andp-MOS do not necessarily have to be ina ratio of 1:3.

IV. SEGMENTED OUTPUT STAGEI Once te size of the HS and LS divers are determine

for a particular peak conversion efficiency, output currentand switching frequency, the overall performance of theoutput stage can be further improved by optimizing theswitching loss. The typical source of power losses in aDC-DC converter is as shown in Fig. 5. The output stage isresponsible for the gate drive and conduction loss. The gatedrive loss, Pgate is dominant at low output current (see Fig. 6)

Fig. 3. A micrograph of an H-bridge output stage for a 50W and is given bymonolithic class D audio amplifier. This chip is fabricated 2 2using a 40V, 0.35ptm CMOS technology. The die size is 2.8 Pgate fs VCgate,P + Cgate,N ) Vinx3.5 mm2.

Pgate is proportional to the size of the n-MOS and p-MOSIII. CMOS PUSH-PULL OUTPUT STAGE drivers. If smaller size power transistors can be selected at

low output current, Pgate can be reduced. This will maintainIn low power, low voltage DC-DC converter high power conversion efficiency over a wide range of

applications (e.g. battery powered, 1W operation), the output current.amount of current that needs to be handled by the HS driveris normally less than IA. In this case, conventional CMOS FETsdevice structures such as those shown in Fig. 4 would be ESR Gate Switching &idea candidates for the HS and LS drivers. No additional loss Drive conductionprocess changes to the standard CMOS technology isneeded, making this approach highly economical and M RL lossattractive. In addition, the fact that a p-MOS is used as the E lsHS driver, the gate drive signal can be the same PWM L _(Pulse Width Modulation) waveform with appropriate -T n

dead-times. MAT

NMOS PMOS Controller

u ~~~~Body diode

~~~~~~Si2i2biasing &_~~~~~~~~~~~~~-p switching

p-guard n-guard Fig. 5. Various power losses in a DC-DC converter.

100

Fig. 4. Cross section of a standard CMOS technology thatcan be used to form a push-pull output stage. 75

Although the hole surface mobility is approximately ,three times lower than that for electron, it is often not a

necessary to design the HS p-MOS driver to have three . Itimes the area as the LS n-MOS driver. Since the duty cycle 25 G-te nrixe & losslof PWM signal is approximately equal to the ratio of the |Cnrleoutput to input voltage,

0

Duty cycle iV0ti/Vn (1) 0 10lout (mA)2030

the average duration that the HS driver turns on is not 5000 Fig. 6. Typical power conversion efficiency versus outputFor example, with a Li-ion battery input voltage of4.2V and current. Gate drive and controller losses dominatean output voltage of 1.OV, the duty cycle for the HS and LS in the low output current range. Conduction loss isdrivers are 2400 and 7600, respectively. In order to achieve more prominent at high output current.

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The circuit configuration of the p-MOS and n-MOS pMOS Drivers nMOS Driversdrivers in a traditional output stage, as shown in Fig. 7, canbe partitioned into parallel combinations of identical _transistors. These transistors can be further grouped in tothree independently controlled segments to achieve a binary. _ _ - -

Tr_aditional Output StagEe:.Dvr

Segmented Output Stage:

J f J . _ ;1Fig. 8. A segmented output stage fabricated using a 0.18pim. .It Ltt<H~ V H +ht -CMOS technology. The n-MOS and p-MOS have active

areas of 0.075 and 0.20mm2, respectively.

10]h2 Gbta Wil.

Fig. 7. Schematic of a traditional CMOS push-pull outputstage with two large gate drive circuits for the high-side and Mudenlow side switches. The segmented output stage is basically are-organization of the same layout with transistor segmentsgrouped into size of 1, 2 and 4. PvGt

weighting of size 1, 2, and 4. The gate drive signals areconnected to individual gate drivers such that only the gatecapacitances of the selected segments are switched. With adigitally controlled DC-DC converter [3], different segment /size can be selected according to output current. This allows 4dynamic optimization of Pgate.

This segmented output stage (see Fig. 8) wasimplemented using a 0.1 8tm standard CMOS technologywith a maximum breakdown voltage of 5V. The active v contactdevice areas for the HS and LS drivers were chosen to

X / ~MI=Substrateotcminimize the conduction loss for an input voltage range of X2.7 to 4.2V and an output voltage of 1.8V with a maximum U PoYMt42Cotatoutput current of 5OOmA. The n-MOS and p-MOStransistors have active areas of 0.075 and 0.20mm2 Fig. 9. Basic cell for the power MOSFET hybrid-wafflerespectively. The layout of the output stage employed a layout structure.hybrid waffle configuration as shown in Fig. 9. Thetransistor fingers are arranged in a square grid where the 1.9 4source and drains are connected using diagonally running [001]: Only smallest segment is ONmetal lines. Initial observation suggests that must silicon 1.7 t -Gn1Ro3.5area is allocated to in-active area and may results in high 1.5 l -Gen2 Ron 3on-resistance. However, the diagonal metal lines used to -tGenl Pgate E

connect drain and the source terminals can now be made 1.3 -\' GenI Pgate 2.5 awider than if minimum geometry was used. This approach itl 2 Lallows the device on-resistance and interconnect resistance I >

to be optimized. 0.9

The measured range of on-resistance and gate drive t=11tpower loss (Gen2) and previously published data (Gent) are 05s [111]: All segments are ON O.Sas plotted in Fig. 10. As the transistor size changes from a 0.3 \ 0normalized size oftl to 7, the gate drive power also increases 0 1 2 3 4 5 6 7 8proportionally for both n-MOS and p-MOS. However, the Enable Code (en_N/P[2:O] )on-resistance reduces from t1.72Q to 0.3Q for the n-MOS. Fig. tO. Measured on-resistance and gate drive loss for the

segmented output stage, ranging from the smallest to theThe efficiency measuremy at low output current range. By largest segment size. Generation 2 is an improvement overcontract, with ents for V111= 2.7V with different enable codes previously published data 131.are shown in Fig. t t. Enable code of<t t t> iS equivalent to

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select all transistor segments, hence the largest transistor Semiconductor Devices and Integrated Circuits (ISPSDsize. The power conversion efficiency is highest for large '06), Naples, Italy, June 4-9, 2006.current, but suffers significantly at low output current range.By contract, with enable code of <001>, only the smallest 95

segment is selected. The power conversion efficiency is now _ _90

highest at low current and reduces as the output currentincreases. Also included in Fig. 11 are the power conversion 85efficiencies for the PFM (Pulse Frequency Modulation) andDCM (discontinuous mode) for the largest and smaller &80power transistor sizes. For very low output current, it is a) J100much more advantageous to switch from PWM to PFM al1mode. With the use of a digital controller [3], the optimal 70 |.0enable codes and operating mode (PWM or PFM) can be -PFM 111selected such that the peak power conversion efficiency can 65 -PFM 001be maintained over the widest possible output current range. 60Using this approach, the converter achieved a peak 1 10 100 1000efficiency of 88%. This is a significant improvement by a Output Current (mA)maximum of 6.2% when compared to the non-segmented Fig. 11. Measured efficiency versus output current for V1case as shown in Fig. 12. The peak efficiency is limited by 2nthe relatively high inductor series resistance and Xhigh-switching losses in the power stage at 4 MHz. combinations out of 49 since the NMOS and PMOS use the

same enable code.

V. CONCLUSIONS 90 V= 4.2 V, Vo= 1.8 Vf,s4MHz=

This paper examined different CMOS compatible output 85stage configurations that are suitable for smart PICimplementation. n-channel EDMOS structures are moreattractive for the HS driver in totem pole output stages in 80high voltage, high current applications. Standard CMOS 6.2%Efficiencylmprovementtechnologies can be used to implement push pull output 75

en P [2:0] = -m-_100stages in battery operated low power applications. The enLN [2:0O] = -0-11Hybrid Waffle layout technique is effective in providing a 7010better trade-off between device on-resistance and metal

NMOS is off PFMlil1interconnect resistance. Further optimization of the power D 001

conversion efficiency over a wide range of output current 6510 100 1000can be realized by using segmented output stages and Output Current (mA)multi-mode operations.

Fig. 12. Measured efficiency versus output current for V.1 -2.7V. In the top curve, the optimal segments are enabled by

VI. ACKNOWLEDGEMENT selecting the appropriate segment size according to theThe authors .ulAsahi output current. The bottom curve is achieved ifThe authors would like to thank Fuji Electric and semnttoni ntusd

Kasei EMD for financial support and devices fabrication. segmentatio s ot usedWe also want to thank Auto2 1, NSERC for financialsupport.

VII. REFERENCES[1] Peter C. Mei, Katsumi Fujikura, Takaaki Kawano,

Satwinder Malhi, "A High Performance 30V ExtendedDrain RESURF CMOS Device for VLSI IntelligentPower Applications," Symposium on VLSI TechnologyDigest of Technical Papers, pp. 81-82, 1994.

[2] V.W.Y. Ma, E.H.P. Xu, W.T. Ng, Y. Hara, Y.Furukawa, K. Sakai, H. Imai, T. Naito, S. Nobuyuki, S.Tamura, K. Takasuka, T. Kohno, "Integration ofComplementary EDMOS in a Standard 0.35um CMOSTechnology for 40V Applications," EDSSC'03, Tech.Digest, Hong Kong, Dec. 16-18, 2003, pp. 301-304.

[3] 0. Trescases, W.T. Ng, H. Nishio, M. Edo and T.Kawashima, "A Digitally Controlled DC-DC ConverterModule with a Segmented Output Stage for OptimizedEfficiency," 18th Inter-national Symposium on Power

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