Output Response Analysis Output Response Analysis ...strouce/class/elec6970/BISTc5.pdf · Output Response Analysis Output Response Analysis -- Organization Organization Types of Output

Output Response Analysis Output Response Analysis -- OrganizationOrganization

�� Types of Output Data CompactionTypes of Output Data Compaction

��ConcentratorsConcentrators

��ComparatorsComparators

��Counting TechniquesCounting Techniques

��Signature AnalysisSignature Analysis

C. Stroud 9/09 Output Response Analysis 1

��Signature AnalysisSignature Analysis

��AccumulationAccumulation

��Parity CheckParity Check

�� Fault Simulation ConsiderationsFault Simulation Considerations

�� Comparing ORAsComparing ORAs

�� Summary of Methods to Reduce AliasingSummary of Methods to Reduce Aliasing

Compaction TechniquesCompaction Techniques

�� Compact multiple output responses into a single resultCompact multiple output responses into a single result�� Counting TechniquesCounting Techniques

��Counting 1s or 0sCounting 1s or 0s��Also called Syndrome AnalysisAlso called Syndrome Analysis��Similar to Berger and BoseSimilar to Berger and Bose--Lin error detection codesLin error detection codes

��Counting lowCounting low--toto--high, highhigh, high--toto--low, or both transitions low, or both transitions ��Hardware: countersHardware: counters


��Hardware: countersHardware: counters

�� Signature analysisSignature analysis(most common ORA in BIST)(most common ORA in BIST)��Single output Single output -- Signature Analysis Register (SAR)Signature Analysis Register (SAR)��Multiple outputs Multiple outputs -- Multiple Input Signature Register (MISR)Multiple Input Signature Register (MISR)

��Hardware: LFSR (CAR would also work)Hardware: LFSR (CAR would also work)

�� Can be used with concentratorsCan be used with concentrators�� Aliasing Aliasing –– faulty circuit produces good circuit faulty circuit produces good circuit

signature/syndromesignature/syndrome

ConcentratorsConcentrators�� Used to reduce number of outputs to be monitoredUsed to reduce number of outputs to be monitored

��Compacts number of output responsesCompacts number of output responses��Does not compact output responses in timeDoes not compact output responses in time

�� Hardware: tree of XOR gatesHardware: tree of XOR gates��Same as parity generationSame as parity generation

�� Often used with other ORA techniquesOften used with other ORA techniques��Passes any combination of odd errorsPasses any combination of odd errorsNN

Outto ORAOutto ORANOutto ORA


��Passes any combination of odd errorsPasses any combination of odd errors��Masks any combination of even errorsMasks any combination of even errors

�� Not selfNot self--testingtesting��Can be tested in only 4 vectorsCan be tested in only 4 vectors

��SS⊕⊕T=RT=R��RR⊕⊕S=TS=T��TT⊕⊕R=SR=S

NN to ORAto ORAN to ORA

S T RS T R0 0 00 0 00 1 10 1 11 0 11 0 11 1 01 1 0

S T RS T R0 0 00 0 00 1 10 1 11 0 11 0 11 1 01 1 0

S T RS T R0 0 00 0 00 1 10 1 11 0 11 0 11 1 01 1 0

++++

++

++++++++

In0In1In2In3In4In5In6In7


Outto ORAOutto ORA

SS

TTRR

RR

TT

SS

RR

1100 S1010 T0110 R1100 S1010 T0110 R1100 S1010 T

1100 S1010 T0110 R1100 S1010 T0110 R1100 S1010 T

++

+

++++


Outto ORA

S

TR

R

T

S

R

1100 S1010 T0110 R1100 S1010 T0110 R1100 S1010 T

ComparatorsComparators�� Works well with known good output responsesWorks well with known good output responses

��From algorithmic TPGFrom algorithmic TPG��Hardware: comparator (w/latch) & extra TPG logic for output responseHardware: comparator (w/latch) & extra TPG logic for output response

��From simulation stored in ROMFrom simulation stored in ROM��Hardware: comparator (w/latch) & ROM with counterHardware: comparator (w/latch) & ROM with counter

��Counter faults are maskedCounter faults are masked

��Outputs of identical circuits with same test patternsOutputs of identical circuits with same test patterns��Hardware: comparator and latchHardware: comparator and latch


��Hardware: comparator and latchHardware: comparator and latch��Equivalent faults are maskedEquivalent faults are masked

��Latch up mismatches until end of BIST sequenceLatch up mismatches until end of BIST sequence��Should be RS flipShould be RS flip--flopflop

��RS latch susceptible to glitchesRS latch susceptible to glitches

�� Single Pass/Fail indicationSingle Pass/Fail indication��What if it is “stuckWhat if it is “stuck--atat--pass”?pass”?��Not selfNot self--testing testing -- need additional test vectorsneed additional test vectors

Pass/FailPass/Fail

A1

B1

An

Bn

A1

B1

An

Bn

setresetsetreset

BIST startClock

BIST startClock

Pass/Fail

A1

B1

An

Bn

setreset

BIST startClock

1s or 0s counting (Syndrome Analysis)1s or 0s counting (Syndrome Analysis)�� Assume Assume m m input vectorsinput vectors

�� Response Response R R = = rr11, r, r22,..., r,..., rmm

�� Syndrome Syndrome SS((RR) = count of response) = count of response�� SS11(R) count 1s, S(R) count 1s, S00(R) count 0s(R) count 0s

��Similar to Berger and BoseSimilar to Berger and Bose--Lin codesLin codes

�� Syndrome aliasingSyndrome aliasing

�� None when None when SS((RR)) = 0 or = 0 or SS((RR)) = = mm�� WorstWorst--case when case when SS((RR)) = = mm/2 /2

∑=

=m

iirRS

1

1 )(

R0=0100 (fault-free)R =0101 (faulty ckt)R0=0100 (fault-free)R =0101 (faulty ckt)

inputsinputsR0=0100 (fault-free)R =0101 (faulty ckt)

inputs


�� WorstWorst--case when case when SS((RR)) = = mm/2 /2

�� Fault(s) creating odd # of errorsFault(s) creating odd # of errors

�� Always detectedAlways detected

�� Fault(s) creating even # of errorsFault(s) creating even # of errors

�� May not be detected (syndrome aliasing)May not be detected (syndrome aliasing)

�� Multiple CUT outputs Multiple CUT outputs ⇒⇒ more hardwaremore hardware

�� Multiple countersMultiple counters

�� Use concentrator to reduce # countersUse concentrator to reduce # counters

1C(R0)=11C(R1)=2 detected1C(R2)=1 aliasing

1C(R0)=11C(R1)=2 detected1C(R2)=1 aliasing

CUTCUTCUTCUT

CounterCounterCounterCounter

R1=0101 (faulty ckt)R2=0010 (faulty ckt)R1=0101 (faulty ckt)R2=0010 (faulty ckt)

ClkClk

outputoutputCUTCUT

CounterCounter

R1=0101 (faulty ckt)R2=0010 (faulty ckt)

Clk

output

Transition CountingTransition Counting�� Assume Assume m m input vectorsinput vectors

��Response Response R R = = rr11 , r, r22 ,..., r,..., rmm

��Syndrome Syndrome SS((RR) = count of response ) = count of response transitions (rising, falling, or both)transitions (rising, falling, or both)

�� AliasingAliasing��Same as 1s/0s countingSame as 1s/0s counting

�� ProblemsProblems

∑−

=+⊕=

1

11)(

m

iiiT rrRS

R0=0100 (fault-free)R1=0000 (faulty ckt)R0=0100 (fault-free)R1=0000 (faulty ckt)

inputsinputsR0=0100 (fault-free)R1=0000 (faulty ckt)

inputs

Example of both transitions


�� ProblemsProblems��Multiple outputsMultiple outputs

��Multiple countersMultiple counters��Use concentrator to reduceUse concentrator to reduce

��Glitches from combinational logic Glitches from combinational logic outputs could be counted if TD is outputs could be counted if TD is connected to clock input of counterconnected to clock input of counter��FaultFault--free CUT declared faultyfree CUT declared faulty

TC(R0)=2TC(R1)=0 detectedTC(R2)=2 aliasing

TC(R0)=2TC(R1)=0 detectedTC(R2)=2 aliasing

CUTCUTCUTCUT

CounterCounterCounterCounter

R1=0000 (faulty ckt)R2=0010 (faulty ckt)R1=0000 (faulty ckt)R2=0010 (faulty ckt)

ClkClk

outputoutput

TDTDTDTD

TransitionDetector

TransitionDetector

CUTCUT

CounterCounter

R1=0000 (faulty ckt)R2=0010 (faulty ckt)

Clk

output

TDTD

TransitionDetector

Counting Techniques (cont)Counting Techniques (cont)

�� Transition detectors Transition detectors –– digital onedigital one--shotshot

��Note: TD output connects to enable input of counterNote: TD output connects to enable input of counter��Not to clock input since glitches cause incorrect resultsNot to clock input since glitches cause incorrect results

BothBothInputInput

ClockClock

RisingRisingInputInput

ClockClock

FallingFallingInputInput

ClockClock

BothInput

Clock

RisingInput

Clock

FallingInput

Clock


�� SelfSelf--testing?testing?

��Only if syndrome > 2Only if syndrome > 2nn--11

��Where Where nn = number of bits of counter= number of bits of counter

��Need to toggle MSB of counterNeed to toggle MSB of counter

∴∴Optimal Optimal nn--bit counter size: 2bit counter size: 2nn > syndrome > 2> syndrome > 2nn--11

Input

Q

TDout

Input

Q

TDout

In•QbIn•Qb In+QbIn+Qb

In⊕QIn⊕Q

Input

Q

TDout

In•Qb In+Qb

In⊕Q

Signature AnalysisSignature Analysis�� Uses LFSR with additional XOR for each CUT outputUses LFSR with additional XOR for each CUT output

��Single output => Signature Analysis Register (SAR)Single output => Signature Analysis Register (SAR)

��Multiple outputs => Multiple Input SAR (MISR)Multiple outputs => Multiple Input SAR (MISR)

��PP((xx) = ) = xx44 + + xx33 + + xx + 1 (for both SAR and MISR below)+ 1 (for both SAR and MISR below)

��Signature = LFSR contents after last output responseSignature = LFSR contents after last output response

fromfromfrom


D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

fromCUTfromCUT

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

fromCUT

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

from CUTfrom CUT

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

from CUT

SARSAR

MISRMISR

Signature Analysis (cont)Signature Analysis (cont)

�� Seed Seed –– initial value of SAR (typically all 0s)initial value of SAR (typically all 0s)

�� Fault detection: Fault detection: SS((RR00) ) ≠≠ SS((RR))0 0 0 seed0 0 0 seed

1/1/00 0 00 00 1/0 1/00 00

1/1/00 0 1/0 1/001/1/00 0 00 01 1/1 1/00 000 1 1/0 1 1/00

1/1/00 1/1/00 1 sig1 sig

response from CUT0 0 1 0 1/0 0 1/0

good circuit responsefaulty circuit response

response from CUT0 0 1 0 1/0 0 1/0

good circuit responsefaulty circuit response

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK


�� Signature aliasing: Signature aliasing: SS((RR00) ) = = SS((RR))

1/1/00 1/1/00 1 sig1 sig

response from CUT0 0 1 0/1 1/0 0 1/0good circuit responsefaulty circuit response


0 0 0 seed0 0 0 seed1/1/00 0 00 00 1/0 1/00 00

1/1/00 0 1/0 1/001 0 01 0 01 1 01 1 00 1 10 1 11 1 1 sig1 1 1 sig

0 0 0 seed0 0 0 seed1/1/00 0 00 00 1/0 1/00 00

1/1/00 0 1/0 1/001 0 01 0 01 1 01 1 00 1 10 1 11 1 1 sig1 1 1 sig

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK


0 0 0 seed0 0 0 seed1/1/00 0 00 00 1/0 1/00 00

1/1/00 0 1/0 1/001 0 01 0 01 1 01 1 00 1 10 1 11 1 1 sig1 1 1 sig

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK


�� Signature analysis is polynomial division by LFSRSignature analysis is polynomial division by LFSR

��Polynomial representation of a binary sequence:Polynomial representation of a binary sequence:�� GG((xx)) = response from CUT= response from CUT

�� GG((xx) arrives highest power coefficient 1) arrives highest power coefficient 1stst

��PP((xx)) = characteristic polynomial= characteristic polynomial

��RR((xx)) = = GG((xx)) mod Pmod P((xx))

Response from CUTResponse from CUTtimetime →→ 100101100101xx55 xx44 xx33 xx22 xx11 xx00

1 0 0 1 0 11 0 0 1 0 1GG((xx)) = x= x55 + + xx22 + 1+ 1


��RR((xx)) = = GG((xx)) mod Pmod P((xx))�� GG((xx) = ) = PP((xx) ) QQ((xx) + ) + RR((xx))

��QQ((xx) = quotient) = quotient

��RR((xx) = remainder) = remainder

�� RR((xx)) = signature= signature

��Same as code word in CRCSame as code word in CRC�� Cyclic Redundancy CheckCyclic Redundancy Check

LFSRLFSRPP((xx))

LFSRLFSRPP((xx))

G(x)fromCUT

G(x)fromCUT

Q(x)Q(x)

Initial state (seed): all 0sFinal state (signature): R(x)


LFSRLFSRPP((xx))

G(x)fromCUT

Q(x)


GG((xx)) = x= x55 + + xx22 + 1+ 1

Signature Analysis (cont)Signature Analysis (cont)�� GG00((xx)) = expected response= expected response

�� RR00((xx)) = expected signature = = expected signature = GG00((xx) mod ) mod PP((xx))

�� GG((xx)) = faulty circuit response = = faulty circuit response = GG00((xx)) + + EE((xx))

�� EE((xx) = error polynomial = ) = error polynomial = GG00((xx)) ++ GG((xx))

�� RR((xx)) = faulty circuit signature = [= faulty circuit signature = [GG00((xx)) + + EE((xx)] mod )] mod PP((xx))

�� RREE((xx) = signature of the error polynomial) = signature of the error polynomial

�� RREE((xx) = ) = RR00((xx)) + R+ R((xx)) = E= E((xx) mod ) mod PP((xx))

0 0 0 seed0 0 0 seed1/1/00 0 00 00 1/0 1/00 00

1/1/00 0 1/0 1/001 0 01 0 01 1 01 1 0


EE 00

�� Signature Aliasing occurs when:Signature Aliasing occurs when:

�� RR((xx)) = = RR00((xx))

�� EE((xx)) = multiple of = multiple of PP((xx))

�� Example:Example:

�� EE((xx)) = = xx66 + + xx44 + + xx33

�� PP((xx)) = = xx33 + + x x + 1+ 1

�� EE((xx)) = multiple of = multiple of PP((xx))�� AliasingAliasing

response from CUT0 0 1 0/1 1/0 0 1/0response from CUT

0 0 1 0/1 1/0 0 1/0

1 1 01 1 00 1 10 1 11 1 1 sig1 1 1 sig

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK

D QD Q

CKCK


Probability of Signature Aliasing:Probability of Signature Aliasing:�� ≅≅ 22--nn where where nn = degree of characteristic (size of LFSR)= degree of characteristic (size of LFSR)Reducing the probability of signature aliasing:Reducing the probability of signature aliasing:�� Use a large signature analyzerUse a large signature analyzer

��High degree characteristic polynomialHigh degree characteristic polynomial�� Use primitive polynomialsUse primitive polynomials�� Use long test sequencesUse long test sequences


�� Use long test sequencesUse long test sequences�� Use multiple polynomialsUse multiple polynomials

��ReRe--apply same test patterns for different polynomialsapply same test patterns for different polynomials�� ReRe--apply the same test patterns in reverse orderapply the same test patterns in reverse order�� Observe intermediate signaturesObserve intermediate signatures�� Use a biUse a bi--directional MISRdirectional MISR

�� rere--apply same patterns after reversing shift directionapply same patterns after reversing shift direction

AccumulationAccumulation�� Same as checksum error detection codesSame as checksum error detection codes�� Three types Three types –– but there are othersbut there are others

�� Single precision Single precision –– ignore carryignore carry--outout�� NN--bit code wordbit code word

�� Residue Residue –– endend--aroundaround--carry (carry added as an LSB)carry (carry added as an LSB)�� NN--bit code wordbit code word

�� Double precision Double precision –– retain all carriesretain all carries�� 22NN--bit code wordbit code word

�� Good for mixedGood for mixed--signal circuits to allow for expected variations in signalssignal circuits to allow for expected variations in signals


�� Good for mixedGood for mixed--signal circuits to allow for expected variations in signalssignal circuits to allow for expected variations in signals�� Due to temperature, voltage, tolerance of componentsDue to temperature, voltage, tolerance of components

NN--bit Adderbit AdderNN--bit Adderbit Adder

NN--bit Registerbit RegisterNN--bit Registerbit Register

NN

NN

NN

Single precisionSingle precision

NN--bit Adderbit Adder

NN--bit Registerbit Register

N

N

N

Single precision

NN--bit Adderbit AdderNN--bit Adderbit Adder


NN

NN

NN

ResidueResidue

FFFFFFFF

carryoutcarryout

carryin

carryinNN--bit Adderbit Adder


N

N

N

Residue

FFFF

carryout

carryin NN--bit Adderbit AdderNN--bit Adderbit Adder


NN

NN

NN

Double precisionDouble precision

carry outcarry out

NN--bit counterbit counterNN--bit counterbit counterNN

NN--bit Adderbit Adder


N

N

N

Double precision

carry out

NN--bit counterbit counterN

Other ORAsOther ORAs�� CA registers can be used for signature analysisCA registers can be used for signature analysis

��SelfSelf--testingtesting

�� Parity checkParity check

��Can be used with concentrator for multiple outputsCan be used with concentrator for multiple outputs

��Can be viewed as special case ofCan be viewed as special case of��Syndrome analysis: 1s counting with 1Syndrome analysis: 1s counting with 1--bit counterbit counter


��Checksum: 1Checksum: 1--bit single precision accumulatorbit single precision accumulator

��Signature analysis: Signature analysis: PP((xx) = ) = xx + 1+ 1

��Probability of aliasingProbability of aliasing��≈≈ 22--11 = 0.5= 0.5

��SelfSelf--testingtesting

Pass/FailPass/Fail

output data from CUT(or from concentrator)output data from CUT(or from concentrator)

DresetDreset

BIST startClock

BIST startClock

Pass/Fail

output data from CUT(or from concentrator)

Dreset

BIST startClock

Comparison of ORA TechniquesComparison of ORA Techniques�� ComparisonComparison

�� No aliasing like signature No aliasing like signature

and syndrome analysisand syndrome analysis

�� Not selfNot self--testingtesting�� Needs additional testsNeeds additional tests

�� CompactionCompaction�� SelfSelf--testingtesting

ORAORA Concurrent Error Detection AnalogConcurrent Error Detection AnalogConcentratorsConcentrators Parallel Parity Check/GenerationParallel Parity Check/GenerationComparatorsComparators ~ Redundancy w/Comparison~ Redundancy w/ComparisonCounting TechniquesCounting Techniques Berger Code/BoseBerger Code/Bose--LinLinSignature AnalysisSignature Analysis Cyclic Redundancy CheckCyclic Redundancy CheckAccumulatorsAccumulators ChecksumChecksumParity CheckParity Check Parity CheckParity Check


�� SelfSelf--testingtesting

�� Suffers from aliasingSuffers from aliasing�� Probability can be Probability can be

controlledcontrolled

�� ConcentrationConcentration�� Must be observed every Must be observed every

output responseoutput response

�� But works with signature But works with signature

and syndrome analysisand syndrome analysis

Documents

Output Response Analysis Output Response Analysis ...strouce/class/elec6970/BISTc5.pdf · Output Response Analysis Output Response Analysis -- Organization Organization Types of Output