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So/i&State Electronics Vol. 41. No. 8. pp. 1133-l 138. 1997 k 1997 Elsevier Science Ltd. All rights reserved
Printed in Great Britain PII: SOO38-1101(97)00036-1 0038-llOl/97 317.00+0.00
OUTPUT CHARACTERISTICS OF THE DUAL CHANNEL EST
S. SRIDHAR and B. J. BALIGA Power Semiconductor Research Center, North Carolina State University, Raleigh, NC 27695-7924,
U.S.A.
(Recehed 25 Ju1.v 1996; in relrised form I I January 1997)
Abstract Analysis of the output characteristics of the Dual Channel EST (DC-EST) is provided for the first time in this article. It is demonstrated by analytical modelling and with the aid of two dimensional numerical simulations that the output resistance in the region of current saturation is determined by the activation of the narrow base NPN transistor in the IGBT segment. Based upon this model. the experimentally observed degradation in the output resistance with an increase in the distance between the shorts in the P-base region of the main thyristor segment can be explained. This model is shown to be consistent with the experimentally observed degradation in the output resistance with larger design rules used for device fabrication because this determines the current level at which the NPN transistor becomes activated. The observed reduction in the output resistance results in a degradation in the forward bias safe operating area. 0 1997 Elsevier Science Ltd.
NOTATION
total current flowing at the anode terminal (A) total current flowing at the cathode terminal (A) channel component of current (A) hole component of cathode current (A) hole component of current collected in the P + base (A) hole component of current flowing in the P-base beneath the N + cathode (A) collector current flowing in the shunted NPN fransistor (A) gain of the vertical PNP transistor gain of the shunted NPN transistor resistance seen by holes in the P-base region of the main thyristor segment (a) resistance of P-base region below the N + cathode 6-v output resistance (Q)
1. INTRODUCTION
Applications such as motor drives and uninterrupted power supplies (UPS) require high power semicon- ductor devices with low on-state drops, high current carrying capability and a large forward blocking voltage capability. The IGBT[l,2] is the device used most commonly for these applications today as it combines the simple gate drive circuitry of the MOSFET with low on-state voltage drops of a bipolar device. It also has a desirable high voltage current saturation capability. Several MOS-gated thyristors (MCT[3], EST[45], BRT[6], and Dual Channel EST[7]) with lower on-state voltage drops than the IGBT have been reported. Of these the Dual Channel EST (DC-EST) is the only MOS-gated thyristor structure that exhibits high voltage current saturation. The FBSOA is an important parameter
in the evaluation of the performance of power devices[lO]. Recent work on the safe operating area (SOA) of the DC-EST[8-91 showed that the forward bias safe operating area (FBSOA) of the DC-EST is superior to that of the IGBT and strongly dependent on the resistance in the P-base region of the main thyristor segment. This makes the DC-EST an attractive alternative to the IGBT.
In this article, the output characteristics of the DC-EST are analyzed for the first time. It was found experimentally that the output characteristics of the DC-EST were dependent on the shorting density for the P-base region of the main thyristor and the design rules used to fabricate the device. An explanation for this behaviour was developed based upon the activation of the NPN transistor in the IGBT segment. The design rules used during the layout of the device which determines the resistance in the P-base region of the parasitic thyristor segment is shown to have a strong influence on the activation of the NPN transistor, and hence the output resistance (R,) of the DC-EST. It is demonstrated that a reduction in the output resistance also results in a degradation in the forward bias safe operating area (FBSOA). The analytical expressions for the output characteristics derived in this article, are in excellent agreement with measured data obtained using DC-ESTs with 700 V forward voltage blocking capability.
2. DEVICE STRUCTURE AND OPERATION
A schematic cross-section of a DC-EST structure is shown in Fig. 1. The P-base region in the main
II33
1134 S. Srldhar and B. J. Baliga
thyristor segment is shorted to the cathode in the the floating N + /P-base junction and the thyristor dimension perpendicular to the cross-section. The latches up. Since there is no cathode contact to the resistive path to current flow through the short is floating N + region, the thyristor current is represented by a lumped equivalent resistance Rel as constrained to flow through the lateral MOSFET. shown in Fig. 1. The device operates in the forward Thus gate control is retained over device operation blocking mode when a positive bias is applied to the even after the latch-up of the main thyristor. At high anode with the gate shorted to the cathode. When the current densities, the parasitic thyristor shown in anode is biased positive with respect to the cathode, Fig. 1, whose latch-up is determined by the resistance the device can be turned on by the application of a Rs2, gets activated resulting in the loss of gate control positive bias to the gate. At low anode current levels, over the device. the device operates like an IGBT. As the anode At low gate biases, as the anode bias is increased current increased, the hole current collected in the (after the latch-up of the main thyristor) the potential P-base region of the main thyristor forward biases at point A (Fig. I) in the N- drift region rises. When
A * 4 I K
. . . B
I Ihl
Floating N+
P Transistor
; A . i
,........_....................-.. .._.._.._.._.._.._..v..-..-..-. ._.._.._.. 1
AIdP. IA
Fig. I. Cross-section of the Dual Channel EST (DC-EST). showing current flow paths during current saturation.
Output characteristics of the dual channel EST 1135
50 0 5 10 15 20 25 30 35 40
Amdevonage(voits)
Fig. 2. Comparison of experimentally obtained and analytically calculated output characteristics of a DC-EST structure. Structure 1 has a loose design rules (L = 2 pm) and a large Rw. Structure 2 has tighter design rules (L = 0.8 pm) and a smaller Rw. The cell pitch is 46 pm.
the potential at A exceeds that applied on the gate, the channel pinches off, disrupting the regenerative thyristor action. It was shown previously[8] that the device then reverts from a thyristor mode of operation to an IGBT mode of operation and hence exhibits high voltage current saturation.
3. ANALYTICAL MODEL
It was demonstrated previously[8] that the DC- EST operates in an IGBT mode during high voltage current saturation. The expression derived pre- viously[l l] for the total current during saturation in an IGBT is;
where IA is the total current, IMos the MOSFET component of the current and apNp the gain of the vertical PNP transistor. However, it was found that this expression does not predict the measured output characteristics of the DC-EST as shown in Fig. 2 for structure 1. It is demonstrated in this section that the activation of the NPN transistor in the IGBT segment caused by hole current flowing in the P-base region of the IGBTregion is responsible for a significant degradation in the output resistance.
In the current saturation region of operation for the DC-EST, the total current collected at the cathode can be obtained by summing up the current components along the P-base/N-drift junction in the IGBT segment of the device (along the boundary AB in Fig. I), with the current collected in the cathode short (via J&i) included in I,,,. The total cathode current (Ik) consists of three components; (a) the electron current flowing in the MOS channel (ZMos), (b) the electron current arising as a result of the action of the shunted NPN transistor (Ici), and (c) the total hole current (I,,) collected in the P-base region of the IGBT segment (this is the sum of the hole currents arising as a result of the action of the vertical PNP transistor (I,,,) and the hole current flowing in
the P-base region below the N + emitter in the IGBT segment (I,,,,)). Hence, the cathode current (Ik) can be written as;
IK = IMOS + I,, + A. (2)
Since, the current flowing in the gate electrode (IG) is zero during steady state operation;
IA = 1MOS + Ic, + lh. (3)
Since IA is the emitter current of the PNP transistor, the hole current collected at the P-base region (collector of the PNP transistor) is given by;
Ih = %dA, (4)
where mpNp is the current gain of the PNP transistor. From eqns (2) and (3);
MOS ‘A=(, f
GNP) + (1 -%:,,P,~ (5)
Let Ihb be the hole current flowing in the base region of the shunted NPN transistor. The collector current Ic, is then related to the base current Ihh by:
&!PN,S hb ICI = (1 - &$ (6)
where aNPN,S is the current gain of the shunted NPN transistor. From eqn (5) and (6);
IA = (1 MOS CINPNSlhb
f ClPNP) + (1 - c&vP)(l - c(,VP,“,s)’ (7)
with ZMos given by;
These equations describe the output characteristics of the DC-EST including the effect of activation of the NPN transistor in the IGBT section. Note that as aNPN,S approaches zero, the second term in eqn (7) can be neglected and we get an expression identical to the one previously derived for an IGBT (eqn 1) under current saturation[l 11. In a DC-EST under current saturation, hole current is collected in the P-base regions of the main thyristor and IGBT segments. When the shorting distance between the P-base region of the main thyristor segment and the cathode is increased, the resistance Rel for holes in this path increases. Thus, the total hole current collected in the IGBT segment (Ihb) increases, resulting in a larger base drive current for the shunted NPN transistor. The increased base drive current increases the current gain (aNpNg) of the shunted NPN transistor making the second term in eqn (7) more significant with increasing &,. Based upon this argument, the saturated current should increase with increasing Rel. This was observed in numerical simulations as shown later. In addition, apNp increases with increasing anode bias caused by an increase in the base transport factor of the PNP transistor caused by a reduction in the undepleted N-base width. Consequently, Ihh increases with an increase in the anode voltage. This
1136 S. Sridhar and B. J. Baliga
Gate
Distance (Microns)
Fig. 3. Current flowlines during high voltage current saturation in a DC-EST at an applied anode bias of 30 V. The gate bias applied is 3.7 V.
implies that the base drive current of the NPN transistor increases with increasing anode bias resulting in a corresponding increase in c+,PN.S. From the second term in eqn (7) it can be concluded that an increase in uNrN.S will lead to an increase in IA. This leads to the conclusion that the saturated anode current will increase with increasing anode bias caused by activation of the NPN transistor resulting in a reduction of the output resistance. The design rules used during the design and layout determine the value of Re2 (shown in Fig. 1). For tighter design rules (smaller L in Fig. I), RB2 will be smaller and for larger design rules (larger L in Fig. 1) RB2 is larger. As the gain of the shunted NPN transistor (cQ,~~,~) is determined by the potential drop across RB2, the transistor gets activated at smaller values of Ihb for larger values of Re2.
4. VERIFICATION OF MODEL
To verify the dependence of the output character- istics on the distant between emitter shorts (or the resistance Rel of the P-base region) in the main thyristor segment, extensive two-dimensional numeri- cal simulations were carried out using MEDICI. The device structure of the simulated DC-EST had a floating emitter length of 15 pm, a gate length of 8 pm, and a gate oxide thickness of 500 A. To account for the distance between emitter shorts, an
external resistance Rsl was used to emulate the resistance in the P-base region. The N-drift region thickness and doping were 50 pm and 1 x lOI4 cm-‘, which gave a blocking voltage of 700 V. The peak surface concentrations of the N+ emitter, P-base and P+ were I x 1020cm-3, 5 x 10’7cm-3 and the junction depths were 1 pm, 3 pm and 5 p respectively. The buffer region had a concentration of 5 x 1Or6 cm-3 and a thickness of 10 pm. A high level lifetime of 2 ps was used in the simulations.
During high voltage current saturation, holes injected into the drift region are partly collected in the P-base region of the main thyristor and partly in the P-base region of the IGBT segment as is seen in the current flowlines in Fig. 3. When the value of the external resistance Rel was increased, it was found that the hole current flowing in the P-base region of the IGBT segment increases. This results in an increase in the saturated anode current and consequently a large reduction in the output resistance. This behaviour is consistent with the predictions of the analytical model described in the previous section.
In order to quantitatively verify the analytical model, IA was calculated analytically for DC-EST structures and compared with the IA values obtained through measurements as shown in Fig. 2. In order to analytically calculate IA, values of awpN.s, aPnP, Ihb and IMos are needed. At any given anode voltage,
Output characteristics of the dual channel EST 1137
--,..‘.,..‘.,‘.. -17 I.. ‘.
-Sinrulated NRN with L=O.Eum /
_ _ _ SimDllated NPN with L=hnn
X EJQ. Data for low Rn, and L=O.Eum
m Exp. Data for 1arrJe RR, and L=2um
I,,~ (Amps/micron) x 1W5
Fig. 4. Plot of CZ,W.S vs Ihb for two different values of RW obtained from simulations.
the current gain (apNp) of the PNP transistor is
independent of the value of RBI and can be obtained
using the known lifetime, the width of the N-base
region, and the injection efficiency of the emitter.
However, aNPN.s cannot be analytically calculated without accurate knowledge of Zhb which is a distributed current. Hence Zhb was obtained by two-dimensional numerical simulations for each operating point. Figure 4 shows a plot of the gain of the shunted NPN transistor (aNPNsS) as a function of the base drive current (Zhb) obtained by two-dimensional numerical simulations performed on the shunted NPN transistor. As expected[l2], the gain of the shunted NPN transistor is “0” at low values of Zhb and increases rapidly beyond a certain value of Zhb. The value of Zhb at which the gain increases rapidly is larger for a device with smaller L because of its smaller shunt resistance. Z,,b was obtained from numerical simulations on the DC-EST structure for each operating point and the value of uNPN,S corresponding to that value of Zhb was then obtained from Fig. 4.
The experimentally obtained Z-V data under current saturation at a gate bias of 3.5 V for a DC-EST design with 700 V blocking capability (structure 1) is compared with the analytically calculated output characteristic under the same bias conditions in Fig. 2. The two show excellent agreement in the region of saturation validating the
model. Also plotted in Fig. 2 is the previous model (eqn (1)) which does not take into account the activation of the NPN transistor. As can be seen in Fig. 2, the previous model (eqn (1)) is inadequate in predicting the output characteristics, while the proposed model shows excellent agreement with the measured characteristics.
From eqn (7) it is evident that the output characteristics improve if mNpN,s approaches zero. In order to verify this behavior, DC-ESTs were designed and fabricated with tighter design rules (L = 0.8 pm) and a smaller Rs, (shorting distance of 100 am) (structure 2). In Fig. 2 the experimentally measured output characteristics for structure 2 are shown for the same gate bias of 3.5 V. It can be seen that the output resistance for structure 2 in much larger than that for structure 1 because of the suppression of the activation of the NPN transistor in structure 2. In structure 2, the NPN transistor is not activated because of (a) a smaller base drive current Zhb resulting from the smaller value of Rsl and (b) a lower value of RB2 which shifts the activation of the NPN transistor to higher values of Zhb (in the vicinity of point Y in Fig. 4). Thus this design shows good output characteristics. In contrast, the higher value of Rel for structure 1 shifts Zhb to a higher value in Fig. 4 (in the vicinity of point X) and the higher value of RB2 moves the current gain curve to the left hand side. Thus, in this case, the NPN transistor gets activated
1138 S. Sridhar and B. J. Baliga
more easily resulting in a degradation of the output characteristics.
5. FORWARD BIASED SAFE OPERATING AREA (FBSOA)
A reduction in the output resistance corresponds to a more rapid increase in the anode current with increase in the anode voltage in the current saturation region. As in the case of IGBTs, the parasitic thyristor of the DC-EST latches up when the anode current density reaches a fixed level. Thus a reduction in the output resistance results in the latch-up of the parasitic thyristor at lower anode voltages. Conse- quently, the FBSOA of the DC-EST becomes limited by the output resistance. Based upon the analysis presented in this article, it can be concluded that the FBSOA of the DC-EST will depend on the distance
between emitter shorts in the main thyristor segments and the design rules used in the layout. This is of great importance from the point of view of designing DC-ESTs for hard switching, inductive load
applications.
6. CONCLUSIONS
A model for the dependence of the output characteristics of the DC-EST on the resistance in the P-base region of the main thyristor segment and the design rules used for the layout has been proposed and verified by relating the degradation in the output resistance to the activation of the NPN transistor in the IGBT segment. An analytical model was
developed which relates the degradation in the output characteristics to an increase in the shorting distance of the P-base region of the main thyristor segment to the gain (aNPN,s ) of the NPN transistor in the IGBT segment. The analytical model has been verified by 2-dimensional numerical simulations and bolstered with measured data. The deterioration in the output characteristics was shown to result in poor FBSOA in the DC-EST.
AcknoM,ledgemenls-The authors wish to thank the sponsors of the Power Semiconductor Research Center (PSRC) for their support and Technology Modelling Associates (TMA) for providing the use of MEDICI, the 2-dimensional numerical simulator used in this study.
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