Outline - eit.lth.se · Pieter Harpe TU/e Outline Introduction Selected literature examples (1997 2017) Detailed design examples A 1nW 1kS/s 10bit SAR ADC An oversampled 12/14b SAR

Advanced SAR ADCsEfficiency, Accuracy, Calibration & References

Pieter Harpe

Eindhoven University of TechnologyEindhoven The Netherlands

Pieter Harpe TU/e

Outline

Introduction

Selected literature examples (1997 2017)

Detailed design examples

Conclusions & Outlook

2

Pieter Harpe TU/e

Outline

Introduction




3 Pieter Harpe TU/e

ADC Architectures over Time

C. Hammerschmied, Q. Huang 1 m CMOS 10b, 200kS/s 109pJ/conv.step

4

Data from B. Murmann,Performance

Survey

S.-E. Hsieh, C.-C. Hsieh 90nm CMOS 11b, 600kS/s 0.4fJ/conv.step

SAR: rapid development during last decade

Pieter Harpe TU/e

Power Efficiency over Time

5


Survey

SAR: leading in efficiencyPieter Harpe TU/e

Speed Resolution Landscape

6

SAR ADCs

+ time-interleaving

+ pipelining

+ Delta-Sigma / noise-shaping


Survey

SAR(-based): efficient & large application space

Pieter Harpe TU/e

Outline

Introduction




7 Pieter Harpe TU/e 8

ISSCC 1997 Hammerschmied, Huang: 10b 20kS/s SAR ADCMOSFET-based R-2R DAC for linearity

ISSCC 2002 Kuttner: 10b 20MS/s SAR ADCSwitched-Capacitor DAC, introduction of redundancy (non-binary array)

ISSCC 2004 Draxelmayr: 6b 600MS/s time-interleaved SAR ADCTime-interleaving

ISSCC 2006 Verma, Chandrakasan: 12b 100kS/s SAR ADCW level design, resolution adaptability

ISSCC 2007 Craninckx, Van der Plas: 9b 0-50MS/s SAR ADCCharge-sharing DAC; Dynamic circuitry (power-speed adaptability)

ISSCC 2008 van Elzakker, et al.: 10b 1MS/s SAR ADC4.4fJ/conversion-step, adiabatic DAC, efficient comparator, asynchronous timing

Pieter Harpe TU/e

Low Power SAR ADCs

Minimize power & Maximize SNR / linearity

9

Comparator- Noise

DAC- Mismatch- Resolution

Circuit Algorithm Calibration,Error-shaping

Layout,Switching scheme

Pieter Harpe TU/e

Comparator: Efficient Circuits

10

van Elzakker, et al.(ISSCC 2008)

Liu, et al.(ISSCC 2015)

Bindra, et al.(ESSCIRC 2017)

Pieter Harpe TU/e

Comparator: Efficient Algorithms

Redundancy: relax comparator in most cycles

2 comparators Giannini, et al. (ISSCC 2008)1 comparator, 2 modes Harpe, et al. (ISSCC 2012)

Oversampling or noise-shapingNoise shaping Fredenburg, Flynn (ISSCC 2012)Selective oversampling Harpe, et al. (ISSCC 2013)Adaptive averaging Morie, et al. (ISSCC 2013)

11

Coarse (N k) Fine (k + 1)(with over range)

Pieter Harpe TU/e

DAC: Switching SchemesSplit capacitor switchingGinsburg, et al. (VLSI 2006)Monotonic capacitor switchingLiu, et al. (JSSC Apr. 2010)Merged capacitor switchingHariprasath, et al. (E. Let. Apr. 2010)Vcm-based switchingZhu, et al. (JSSC June 2010)Charge average switchingLiou, et al. (ISSCC 2013)Detect-and-skip, aligned switchingTai, et al. (ISSCC 2014)Swap-to-resetLiu, et al. (ESSCIRC 2016)

etcEspecially useful for higherresolutions (larger CDAC)

12

VREF GND

C0C1C2b0b1b2

Different bit transitions Different energye.g. 011 to 100 transition = costly

Pieter Harpe TU/e

DAC: Capacitor Implementation

kT/C noise limit (ignoring mismatch):

<10b ADCs usually overdesigned>10b ADCs require a lot of units and large Ctotal

13

# bits Ctotal Cunit

6 0.2fF 3aF8 3.3fF 13aF

10 52fF 51aF12 0.8pF 0.2fF14 13pF 0.8fF16 0.2nF 3.2fF

Assumptions0.5V signal amplitude (1Vpp),kT/C noise = quantization noise,Ctotal = 2N Cunit

MIMCAPArea inefficientCmin usually > 2fF

MOMCAPArea efficientEasy to wire in arrayCmin < 0.5fF

Harpe, et al.(ISSCC 2010 /JSSC Jul. 2011)

Pieter Harpe TU/e

DAC: Mismatch Non-Linearity

Calibration: measuring and correcting errors

Rotation / DEM / Mismatch error shaping

14

VREF GND

C0C1C2b0b1b2

Ding, et al. (ISSCC 2015)

Digitalcalibration

loop

VREF GND

C0C1C2b0b1b2

Rotation: Distortion NoiseLiu, et al. (ESSCIRC 2016)

1 Z-1 error shapingShu, et al. (ISSCC 2016)

Pieter Harpe TU/e

Outline

Introduction


Detailed design examplesA 1nW 1kS/s 10bit SAR ADCAn oversampled 12/14b SAR ADCA 13b SAR ADC with background calibrationA 10b SAR ADC with a DAC-compensated reference

Conclusions & Outlook15 Pieter Harpe TU/e

10bit SAR ADC

Based on ADC architecture as in [1]Self-synchronized ADC Only need clock at 1kS/sClock boosting Linearity & low-voltage operationDynamic circuits only Power scales down with Fsample

HVT devices, return-to-standby Lower leakage0.6V operation

16[1] Harpe, ISSCC 2013

Pieter Harpe TU/e

10bit DAC Design

Small unit caps, custom design (250aF)Total Cin = 300fF (with parasitics)

3b Unary / 7b Binary segmentationImproves power and DNL

17

7b binary3b unary

Pieter Harpe TU/e

Binary:

Unary:

Impact of Unary/Binary Segmentation

Less switching elements lower power and DNLNote: advantage depends on switching scheme

18

1 1 1 1 1 1 1

4 2 1

4

2

Code

Code6 switchingelements

Code

Code2 switchingelements

1 1 1 1

1 1

Pieter Harpe TU/e

Comparator: Efficient Pre-amplifier

19

van Elzakker, et al.(ISSCC 2008)

Liu, et al.(ISSCC 2015)

Pieter Harpe TU/e

Digital Logic: Low-Speed Operation

Technology scalingActive power , Leakage power

Power at low speed limited by leakageOptimized by: Low VDD, high Vt transistorsReduce number of gates in the logicManual design rather than synthesized logic

20

Operating speed

Pow

erco

ns. Pdynamic

Pshort-circuit

Pleakage

Pieter Harpe TU/e

Die Photo in 65nm CMOS

0.2mm2, excluding pads,including supply decouplingNo external componentsSingle 0.6V supply

21 Pieter Harpe TU/e

Static ADC Measurements

INLmax = 0.87LSB, DNLmax = 0.96LSB

22

Pieter Harpe TU/e

Dynamic ADC Measurements

Measured at 100kS/s (max. ADC rate @ 0.6V)

ENOB 9.2bitup to Nyquist


ADC Power MeasurementsDynamic power consumption

Leakage 0.15nWDAC is about 20% of total power consumption

Power efficiency1.5fJ/conversion-step at 100kS/s1.7fJ/conversion-step at 1kS/s

24

88nW @ 100kS/s

1nW @ 1kS/s

Pieter Harpe TU/e

Outline

Introduction




12/14b SAR ADC for Sensors in IoT

Challenges & solutions

Final result: SNDR 79.1dB, SFDR 87.1dB

Harpe, et al. (ISSCC 2014)

26

White Noise 1/f Noise MismatchData-Driven

Noise ReductionOversampling

Chopping

Dithering

Pieter Harpe TU/e

SAR ADC Core Architecture

Supports 12 & 14-bit resolutionSingle 0.8V supply / referenceSelf-synchronized (requires clock @ fsample only)Max. sample rate of 128kS/s


14b Charge Redistribution DAC

9pF per side for 85dB kT/C-SNR14b resolution: 4b unary MSBs + 10b binary LSBs

28

Pitch = 0.4 m

Layout units of1.1, 2.2, 4.4 and 8.8fF

Bit T<14..0> B<9..4> B<3> B<2> B<1> B<0>Unit 8.8fF 8.8fF 4.4fF 2.2fF 1.1fF 1.1fF

#Units 64 (15X) 32, 16, 8, 4, 2, 1 1 1 1 ½

Pieter Harpe TU/e

Oversampling

4X oversampling (i.e. 4X power) +6dB SNRHelps for thermal noise and quantization noise,but not for 1/f noise or distortion

29

fsample/2

fsample

Nyquist-rate

4X OSR

noise

noise

signal

signalfsample = 4fsample

Pieter Harpe TU/e

System Level Chopping

fchop = fsample / 2Negligible power/area overhead

30

Pieter Harpe TU/e

Chopping Result

1/f noise and distortion modulated with fchop

fchop = ½ fsample and OSR 2X1/f noise and even-order HD out of baseband

31

fsample/2

Without chopping

fsample/2

With chopping

Baseband for OSR = 2X

distortionsignal

1/f noise

Pieter Harpe TU/e

Majority Voting

Analog scaling: 4x Ecmp 2x lower Vnoise

Digital majority voting (oversampling / averaging):Repeat the same comparison k times (10110)Majority voting on k samples to decide ( 1)Effectively reduces input-referred noiseMajority-voting on 5 samples 4x analog scaling

32

Vin

Vnoise

Vin

Output probability

0

1P1P0

0 0

Vnoise

Ecmp

Pieter Harpe TU/e

Data-Driven Noise Reduction (DDNR)

Only a few comparator decisions are noise criticalSelective majority voting for critical cases only

How to detect these cases?

33

<0.5LSB

Comparator inputas function of time

Pieter Harpe TU/e

Comparator Decision Time

Not noise criticalNoise critical

34

Input signal

Comparator decision time

not to scale

d

d

Pieter Harpe TU/e

DDNR Time-Domain Behavior


Feedback-Controlled DDNR

36

Analog Digital

Numberof votes

Thresholdfor voting

Pieter Harpe TU/e

Die Photo, 65nm CMOS

37

Total area: 0.18mm2

Area includes supply/reference decoupling caps

Pieter Harpe TU/e

Measured INL/DNL Nyquist Modes

38

12bit mode

14bit mode

Pieter Harpe TU/e

Effect of Chopping, Dithering and DDNR

14b mode, 128kS/s, 16X OSR, fin = 169.22Hz

39

Techniques disabled

Techniques enabled

Pieter Harpe TU/e

ADC Performance Summary

40

[1] Harpe, ISSCC2013 [2] Liou, ISSCC2013 [3] Perez, ISSCC2011

Pieter Harpe TU/e

Outline

Introduction




6.4MS/s 13b SAR ADC in 40nm CMOS

ULP radio receiver

Problem:13b intrinsic linearity Power and area hungryCalibration Often also power and area hungry

Goal:

Power/Area-efficient background calibrationComparator offset & DAC mismatch

42

Ding, et al. (ISSCC 2015, JSSC Feb. 2017)

Pieter Harpe TU/e

13b ADC Architecture

Asynchronous operation15 cycles for 13b output (2b redundancy)

One optional cycle (16th) for calibration

43

2048, 1024, 512, 256, 128, 64

64, 32, 16, 8

8, 4, 2, 1

Pieter Harpe TU/e

DAC Mismatch Error Correction

Correction step size: 0.25LSB (75aF)

Analog correction Low power, low area

44

1024 LSB2 0.5 0.25

Pieter Harpe TU/e

DAC Mismatch Error Detection

45

Binary array

A = B + 1 LSBCA = CB + CLSB +

2048, 1024, 512, 256, 128, 64

64, 32, 16, 8

8, 4, 2, 1

With redundancyCode A: 100000 +Code B: 011111 +CA = CB +

Pieter Harpe TU/e

DAC Mismatch Error Detection

If code A is detected @ 15th cycle, then:16th cycle is performed, repeating 15th cycle, but:

DAC code is switched from A to BSign of the error is determined by C15C16

46

code A ( code B (

Comparator outputs:

Pieter Harpe TU/e

Detailed 13b ADC Architecture

47

Comparator correctionDAC mismatch correction

Detection Only sign detection necessaryBackground, low activation rateAnalog correction = low power

Pieter Harpe TU/e

Die Photo and Power Breakdown

Calibration is low cost4% of chip area5% of power consumption

48

500 m 135 m

Calibration logic

Pieter Harpe TU/e

Code

With comparator and DAC calibrations

Code

INL(

LSB)

DN

L(LS

B)S&H non-linearity

Measured Static Performance

49

Without calibrationIN

L(LS

B)

DN

L(LS

B) Comparatoroffset error

With comparator calibration only

INL(

LSB)

DN

L(LS

B)DAC mismatch error

Pieter Harpe TU/e

Measured Spectrum @ 6.4MS/s

50

Without calibration

Pow

er(d

BFS)

With comparator calibration only

Pow

er(d

BFS)

Spurs due to DAC mismatch

With comparator and DAC calibrations

Pow

er(d

BFS)

HD3 due to S&H distortion

20dB

Input Frequency (MHz)

Pieter Harpe TU/e

ADC Performance Benchmark

All ADC papers in ISSCC/VLSI 1997-2014 with fs > 1MS/sSource: http://web.stanford.edu/~murmann/adcsurvey.html

51

5.5fJ/c.s

Pieter Harpe TU/e

ADC Performance Summary[2] [4] [5] [8] This

workTechnology (nm) 130 28 28 65 40Resolution (bit) 12 14 14 14 13Sample rate (MS/s) 22.5 200 80 0.032 6.4Power (µW) 2790 2300 1500 0.352 46Nyquist SNDR (dB) 70.11 65 66 69.7 64.1FOMW_Nyq. (fJ/c.s) 50.8 7.9 11.5 4.4 5.5FOMS_Nyq. (dB) 165.9 171.4 170.3 176.3 172.5Calibration Off-chip Off-chip On-chip N.A. On-chipCal. Circuit Area (mm2) 0.01* Not incl. Included N.A. 0.0026Cal. Circuit Power (µW) 200* Not incl. Included N.A. Included

52

*Estimated

Pieter Harpe TU/e

Outline

Introduction




SAR ADC is Energy-

Reference buffer required for the DACCan be significant in chip area (A) or powerconsumption (P)

0

1

2

3

4

5

[9] C.-C. Liu, et al., JSSC 2016

[8] M. Inerfield, et al., VLSI 2014

[7] W.-H. Tseng, et al., JSSC 2016

Aref buf /AADC

Pref buf /PADC

54

Liu, et al. (ESSCIRC 2017)

Pieter Harpe TU/e

Charge-Redistribution DAC


Reference Buffer

56

Pieter Harpe TU/e

Passive Driving by CDEC

Large CDEC Approximates ideal binary search

Smaller CDEC Non-binary DistortionCan be solved with DAC compensation


DAC-Compensated ReferenceIf CDEC is not largeVREF,DEC drops and depends on the code (Di)

DAC compensationCode-dependent VREF Non-binary scalingBinary scaling

58

Pieter Harpe TU/e

Pre-Charging CDEC


Tradeoff: SNDR gain vs Complexity (10b)

2 3 4 5 6 7 8 940

50

60

70

No. of compensation bit

10

100

1k

60

Pieter Harpe TU/e

ADC with 3b Compensation DAC

VINP

VINN

Bootstrap switches DOUT<9:0>SARlogic

9b binary DAC

CompensationDAC for 3 MSBs

Comp.logic

Pre-charger

VDDA(1V)

CDEC(20x CT)

VDDD(0.8V)

VREF(0.9V) VREF, DEC

(0.9V)

Clock

VDACP

VDACN


Compensation DAC for 3MSBsCompensation capacitors:

MSB requires no compensation (code-independent loss)MSB-1 compensation depends on first 2 decisions (00, 01, 10, 11)Calculated analytically with extracted parasitic informationSame capacitor type as the DAC array for matchingTotal compensation capacitance ~1% CT Low power + small area

VDACP

GND

VDACN

VREF

C011 C101

VREF

GND

C01 C10 C11 C00

C01 C10 C11 C00

C001 C111

Compensation for the2nd switching step

C100 C010 C110 C000

Compensation for the 3rd

switching step

C011 C101 C001 C111C100 C010 C110 C000

C1 C2

9b binary DAC

C1

C1

C1 C2

C2

C2

62

Pieter Harpe TU/e

Die Photo in 65nm CMOS

CDEC, pre-charger and DAC-compensationAdd 10.1% chip area to the SAR ADCCDEC takes most of this 10.1%

150µm 40µm

275µm

3b CompensationDAC

CDEC+pre-charger

Compensationlogic


Dynamic Performance @20MS/sBy enabling DAC compensation

+2.7dB SNDR / +11.6dB SFDRPower consumption 151 W, FoM of 15.7fJ/c.s.

0.0 5.0M 10.0M-100

-50

0 3b compensationSNDR=55.4dBSFDR=68.2dB

No compensationSNDR=52.7dBSFDR=56.6dB

Frequency (Hz)64

Pieter Harpe TU/e

Static PerformanceWithout and with DAC compensation

0 1023-20246

[-1.0LSB, 3.3LSB][-1.0LSB, 5.0LSB]

Code

0 1023-5

0

5

[-3.2LSB, 3.2LSB]

[-4.2LSB, 4.2LSB]

Code

0 1023-2-1012 No comp.

Code

0 1023-2-1012 3b comp.

Code

0 1023-2-1012 6b comp.

Code

0 1023-2-1012 9b comp.

Code

Behavioral simulationsChip measurements


Power and Area Overhead

CDEC, pre-charger and DAC compensation:10.8% more power to the SAR ADC10.1% chip area to the SAR ADC

0

1

2

3

4

5

This work

Aref buf /AADC

Pref buf /PADC

[9] C.-C. Liu, et al., JSSC 2016

[8] M. Inerfield, et al., VLSI 2014

[7] W.-H. Tseng, et al., JSSC 2016

66

Pieter Harpe TU/e

ConclusionsA passive DAC-compensated driving scheme is proposed

Continuous-time buffer Duty-cycled buffer Low powerDAC compensation enables small CDEC Small areaCombines the advantages of CR and CS DACs:

DACarchitecture

Precision(noise,

parasitics)

Usereference

buffer

Buffer cost(area & power)

Charge-redistribution Simple Good Frequently High

Charge-sharing Complex Poor Only during

tracking Low

This work Simple Good Only duringtracking Low


Outline

Introduction




68

Pieter Harpe TU/e


Techniques for low-power / noise / linearityMany different solutions (circuit, algorithm, A / D)Still substantial progress; not yet at fundamental limits

OutlookRecent years show a shift to SAR-based rather thanpure SAR ADCs (more speed, more resolution)Simple SAR ADCs excellent for ~6-12b, DC-100MS/sMore attention needed for surrounding circuits


Acknowledgement

Special thanks to

Ming Ding & Maoqiang Liu

for their contributions to this presentation

70

Documents

Outline - eit.lth.se · Pieter Harpe TU/e Outline Introduction Selected literature examples (1997 2017) Detailed design examples A 1nW 1kS/s 10bit SAR ADC An oversampled 12/14b SAR