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OULU 2016

C 565

Pekka Keränen

HIGH PRECISION TIME-TO-DIGITAL CONVERTERS FOR APPLICATIONS REQUIRINGA WIDE MEASUREMENT RANGE

UNIVERSITY OF OULU GRADUATE SCHOOL;UNIVERSITY OF OULU,FACULTY OF INFORMATION TECHNOLOGY AND ELECTRICAL ENGINEERING;INFOTECH OULU

C 565

ACTA

Pekka Keränen

C565etukansi.kesken.fm Page 1 Wednesday, March 9, 2016 2:10 PM

A C T A U N I V E R S I T A T I S O U L U E N S I SC Te c h n i c a 5 6 5

PEKKA KERÄNEN

HIGH PRECISION TIME-TO-DIGITAL CONVERTERS FOR APPLICATIONS REQUIRING A WIDE MEASUREMENT RANGE

Academic dissertation to be presented with the assent ofthe Doctoral Training Committee of Technology andNatural Sciences of the University of Oulu for publicdefence in the OP auditorium (L10), Linnanmaa, on 15April 2016, at 12 noon

UNIVERSITY OF OULU, OULU 2016

Copyright © 2016Acta Univ. Oul. C 565, 2016

Supervised byProfessor Juha Kostamovaara

Reviewed byDoctor Ryszard SzpletProfessor Kari Halonen

ISBN 978-952-62-1150-3 (Paperback)ISBN 978-952-62-1151-0 (PDF)

ISSN 0355-3213 (Printed)ISSN 1796-2226 (Online)

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JUVENES PRINTTAMPERE 2016

Keränen, Pekka, High precision time-to-digital converters for applicationsrequiring a wide measurement range. University of Oulu Graduate School; University of Oulu, Faculty of Information Technologyand Electrical Engineering; Infotech OuluActa Univ. Oul. C 565, 2016University of Oulu, P.O. Box 8000, FI-90014 University of Oulu, Finland

Abstract

The aim of this work was to develop time-to-digital converters(TDC) with a wide measurementrange of several hundred microseconds and with a measurement precision of a few picoseconds.Because of these requirements, the focus of this work was mainly on TDC architectures based onthe Nutt interpolation method, which has several advantages when a long measurement range is arequirement.

Compared to conventional data converters the characteristics of a Nutt TDC differ significantlywhen, for example, quantization errors and linearity errors are considered. In this thesis, theoperating principle of a Nutt TDC is analysed and, in particular, the effects of reference clockinstabilities are studied giving new insight how the different phase noise processes can be reliablytranslated into time interval jitter, and how these affect the measurement precision when very longtime intervals are measured. Furthermore, these analytical results are confirmed by measurementsconducted with a long-range TDC designed as part of this work.

Two long-range TDCs have been designed, each based on different interpolator architectures.The first TDC utilises discrete component time-to-voltage converters(TVC) as interpolators.Other key functionality is implemented on an FPGA. The interpolators use Miller integrators toimprove the linearity and the single-shot precision of the converter. The TDC has a nominalmeasurement range of 84ms and it achieves a single-shot precision of 2ps for time intervals shorterthan 2ms, after which the precision starts to deteriorate due to the phase noise of the referenceclock.

In addition to the discrete TDC, an integrated long-range CMOS TDC has been designed with0.35μm technology. Instead of TVCs, this TDC features cyclic/algorithmic interpolators, whichare based on switched-frequency ring oscillators(SRO). The frequency switching is used as amechanism to amplify quantization error, a key functionality required by any cyclic or a pipelineconverter. The interpolators are combined with a 16-bit main counter giving a total range of 327μs.The RMS single-shot precision of the TDC is 4.2ps without any nonlinearity compensation.Furthermore, a calibration functionality implemented partially on-chip ensures that the accuracyof the TDC varies only ±2.5ps in a temperature range of -30C to 70C. Although implemented withfairly old technology, the interpolators’ effective linear range and precision represent state-of-the-art performance.

Keywords: clock jitter, phase noise, switched-frequency ring oscillator, time intervalmeasurement, time-to-digital converter, time-to-voltage converter

Keränen, Pekka, Korkean tarkkuuden aika-digitaalimuuntimia laajan mittausalueenvaativiin sovelluksiin. Oulun yliopiston tutkijakoulu; Oulun yliopisto, Tieto- ja sähkötekniikan tiedekunta; InfotechOuluActa Univ. Oul. C 565, 2016Oulun yliopisto, PL 8000, 90014 Oulun yliopisto

Tiivistelmä

Tämän työn tavoitteena oli kehittää aika-digitaalimuuntia (TDC), joilla on laaja satojen mikrose-kuntien mittausalue ja muutaman pikosekunnin kertamittaustarkkuus. Näistä vaatimuksista joh-tuen tässä työssä keskitytään pääasiassa Nuttin interpolointimenetelmään perustuviin TDC-ark-kitehtuureihin.

Verrattuna tavanomaisiin datamuuntimiin, Nutt TDC:n toiminta poikkeaa merkittävästi, kuntarkastellaan kvantisointi- ja lineaarisuusvirhettä. Tässä väitöskirjatyössä Nuttin menetelmäänperustavan TDC:n toiminta analysoidaan, jonka yhteydessä tutkitaan erityisesti referenssioskil-laattorin epästabiilisuuksien vaikutusta mittausepävarmuuteen. Tämän pohjalta vaihekohinan erikohinaprosessit voidaan luotettavasti muuntaa taajuustason kohinatiheysmittauksista aika-tasos-sa kuvattavaksi aikavälijitteriksi. Nämä teoreettiset tulokset ovat varmistettu yhdellä osana tätätyötä suunnitellulla pitkän kantaman TDC:llä.

Teoreettisen tarkastelun lisäksi kaksi pitkän kantaman TDC:tä on suunniteltu, toteutettu jatestattu. Ensimmäinen näistä perustuu erilliskomponenteilla toteutettuun aika-jännitemuunnok-seen (TVC) pohjautuvaan interpolointimenetelmään. Analogisten interpolaattoreiden ohella muuolennainen toiminnallisuus toteutettiin FPGA:lle. Interpolaattorit käyttävät Miller-integraattorei-ta lineaarisuuden ja kertamittaustarkkuuden parantamiseksi. TDC:n nimellinen mittausalue on84ms ja sillä saavutetaan 2ps:n kertamittaustarkkuus, kun mitattava aikaväli on lyhyempi kuin2ms, minkä jälkeen mittaustarkkuus heikkenee referenssioskillaattorin vaihekohinan vaikutuk-sesta.

Toinen pitkän kantaman TDC perustuu 0.35μm:n CMOS teknologialla totetutettuun integroi-tuun piiriin. Aika-jännitemuunnoksen sijasta tämä TDC perustuu sykliseen/algoritmiseen inter-polointitekniikkaan, jossa taajuusmoduloitua rengasoskillaattoria(SRO) käytetään kvantisointi-virheen vahvistamiseksi. Interpolaattorit ovat yhdistetty 16-bittiseen referenssioskillaattorin las-kuriin, jolloin TDC:n mittausalue on noin 327μs. Tämän TDC:n RMS kertamittaustarkkuus on4.2ps, joka saavutetaan ilman epälineaarisuuden kompensointia. Samalle piirille on lisäksi toteu-tettu kalibrointitoiminnallisuus, jolla varmistetaan TDC:n hyvä mittaustarkkuus kaikissa olosuh-teissa. Mittaustarkkuus poikkeaa maksimissaan vain ±2.5ps, kun lämpötila on välillä -30C-70C.Vaikka TDC on toteutettu kohtalaisen vanhalla CMOS teknologialla, interpolaattoreiden efektii-vinen lineaarinen alue ja mittaustarkkuus edustavat alansa huippua.

Asiasanat: aika-digitaalimuunnin, aika-jännitemuunnin, aikavälimittaus, kellojitter,rengasoskillaattori, vaihekohina

Acknowledgements

The work presented in this thesis is the result of research work carried out at theElectronics Laboratory of the Department of Electrical Engineering, University of Oulu,Finland, during the years 2010-2015.

I wish to express my gratitude to the supervisor of this work, Professor JuhaKostamovaara, for offering me the opportunity to work in his research group and for allthe invaluable discussions and helpful comments related to my thesis. I would like tothank all of my colleagues at the Electronics laboratory for the helpful and pleasantwork environment. I also want to thank the reviewers of this thesis, Dr. Ryszard Szpletand Professor Kari Halonen, for their valuable and constructive feedback.

This research work has been financially supported by the Academy of Finland,Infotech Oulu Graduate School, Tekniikan edistämissäätiö, Tauno Tönningin säätiö andNokia Foundation, all of which are gratefully acknowledged.

I would like to thank my parents, Raija and Eino, and my sisters with their familiesfor the positive support during these years. I want to thank my friends for other activitiesand giving me something else to do and think than just work.

Last, but most importantly, I want to express my deepest gratitude to my wife, Outi,for the encouragement, support and understanding during my doctoral studies.

Oulu, February 2016 Pekka Keränen

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Abbreviations

ADC Analog-to-Digital ConverterADPLL All-Digital Phase-Locked LoopCMOS Complementary Metal–Oxide–SemiconductorDAC Digital-to-Analog ConverterDCO Digitally Controlled OscillatorDNL Differential NonlinearityDTC Digital-to-Time ConverterFWHM Full Width at Half MaximumFPGA Field-Programmable Gate ArrayGRO Gated Ring OscillatorINL Integral NonlinearityLDPC Low-Density Parity-CheckOCXO Oven Controlled Crystal Oscillatorppm Parts Per MillionPECL Positive Emitter-Coupled LogicPSD Power Spectral DensitySAR Successive Approximation RegisterSNR Signal-to-Noise RatioSPAD Single-Photon Avalanche DiodeSQNR Signal-to-Quantization-Noise RatioSRO Switched(-frequency) Ring OscillatorTAC Time-to-Amplitude ConverterTCXO Temperature Compensated Crystal OscillatorTDC Time-to-Digital ConverterToF Time-of-FlightTVC Time-to-Voltage ConverterVTC Voltage-to-Time Converter

L ( f ) Sideband power spectral density below carrierA AmplitudeC Capacitancecx(n) Nth fourier coefficient for a signal x

9

F Fractional part of a normalized time intervalgm Small-signal transconductanceI Currenti2n Current noise powerINLst Integral nonlinearity error of a start channel interpolatorINLsp Integral nonlinearity error of a stop channel interpolatorK Capacitance/current ratio of an analog time-stretcherQ Integer part of a normalized time intervalQst Quantization error of a start channel interpolatorQsp Quantization error of a stop channel interpolator∆Q Quantization stepr Small-signal resistanceRx(τ) Autocorrelation of a variable x with a lag τ

S( f ) Two-sided power spectral densityS1s( f ) One-sided power spectral densityTre f Period of a reference oscillator∆T Time interval∆TFS Full-Scale time-interval∆t Time interval normalized by a reference period∆tin Normalized input time interval∆tstart Normalized time interval measured by a start channel interpolator∆tstop Normalized time interval measured by a stop channel interpolatorVFS Full-Scale voltageVov Overdrive voltagev2

n Voltage noise powerτ Time delay/time constantφ Phase of an oscillatorµ Mean/Expected valueσ Standard deviationσrms Root-mean-square single-shot precisionσssp(F) Single-shot precision for a fractional part Fσx,y Covariance of random variables x and yx̂ Estimated value of x

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List of original publications

This thesis consists of an overview and the following five publications:

I Keränen P, Määttä K & Kostamovaara J (2011) Wide-range time-to-digital converter with1-ps single-shot precision. IEEE Transactions on Instrumentation and Measurement 60(9):3162–3172.

II Keränen P & Kostamovaara J (2013) Oscillator instability effects in time interval measure-ment. IEEE Transactions on Circuits and Systems I: Regular Papers 60(7): 1776–1786.

III Keränen P & Kostamovaara J (2013) Noise and nonlinearity limitations of time-to-voltagebased time-to-digital converters. Proc IEEE Nordic-Mediterranean Workshop on Time-to-Digital Converters (NoMe TDC). Perugia, Italy: 1–6.

IV Keränen P & Kostamovaara J (2013) Algorithmic time-to-digital converter. Proc IEEENORCHIP Conference (NORCHIP). Vilnius, Lithuania: 1–4.

V Keränen P & Kostamovaara J (2015) A wide range, 4.2ps(rms) precision CMOS TDC withcyclic interpolators based on switched-frequency ring oscillators. IEEE Transactions onCircuits and Systems I: Regular Papers 62(12): 2795-2805.

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Contents

AbstractTiivistelmäAcknowledgements 7Abbreviations 9List of original publications 11Contents 131 Introduction 15

1.1 Motivation and aim of the research . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

1.2 Thesis organisation and contribution of this work . . . . . . . . . . . . . . . . . . . . . . . . 17

2 Long range time-to-digital converters 192.1 Counter method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.2 Nutt interpolation method. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

2.2.1 Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.3 Short-range TDC as an interpolator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.4 Short-range TDC architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.4.1 Flash TDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

2.4.2 Vernier TDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

2.4.3 TDCs based on time-to-voltage converter and an ADC . . . . . . . . . . . . 32

2.4.4 TDCs based on analog time amplifiers/stretchers . . . . . . . . . . . . . . . . . 33

2.4.5 Advanced CMOS time amplifier topologies . . . . . . . . . . . . . . . . . . . . . . 34

2.4.6 Binary search/SAR TDC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

2.4.7 Interpolator structures implemented in this work . . . . . . . . . . . . . . . . . . 38

3 Outline of original publications and main contributions 393.1 Paper II, Oscillator instability effects in long range TDCs . . . . . . . . . . . . . . . . 40

3.1.1 Phase noise as a power-law PSD and sources for differentnoise processes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.1.2 Phase noise to jitter conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.1.3 Clock jitter measurements with a long range TDC . . . . . . . . . . . . . . . . 49

3.2 Paper III, Thermal noise and nonlinearity limitations of an integratedCMOS time-to-voltage converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

3.2.1 Thermal noise in a constant current integrator . . . . . . . . . . . . . . . . . . . . 55

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3.2.2 Nonlinearity due to the integrator’s finite time-constant . . . . . . . . . . . . 574 Implemented long range time-to-digital converters 61

4.1 Papers IV & V, 4.2ps(RMS) single-shot precision, 327µs rangeintegrated TDC with cyclic switched-frequency interpolators in0.35µm CMOS technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614.1.1 Time-residue amplification with switched-frequency ring

oscillators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624.1.2 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664.1.3 Cyclic interpolators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664.1.4 Digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724.1.5 Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

4.2 Paper I, 2ps single-shot precision, 84ms range discrete TDC withinterpolators based on a time-to-voltage conversion . . . . . . . . . . . . . . . . . . . . . .824.2.1 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824.2.2 TVC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854.2.3 Measurement results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

5 Discussion 915.1 Performance summary and comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92

6 Summary 97References 101Original publications 107

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1 Introduction

1.1 Motivation and aim of the research

The history of high resolution time-to-digital converters(TDC) extends back to late 1960s[1]. Some traditional applications for TDCs include, for example, time-of-flight(ToF)measurements in high-energy physics [2–5] and laser range finding [6–9]. Today,technology scaling and integrated CMOS receiver circuits have brought ToF techniquescloser to consumer level electronic devices. 3D ToF imaging techonology can be found,for example, in modern home entertainment electronic devices, such as Microsoft Kinect[10].

Although technology scaling allows to design smaller and more power efficientdigital logic devices, traditional analog circuits have not benefited as much fromthe scaling technology. However, modern CMOS TDCs, and time-mode circuits ingeneral, are essentially digital-like devices, in the sense that they are insensitive toamplitude variations and merely operate on the time/phase domain information of asignal. Consequently, TDC circuits are quite often built out of the same logic gateswhich are used to synthesize traditional digital logic. This is one of the reasons, whyTDCs have been receiving a lot of research interest in the past years. For example, amodern integrated frequency synthesizer might use an ADPLL, where a TDC is used asa phase detector to directly digitize the phase error of a DCO [11–15]. A TDC couldalso be used for sensing timing skew and calibrating a high-speed time interleaved ADC[16].

Furthermore, the increasing switching speed and the reduced SNR available in scaledCMOS technologies has encouraged designers also to experiment with relocating all ofthe analog signal processing into the amplitude insensitive time domain. A quite radicalapproach is to move the whole ADC quantization process into the time domain. Forexample, in [17], a 5GS/s ADC is realised by using a voltage-to-time converter(VTC) toconvert the analog voltage to a time interval which is then quantized by a high speedTDC. A 14-bit ADC in [18] uses a VTC and a pipelined TDC for quantization. A 10-bitsubranging successive-approximation ADC with a coarse TDC quantizer is proposed in[19]. A noise shaping GRO-TDC is used as a quantizer in [20], and a ∆Σ ADC withtime-mode signal processing is proposed in [21].

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In addition to data conversion circuits, research efforts have also been focusedon developing signal processing circuits that could potentially operate entirely withtime-mode signals, i.e. with signals where the information is stored as a pulse-widthrather than as an amplitude. Conventionally, discrete-time analog signal processing relieson switched-capacitor circuits, but functionally similar signal processing blocks havealso been developed as time-mode circuits, which better suite the capabilities of modernCMOS processes. [22–24] propose several concepts and circuit blocks for summation,integer multiplication, accumulation and other arithmetic operations required for signalprocessing. Using these techniques, [23] demonstrates a time-mode LDPC decoder.[24] proposes a fourth-order delta-sigma TDC using some of the proposed time-modesignal processing circuit blocks.

TDCs can be also used in digital transmission links. [25] proposes a pulse widthmodulated signaling scheme, where the transmitter contains a digital-to-time(DTC)converter for generating pulse width modulated signals. A receiver chip includes aTDC which demodulates the transmitted data. The time domain modulation aims toenhance the spectral efficiency and performance in band-limited channels where ahigh-speed NRZ scheme fails. Furthermore, TDCs could also be potentially used inwireless applications as well. [26] demonstrates an IF polar receiver using a TDC toextract and quantize the baseband phase of the received IF signal.

A lot of research effort has also been focused on developing large arrays of CMOSSPADs (Single-Photon Avalanche Diode). This technology would allow to construct alarge array of ToF receivers on a single chip. Each pixel consisting of a SPAD and acompact TDC would form an independent ToF receiver. These devices could have ahuge range of different kinds of applications. Single chip ToF array solutions have beendemonstrated, for example, in Raman spectroscopy [27], fluorescence-lifetime imagingmicroscopy [28–30], positron emission tomography [30–33] and of course ToF 3D laserscanning [6, 10].

Other applications for TDCs include calibration of timing sensitive devices [34],clock synchronization in large distributed sensor arrays [35], phase noise measurement[36, 37] and interfacing capacitive sensors [38].

The aim of this work was to develop very high precision TDCs with a longmeasurement range. A long range TDC is required, for example, in ToF based distancemeasurement, where a distance of one meter roughly corresponds to a time interval of6,67 nanoseconds. These long range TDCs typically employ the Nutt interpolationmethod, in which two short-range TDCs are used as interpolators and an external

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reference clock is used to provide a stable time base against which the measurement isdone. Although the architecture of a Nutt TDC differs from a typical short-range TDC,the interpolators developed in this work could be also used as independent short-rangeTDCs after some small modifications.

The stability of the time base, i.e. the reference clock, is extremely important. Ingeneral, when short time intervals are measured, phase noise induced measurement erroris usually negligible and is masked by other error sources, such as quantization error.However, when the measurement range needs to cover several microseconds, phasenoise effects cannot be neglected anymore. In addition to the developed TDCs, this workaims to also provide a thorough analysis of oscillator instability induced measurementerrors, which are verified by measurements conducted with one of the designed TDCs.

1.2 Thesis organisation and contribution of this work

This thesis is organised as follows. In chapter 2, the operating principle of a TDCbased on the Nutt interpolation technique is reviewed. This chapter aims to provide anoverview of the basic building blocks required by a long range time-to-digital converter.Some of the most common and recently published short-range TDC architectures, whichare suitable to be used as interpolators, are also presented.

Chapter 2 also aims to clarify the key differences between a conventional dataconverter and a long range Nutt TDC. The error sources affecting the single-shotprecision and accuracy are reviewed.

In chapters 3 and 4, the main contributions of this work are presented. The originalpublications presented in chapter 3 are mostly focused on the noise and jitter analysis ofTDCs based on the Nutt interpolation method. In particular the influence of referenceclock instability is thoroughly analyzed and verified with measurements conducted withone of the TDCs implemented in the course of this work. Furthermore, time-to-voltagebased interpolators are analyzed, with an emphasis on linearity and thermal noiselimitations in CMOS technology.

In chapter 4, the implemented long range TDCs are presented. The first one is anintegrated CMOS TDC with cyclic switched-frequency interpolators implemented in0.35µm technology. The architecture and the operating principle of the cyclic/algorithmicinterpolator utilizing a switched-frequency ring oscillator(SRO) is presented. Also,the developed correlation based digital calibration method is explained and finallymeasurement results are presented. The second long-range TDC uses a discrete

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component Miller-integrator based time-to-voltage converter as an interpolator, whileother key functionality is implemented on an FPGA. A detailed view of the architectureis presented and the performance of the TDC is verified by measurement results.

Discussion is provided in chapter 5, where also the implemented TDC designs arecompared with other recently published TDCs. A summary of the findings and theresults of the thesis are provided in chapter 6.

In summary, the main contributions of this work are

– Phase noise analysis and its effects on the measurement precision of a long range NuttTDC

– Analysis of time-to-voltage converters and their linearity and noise limitations inmodern CMOS technologies

– Design and implementation of a 327µs range, 4.2ps RMS single-shot precisionCMOS TDC with cyclic interpolators using switched-frequency ring oscillators fortime-residue amplification

– Development of a digital radix extraction technique for cyclic interpolators utilisingtime-residue amplification

– Design and implementation of a discrete component TDC with time-to-voltageinterpolators achieving 84ms range and 2ps single-shot precision

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2 Long range time-to-digital converters

In this chapter, the techniques and the most usual circuit blocks utilized by long rangeTDCs are reviewed. The first section covers clock counters, which are used in nearlyall long range TDCs as the coarse time measurement block. The following sectionsintroduce techniques which can be used to improve the clock counter resolution closerto a picosecond level. Furthermore, error sources and synchronization issues are alsodiscussed.

2.1 Counter method

A simple method to digitize a time interval is to use a reference clock counter [39].During a time interval measurement, the full cycles of an oscillator are counted. Theresolution is determined by the oscillator frequency, and the maximum quantizationerror is ±Tre f , i.e. the period of the reference clock. Fig. 1 shows the timing diagram fora TDC based on counting the full cycles during a time interval.

Hereafter, all further equations using a lower case symbol for a time interval, e.g. ∆t,have been normalised by a reference time period, i.e. ∆t = ∆T/Tre f . Using this notation,the input time interval, ∆tin, can be written as Q+F , where Q is the integer part of thetime interval and F is the fractional part of the time interval. The counter output is givenby

N = dQ+F−∆tstarte (1)

ûTin

CLKref

Start

Stop

ûTstart NTref

ûTstop

Fig. 1. Timing diagram illustrating the operating principle of a counter based TDC.

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where 0≤ ∆tstart < 1 accounts for the time difference between the start signal and thefollowing reference clock edge. This error can be deterministic, or totally random if thestart signal is asynchronous with respect to the counter’s reference clock.

Measurement error is given by

ε∆T = N−Q−F = dF−∆tstarte−F

=

{1−F ,0≤ ∆tstart < F

−F ,F ≤ ∆tstart < 1

(2)

If the input is asynchronous(i.e. ∆tstart is uniformly distributed), the counter methodis linear and no static error is formed. The mean value and variance for a static input aregiven by

E[ε∆T ] = F(1−F)+(1−F)(−F) = 0

Var[ε∆T ] = F(1−F)2 +(1−F)(−F)2−E[ε∆T ]2 = F(1−F)

(3)

The counter method provides a wide measurement range only limited by the width ofthe counter. The only limitation of the counter method is the low resolution determinedby the reference clock frequency. However, the Nutt interpolation method [1] can beused to improve the resolution closer to a picosecond level.

2.2 Nutt interpolation method

The Nutt interpolation method is based on measuring the errors formed in the countermethod and then subtracting these errors from the counter result. This method, originallyproposed in [1] and further developed in various sources [40, 41], traditionally usedanalog time-stretchers as interpolators. Nowadays, in general, the term Nutt TDC refersto any TDC using a counter and two short-range TDCs as interpolators for measuringthe errors of the counter.

The short-range TDCs can be based on several different kinds of TDC architectures.In the literature, these short-range TDCs are predominantly used as stand-alone TDCs inapplications requiring only a short measurement range, such as ADPLLs.

The Nutt interpolation method is an extension of the counter method, and as shownin Fig. 1, the time errors measured by the interpolators are ∆tstart and ∆tstop. The inputtime interval can be then written as

∆tin = N +∆tstart −∆tstop (4)

20

If ∆tin is written as Q+F and ∆tstart is considered to be a random variable distributedbetween 0 and 1, the three different time spans shown in Fig. 1 can be written as

0≤ ∆tstart < 1

∆tstop = dF−∆tstarte− (F−∆tstart)

N = Q+ dF−∆tstarte

(5)

It is important to note that since ∆tstart can be considered to be a random variable, aTDC based on the Nutt interpolation method has a few significant differences whencompared to conventional data converters. A Nutt TDC is capable of measuring timeintervals that are asynchronous with respect to the reference clock (i.e. ∆tstart is random),which can be used to scramble the nonlinearity and quantization errors of the short-rangeinterpolators. With asynchronous measurements, the interpolator’s static nonlinearitiesand quantization errors are converted into noise-like dynamic errors, which can befiltered/averaged out.

Moreover, typical short-range TDC architectures employ either delay lines or ringoscillators, where the thermal noise induced jitter tends to build-up towards the endof the delay line. In a Nutt TDC, since ∆tstart and ∆tstop are always between 0 and 1,the maximum time interval which the interpolators need to measure is limited by thereference clock. Therefore the jitter due to thermal noise has only a one clock periodof time to build up. The long range stability and the jitter of a Nutt TDC is mainlydetermined by the stability of the reference clock, for which reason a high quality OCXOor TCXO is usually used when aiming for a range of several hundred microseconds.

Essentially, the Nutt interpolation method combines the high resolution of a short-range TDC with the long range and the stability provided by a clock counter using ahigh quality external oscillator.

2.2.1 Synchronization

The time intervals, ∆tstart and ∆tstop, need to be accurately formed for the interpolators.Usually these time intervals are formed by using a synchronizer that produces logiclevel signals with pulse widths that are proportional to ∆tstart and ∆tstop. Fig. 2 shows apractical synchronization block which produces three signals: ENstart which is high forthe duration of ∆tstart , ENstop which is high for the duration of ∆tstop and ENCT R whichis a synchronous signal that is high during the time that the main counter is enabled.This arrangement requires the input timing signals to be latched before synchronization,

21

DFF1b

D QR

Reset

CLKrefDFF1a

D QR

Reset

CLKref

DFF2b

D QR

Reset

CLKrefDFF2a

D QR

Reset

CLKref

Start

Stop

ENCTR

ENStart

ENStop

CLKref

Start

Stop

DFFs to avoid

metastability

NmainTref

ûTstop

ûTstart

...

Fig. 2. Synchronization logic used to split the input time interval into three pulses.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2400

420

440

460

480

500

520

540

560

580

Pro

pa

ga

tio

n d

ela

y [

ps

]

Time from Data edge to CLK edge [ns]

Fig. 3. DFF propagation delay vs. the time difference of data and clock inputs.

so that the Start/Stop signals stay high for the duration of the whole measurementregardless of the actual pulse widths at the TDC’s input.

In Fig. 2, the rising edge of the pulse, ENstart or ENstop, is determined by theStart/Stop event. The falling edge of the time span is made synchronous to the followingreference clock edge. A practical synchronizer needs to use two DFFs for the fallingedge synchronization instead of one. The reason for this is that the propagation delay ofa DFF increases when its setup time is violated, which can, in an extreme case, lead tometastability when the Start/Stop edge and the reference clock edge coincide [42]. Thisissue is illustrated in Fig. 3, which shows the simulated propagation delay of a DFFavailable in a 0.35µm CMOS process.

22

When the synchronizer uses two DFFs, the propagation delay of the first DFFcan increase by a maximum of one reference clock period without introducing anymeasurement errors. Although the DFF can still enter metastability, the DFF will besteered to either logical state due to noise when given enough time. The additionalDFF also adds an offset of one reference clock period to ∆tstart and ∆tstop. However, theoffset is compensated when the final output is calculated according to (4).

2.3 Short-range TDC as an interpolator

When the Nutt interpolation method is used by combining the counter method withshort-range interpolators that each have B-bits of resolution, the single-shot precision isimproved by a factor of 2B. Fig. 4 shows the single-shot precision of a TDC based onthe Nutt interpolation method with various interpolator resolutions. The use of B-bitinterpolators is equivalent to increasing the reference frequency of a counter methodTDC by a factor of 2B. The peak variance relative to the reference clock period is givenby 1/(4×22B) and the average variance(RMS precision) is 1/(6×22B).

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 10

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

Fractional part F

Sta

nd

ard

de

via

tio

n

Counter method

Interpolator bits: 2

Interpolator bits: 4

Fig. 4. Single-shot precision relative to the reference clock period when using interpolatorswith B-bits of resolution.

23

A real interpolator, however, is not only affected by quantization error, but also bynonlinearity and offset errors. However, one of the major advantages of the Nutt interpo-lation method is, that when measurements can be done asynchronously with respect tothe reference clock, the nonlinearity and quantization error of the interpolator appear asa noiselike dynamic error rather than a static error at the TDCs output. Suppose thatthe interpolator errors are given by εstart(∆tstart) and εstop(∆tstop), which include errorsdue to quantization, nonlinearity and offset. Now, when asynchronous measurementsare considered, ∆tstart is a uniformly distributed random variable. According to (4),the mean error at the TDC’s output is given by integrating the interpolator errors withrespect to ∆tstart from 0 to 1.

µ = E[εstart(∆tstart)]−E[εstop(∆tstop)]

=∫ 1

0εstart(x)dx−

∫ 1

0εstop(dF− xe− (F− x))dx

=∫ 1

0εstart(x)dx−

∫ F

0εstop(1− (F− x))dx−

∫ 1

Fεstop(0− (F− x))dx

=∫ 1

0εstart(x)dx−

∫ 1

1−Fεstop

(x′)dx′−

∫ 1−F

0εstop

(x′)dx′

=∫ 1

0εstart(x)dx−

∫ 1

0εstop

(x′)dx′ = µstart −µstop

(6)

The above result is independent of the input time interval Q+F , therefore only an offseterror is possible. However, a real TDC might still be nonlinear due to crosstalk issues.Crosstalk is usually most pronounced when measuring really short time intervals when∆tstart and ∆tstop are very close to each other and both interpolators are active at thesame time.

However, the dynamic error, i.e. the single-shot precision or the variance of theTDC’s output, is affected by the nonlinearities. The variance of the TDC’s output isgiven by

σ2ssp(F) =Var[εstart(∆tstart)− εstop(dF−∆tstarte− (F−∆tstart))]

=∫ 1

0ε

2start(x)dx−µ

2start

+∫ 1

0ε

2stop(dF− xe− (F− x))dx−µ

2stop

−2∫ 1

0εstart(x)εstop(dF− xe− (F− x))dx−µstart µstop

= σ2start +σ

2stop−2σstart,stop(F)

(7)

24

where σ2start and σ2

stop are the interpolator error variances for a uniform ∆tstart , andσstart,stop(F) is the covariance of interpolator errors, which is a function of the fractionalpart F . Therefore, the single-shot precision of a Nutt TDC is a periodic function of theinput time interval, ∆tin, which repeats itself with a period equal to the reference period.

Furthermore, the variance of the interpolator error can be split into quantizationerror and nonlinearity error. The covariance is usually dominated by the nonlinearityerror, which gives the following expression for the single-shot precision

σssp(F) =√

σ2start +σ2

stop−2σstart,stop(F)

≈√

σ2Qst +σ2

Qsp +σ2INLst +σ2

INLsp−2σINLst,INLsp(F)(8)

where σ2Qst and σ2

Qsp are the variances due to quantization error, σ2INLst and σ2

INLsp are thevariances due to nonlinearity error and σINLst,INLsp(F) is the covariance of nonlinearityerrors.

The RMS single-shot precision is given by integrating the total variance with respectto F from 0 to 1. For the covariance part, the integration gives∫ 1

0σstart,stop(F)dF =

∫ 1

0εstart(x)

(∫ 1

0εstop(dF− xe− (F− x))dF

)dx−µstart µstop

=∫ 1

0εstart(x)µstopdx−µstart µstop

= µstart µstop−µstart µstop = 0

(9)

Therefore, the RMS single-shot precision due to the interpolators’ quantization errorand nonlinearity error is given by

σrms =

√∫ 1

0σ2

ssp(F)dF

=√

σ2start +σ2

stop

=√

σ2Qst +σ2

Qsp +σ2INLst +σ2

INLsp

(10)

Fig. 5 shows an example of a Matlab simulated INL/DNL when the DNL is normallydistributed with a standard devation of 0.1LSB. Then using equations (8) and (10), thesingle-shot precision and the RMS precision is solved, which is shown in Fig. 6. A morecomplete view of the total error is shown in Fig. 7, which depicts the TDC’s error due toquantization error and INL for every possible combination of ∆tstart and F . This was

25

100 200 300 400 500 600 700 800 900 1000-1

-0.5

0

0.5

1

BIN #

DN

L [

LS

B]

Start channel

Stop channel

100 200 300 400 500 600 700 800 900 1000

-2

0

2

BIN #

INL

[L

SB

]

Fig. 5. An example of DNL/INL when DNL is gaussian with σDNL = 0.1σDNL = 0.1σDNL = 0.1LSB.

done in Matlab by modeling the full TDC with the given DNL/INL and by sweeping∆tstart and F with a step much smaller than the interpolators’ quantization step.

When asynchronous measurements are considered, the shape of the single-shotprecision curve is determined by the covariance of the interpolator errors. If bothinterpolators are affected by some deterministic error source arising from, for example,poor layout or clock feedthrough, the INL of the interpolators can be close to identical.When the INLs are identical, the covariance will be maximised when the time interval isan integer multiple of the reference clock period. This results from ∆tstop being equal to∆tstart , when F = 0 as seen from Eqn. (5). Therefore, the minimum single-shot precisionis usually achieved when measuring time intervals that are an integer multiple of thereference clock period.

When calculating the TDC output according to (4), one potential issue is that theinterpolator outputs need to be adjusted for correct gain. When the output of the fullTDC is considered, an interpolator gain error results in an offset error and also has asignificant impact on the single-shot precision as discussed in Paper I.

26

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.90.8

0.9

1

1.1

1.2

1.3

1.4

1.5

1.6

1.7

1.8

Fractional part(F) of the time interval

Sin

gle

-sh

ot

pre

cis

ion

[L

SB

]

σ(F)

σRMS

Fig. 6. An example of the resulting single-shot precision due to interpolator INL and quanti-zation error.

Fractional part(F) of the time interval

∆t s

tart

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.90

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

Err

or

[LS

B]

-3

-2

-1

0

1

2

3

4

Fig. 7. A complete view of the simulated TDC’s error due to quantization and interpolatornonlinearity.

27

The TDCs output needs to be calculated as

∆̂t in = Nre f +∆Qstart

∆Qre fNstart −

∆Qstop

∆Qre fNstop

= Nre f +αstartNstart −αstopNstop

(11)

where ∆Qre f is the quantization step for the main counter, ∆Qstart , ∆Qstop are thequantization steps for the interpolators and αstart ,αstop are the gain coefficients. Thequantization step for the main counter is Tre f , but for the start interpolator, for example,the quantization step, ∆Qstart , might not be well defined due to PVT variations. Therefore,the gain coefficients, αstart and αstop, must be resolved through calibration. Calibrationtechniques can be, in general, split into background and foreground algorithms, wherethe latter requires the measurement to be interrupted for the duration of calibration.

One other popular option is to adjust the interpolator gain through biasing so that thegain coefficient is guaranteed to be a binary value 2−B. In this case, the interpolatoroutputs can be simply shifted right by B bits and summed with the main counter output.For example, delay line based TDCs in [9, 43], use a delay locked loop and a replicadelay line to adjust the quantization step, ∆Qstart . The matching of the replica delay line,however, might not be perfect which can lead to a small gain error. The replica biasingtechnique has the benefit that the measurement process does not have to be interruptedand that the gain multiplication in the digital domain can be entirely avoided.

On the other hand, calibration techniques have the advantage that the actualinterpolator results are used for finding the gain coefficients, thus there are no replicabiasing related mismatch errors. However, calibration algorithms usually require digitalmultiplication, which is an expensive operation that can take a lot of area and powerwhen implemented on-chip.

In general, when gain error is present, the single-shot precision and RMS precisionare given by

σssp(F) =

√1

12

(αεstart

αstart−

αεstop

αstop

)2

+αεstart

αstart

αεstop

αstopF(1−F)

σrms =

√1

12

(αεstart

αstart

)2

+1

12

(αεstop

αstop

)2(12)

where αεstart and αεstop are the gain errors of the start and stop channels, respectively.

28

2.4 Short-range TDC architectures

In this section, some of the most common and recently published short-range TDCarchitectures are reviewed. These circuit architectures are quite often used as stand-aloneTDCs in applications where the required measurement range might only cover a fewhundred picoseconds. However, in a long range TDC based on the Nutt interpola-tion method, these circuit architectures are used to build the start and stop channelinterpolators that determine the resolution and the precision of the full TDC.

2.4.1 Flash TDC

Fig. 8 shows a simple Flash TDC based on a delay line using DFFs as arbiters. TheStart signal propagates through a tapped delay line, whose state is sampled by the Stopsignal. The resolution of a delay line TDC is given by the propagation delay of a singledelay cell, τ . The range is thus Nτ , where N is the number of delay cells and arbiters.The delay cells are usually inverters and therefore the resolution is typically limited tofew tens of picoseconds.

The benefits of a delay line TDC is its simple structure and low latency as the outputis immediately available after the arrival of Stop signal. Delay line TDCs can be alsoeasily realized on FPGAs [44–47]. However, when a long range needs to be covered thedelay line quickly becomes large. Furthermore, random mismatch between the delaycells and between the arbiter threshold voltages directly affect the DNL and INL of theconverter. The random variation in propagation delay accumulates through the delayline, and the worst case deviation from nominal delay is expected to be at the end of thedelay line. Furthermore, the jitter of the propagating signal will increase towards the endof the delay line, as each of the delay cells adds jitter due to thermal noise.

The range of a delay line TDC can be extended by arranging the delay line as aring oscillator as shown in Fig. 9. The ring oscillator is started from a Start signal and

2

Stop

Start2

Q0

DFF

D QQ1

DFF

D QQ2

DFF

D QQ3

DFF

D Q

2 2

Fig. 8. Simple delay line based Flash TDC with DFF arbiters.

29

2 2 2

State Registers

CounterStart

Stop

EN

Fig. 9. Conceptual diagram of a Flash TDC arranged as a ring oscillator.

a counter is used to observe the "overflow" from the delay line. A Stop signal thensamples the state of the ring oscillator and disables the counter. Although the areaof the converter can be greatly reduced using a ring oscillator, the resolution is stillgiven by the gate delay. A multipath ring oscillator [48, 49] can be used to lower theeffective propagation delay, however with the expense of increased power consumption.In a multipath ring oscillator, the inputs of a single delay cell are connected to twoor more preceding delay cell outputs, effectively forming several feedback loops inthe ring oscillator. This technique can be used to greatly improve the resolution. Forexample, [50] reports a multipath ring oscillator with a nominal gate delay of 6ps in0.13µm CMOS technology.

2.4.2 Vernier TDC

A Vernier TDC aims to improve the resolution beyond the gate delay limit. Compared tothe Flash TDC, here the Stop signal also propagates through a delay line as shown in Fig.10. The propagation delays for the Stop signal are made smaller than the propagationdelays for the Start signal, and thus the Stop signal slowly catches the Start signal as itpropagates through the delay line. The resolution of a TDC based on the Vernier delayline is given by ∆ = τ1−τ2. Therefore a high resolution can be achieved even with quiteold technology. For example in [51], a 7-bit Vernier TDC in 0.7µm CMOS technologyachieves a resolution of 30ps.

Compared to the Flash TDC, the Vernier TDC has a latency which is equal to thetime that it takes for the Stop signal to catch the Start signal. Furthermore, for a givenfull scale range, the jitter due to thermal noise will be larger than in the case of FlashTDC since the timing signals need to propagate longer in the delay lines.

Just like the Flash TDC, the Vernier TDC can be also arranged as a ring oscillator,in which case the range of the converter is only limited by the size of the full cycle

30

Stop

Start21

Q0

DFF

D QQ1

DFF

D QQ2

DFF

D QQ3

DFF

D Q

21 21 21

22 22 22 22

Fig. 10. A Vernier delay line TDC with DFF arbiters.

22

Arbiter

-4û�

Arbiter

-û�

Arbiter

2û�

Arbiter

-2û�

Arbiter

û�

Arbiter

4û�

Arbiter

0

Arbiter

3û�

Arbiter

6û�

22

21 21

Arbiter matrix

(22= 2û, 21= 3û)

Start

Stop

Fig. 11. A conceptual diagram of a 2D-Vernier TDC.

counter. In [52] a ring oscillator Vernier TDC achieves a resolution of 8ps in 0.13µmtechnology. [43] reports a TDC based on the Nutt interpolation method using Vernierring oscillators as interpolators while achieving 17ps single-shot precision with a rangeof 164ns. [53] uses gating to achieve noise shaping with a Vernier ring oscillator andachieves an equivalent resolution of 3.2ps.

The latency and range of a Vernier TDC can be further improved by using a 2-dimensional Vernier topology [54]. Fig. 11 shows an example of a 2D Vernier TDCwith only two delay cells used in each signal path while still providing a linear rangefrom −2∆ to 4∆. The reduced number of delay cells improves jitter and nonlinearitydue to delay mismatches. However, the number of arbiters is still equal to the number ofbins and therefore the area of the circuit is not reduced as much. This architecture canbe also extended by replacing the delay lines with ring oscillators and adding counters tocount the full cycles [55, 56].

31

2.4.3 TDCs based on time-to-voltage converter and an ADC

A time-to-voltage(TVC)/time-to-amplitude converter(TAC) converts a time interval intoa voltage. Traditionally, this functionality is realized as a constant current integrator inwhich a capacitor is charged with a constant current for the duration of the time interval.The voltage over the capacitor is then quantized by an ADC. A conceptual view of aTVC/TAC followed by an ADC is shown in Fig. 12. The output voltage of a TVC isgiven by

∆Vout =∫

∆Tin

0

IC

dt =IC

∆Tin (13)

The somewhat simple structure, however, suffers from a few practical issues,especially when modern CMOS processes are considered. A practical current source hasnonlinear output characteristics and finite output resistance, which limits the linearityof the whole TDC. However, when the range of the TVC/TAC can be kept short, thelinearity requirements can be significantly relaxed.

For example, [57] utilises a Gm-C integrator and a SAR-ADC to build a 9-bit TDCwith ±256ps range and 11.7ps single-shot precision in a 90nm CMOS technology.[58] reports a TAC in 0.35µm BiCMOS technology with a longer range of 45ns, butachieves only a precision of 40ps(FWHM). [59] uses a TAC and an ADC in 1.2µmCMOS technology to achieve a range of 16ns with a resolution of 107ps.

A TVC/TAC is also simple enough to realise with discrete components. [8] usesthe Nutt interpolation method with TVC based interpolators. The full TDC achieves arange of 2.55µs with a single-shot precision of 14ps. A discrete TDC with TVC basedinterpolators is also realised in this work(Paper I). The developed TDC has a nominalrange of 84ms and a better than 2ps single-shot precision.

I

C

ΔTin

ADCRST

Fig. 12. Time-to-voltage/time-to-amplitude converter followed by an ADC.

32

2.4.4 TDCs based on analog time amplifiers/stretchers

An analog time-stretcher aims to improve the resolution by amplifying the input timeinterval and then using a low resolution TDC(e.g. a clock counter) to quantize theamplified input. An analog time-interval amplifier is usually based on a constant currentintegrator similar to the ones used in time-to-voltage converters, however no ADC isrequired. Fig. 13 shows conceptual schematics for two possible analog time-stretchingtechniques.

The first one is based on charging a capacitor with a constant current for the durationof the time interval. Then, the capacitor is discharged with a lower current. The time ittakes to discharge the capacitor is equal to the input time interval multiplied by thecharging/discharging current ratio, K. Usually a synchronous clock counter is used as aTDC to quantize the discharging period. The output of an analog time stretcher can bewritten as

∆Tout = ∆TinI1

I2= ∆TinK (14)

where I1 is the charging current and I2 is the the discharging current.Many of the first TDCs were based on this analog time stretching technique. In [60],

a discrete TDC based on the Nutt interpolation method uses an analog time stretcher tobuild a cyclic interpolator with a resolution of 97.6ps. [40] reports a TDC with a rangeof 33ms and with a resolution of 125ps. [18] demonstrates that this technique can be

I C

TDC

K*I

ûTin

-TDC

Time amplifier/stretcher

-TDC

I

K2*C

K1*I

C

TDC

ûTin

Time amplifier/stretcher

Fig. 13. Analog time-stretchers(time amplifiers): (a) Single integrator time-stretcher, (b) Dualintegrator time-stretcher.

33

used in modern CMOS technologies as well by utilising analog time amplifiers to builda 11b pipeline ADC with time domain quantization.

Instead of discharging the capacitor, a functionally equivalent time stretcher mighthave another capacitor which is charged to the same voltage as the main capacitor. Thetime it takes to charge the secondary capacitor to the same voltage, is given by

∆Tout = ∆TinC2I1

C1I2= ∆TinK1K2 (15)

A time stretcher with two capacitors has the extra freedom of adjusting the gain not onlyby currents, but by capacitor ratios as well. A BiCMOS TDC utilising this techniqueand the Nutt interpolation method achieves a 2.5µs range and 30ps single-shot precisionin [61]. [62] reports a time-stretcher based Nutt TDC in 0.35µm CMOS technologywith a range of 250ns and a resolution of 50ps.

2.4.5 Advanced CMOS time amplifier topologies

Time amplifiers can be also designed by utilising SR-latches [63], custom time amplifiercells [64] or by using pulse-train time amplifiers [65]. These time amplifier topologieshave been used in several designs to construct, for example, two-step TDCs [63, 66],pipeline TDCs [65, 67, 68] or cyclic/algorithmic TDCs [69, 70].

An SR-latch based time amplifier is illustrated in Fig. 14. It relies on the metastabilityregion available in latches. Time amplification is achieved because the propagation delayof the SR-latch increases when the inputs are close to each other. The peaks shown inFig. 14 are the metastability points, which are shifted away from zero by the delay cellsat the input. The time difference between the peaks is given by the delay difference ofthe delay cells 2(τ1− τ2). However, the useful linear range of the amplifier is muchsmaller than this. For a small time difference, the time interval gain is given by [63]

GSR =2C

gm(τ1− τ2)(16)

where C is the effective load capacitance of the SR-latch, and gm is the transconductanceof the SR-latch at metastability. The offset delays, τ1 and τ2, can be adjusted for highlinearity, but with the expense of low gain.

Fig. 15 illustrates a two-step TDC topology which uses time amplifiers for residuegeneration. In [63], this two-step topology is implemented in 90nm CMOS technologyand utilises the SR-latch based time amplifiers. In this particular design, the time

34

22

21

21

22

Startin

Stopin

Stopout

Startout

0

0

∆Tout

∆Tin

Fig. 14. (a): Time amplifier based on SR latches. (b): Characteristics of the time amplifier.

Fine TDC

Coarse TDC

MUX

2

Arbiter

TA

D0

2

Arbiter

TA

D1Arbiter

TA

D2

2

Arbiter D0'

2

Arbiter D1'

Arbiter D2'

Residue

Selection

Logic

D0 D1 D2

Start

Stop

Fig. 15. A conceptual diagram of a two-step TDC utilising time amplifiers [63].

amplifiers’ gain is about 20, while the useful input range covers only 40ps. The totalrange of the TDC is 640ps with a resolution of 1.25ps.

Another commonly used short range time amplifier topology is shown in Fig. 16.Originally proposed in [64], the circuit achieves time amplification by a cross-couplingarrangement, which reduces the drive-strength for the signal arriving later to the amplifier.However, the linear range for this type of amplifier is also quite limited.

As an example, Fig. 17 shows a 1.5-bit quantization and amplification stage, wherethis amplifier topology is employed in [67, 69]. [67] uses this amplifier topology toconstruct a 1.8ns range, 10-bit pipeline TDC in 0.13µm CMOS technology. The time

35

Startin Stopin

StopoutStartout

0

0

∆Tout

∆Tin

Fig. 16. (a): Circuit diagram of a time amplifier proposed in [64]. (b): Characteristics of thetime amplifier.

2 2

Arbiter

1

0

1

02 2

TA

Startin

Stopin

Startout

Stopout

Arbiter

D1¶

D0¶

D1¶

D0¶

D1

D0

2d

2d

2d

2d

Fig. 17. 1.5-bit quantization and error amplification stage used in [67, 69].

amplifier is only used in the last 6 stages of the pipeline, where the input range of theamplifier covers about ±28ps. [69] also uses the same amplifier topology in a cyclicTDC architecture. The 8-bit converter has a range of ±160ps while the amplifier coversan input range of ±80ps.

Fig. 18 shows a conceptual diagram of a pulse-train time amplifier proposed in [66].Compared to the previous amplifier topologies, the pulse-train amplifier has much widerlinear range. First, the time interval is converted to a logic level pulse having a widthproportional to the time interval. The pulse is then replicated and delayed by a delay line.The original pulse and the delayed pulse is then combined in an OR gate to produce apulse train. The two combined pulses can be then used to control a gated delay line,allowing a signal to propagate for a total length of 2∆Tin. The output is read out simplyby sampling the delay line after the pulse-train. No gain calibration is required as the

36

2d

Q0

DFF

D QQ1

DFF

D QQ2

DFF

D QQ3

DFF

D Q

2 2 2

¶1'

2

Sample

Startin

Stopin

Pulse-train amplifier & gated delay line

Fig. 18. A conceptual diagram of a pulse-train time amplifier used with a gated delay line.

gain of the pulse-train amplifier is simply the number of combined input pulses. A65nm CMOS 7-bit two-step TDC utilizing the pulse-train amplifier in [66] has a rangeof 480ps and a resolution of 3.75ps. However the number of effective linear bits is only5.28. In [65], a 9-bit(7.57-bit linear) pipeline TDC in 65nm CMOS technology alsoutilizes the pulse-train amplifier, and achieves a range of 570ps with a resolution of1.12ps.

2.4.6 Binary search/SAR TDC

A binary search TDC, or a successive-approximation TDC, uses a binary searchalgorithm to resolve a time interval. Fig. 19 shows a conceptual diagram of a 4-bitbinary search TDC topology proposed in [23]. Each stage of the TDC incorporates anarbiter and a digital-to-time converter (DTC). In each stage, the arbiter resolves whichsignal, Start or Stop, leads the other. The leading signal is then delayed by the DTCbefore the Start and Stop signals enter the following stage. The DTC delays are binaryscaled, and the number of stages is equal to the number of bits. Compared to a FlashTDC, the number of arbiters is significantly reduced.

In [71] a long range TDC, in 0.35µm CMOS technology, utilizes successive-approximation TDCs as interpolators. The binary search algorithm is realised in aclosed-loop manner, where only a single programmable DTC and a phase detectorare used to cyclically resolve the time interval. The TDC has a range of 327µs with asingle-shot precision of 11ps(rms). [72] uses the same SAR-TDC technique to build a

37

Start

Arbiter D0

Arbiter

1

0

42 1

02d

D3

42 2d

Arbiter

1

0

22 1

02d

D2

22 2d

Arbiter

1

0

2 1

02d

D1

2 2d

Stop

Arbiter + DTC

Fig. 19. A conceptual diagram of a 4-bit binary search TDC [23].

10-bit, 10ns range TDC in 65nm CMOS technology. The TDC achives a resolution of9.77ps with a peak INL of 17ps. Open-loop binary search TDCs are also used in [23],where the TDCs are used as a building block for an LPDC decoder.

2.4.7 Interpolator structures implemented in this work

Two interpolator topologies have been designed and implemented in the course ofthis work. The main object was to improve the linearity and jitter characteristics ofinterpolators in order to achieve an effective linear range of 10 bits or more when theinterpolators use a reference clock period of 5ns.

The first interpolator structure is based on a TVC and is implemented with discretecomponents(Paper I). The aim was to improve the single-shot precision and the linearityof the TVC by using a Miller-integrator based TVC instead of a simple capacitordischarging circuit. With the Miller-integrator the TVC achieves a peak INL of ±2pswhich roughly corresponds to 11 linear bits.

The second interpolator topology is implemented as an integrated CMOS circuit in0.35µm technology(Papers IV & V). This interpolator uses a time-interval amplificationconcept to build a cyclic/algorithmic TDC. The time-residue amplification is realizedwith a ring oscillator, whose frequency can be switched between two values, a highfrequency and a low frequency, whose ratio gives the time-residue gain. This interpolatorachieves a peak INL of ±4.5ps, which corresponds to about 10 linear bits.

Both of these interpolator topologies are presented in more detail in chapter 4, wherethe interpolators are used to implement long range TDCs based on the Nutt interpolationmethod.

38

3 Outline of original publications and maincontributions

This work consists of five publications, of which two are more focused on the theoreticalanalysis of noise related measurement uncertainty in TDC’s using the Nutt interpolationmethod. The three other publications, on the other hand, are focused on the actual TDCsimplemented over the course of this work. Two different Nutt TDCs have been designedand tested, each one of them using different techniques for realizing a high resolutioninterpolator.

In this chapter, the publications providing contributions to the theoretical noiseanalysis of the Nutt interpolation method are presented.

Paper II provides a thorough analysis of phase noise induced measurement uncer-tainty. This analysis aims to provide mathematical tools and practical measurementtechniques to translate various power-law phase noise processes into time domain jitter.The results are verified with measurements conducted with one of the TDC’s developedin the course of this work.

Paper III focuses on the analysis of thermal noise and linearity of time-to-voltageconverters implemented in CMOS technology. The publication aims to sort out thecapacitor and current source related design constraints that limit the maximum achievableprecision.

In Chapter 4, the actual designed and implemented TDCs are presented along withmeasurement results.

Paper I presents a TDC implementation based on interpolators using a time-to-voltage converter. The TVCs are implemented with discrete components and use aMiller integrator to improve the linearity of the interpolator. This TDC has a nominalmeasurement range of 84ms and a measurement precision of 2ps up to time intervals offew milliseconds.

Papers IV and V present an integrated CMOS TDC in 0.35um technology, whichuses cyclic/algorithmic interpolators based on switched-frequency ring oscillators.Whereas an analog time stretcher uses two different charging/discharging currents toamplify a time interval, a switched-frequency oscillator uses two different frequencies toprovide time amplification. This technique was used to replace the traditional TVC witha more robust ring oscillator based design to build a cyclic/algorithmic interpolator. The

39

TDC has a measurement range of 327us and achieves an RMS single-shot precision of4.2ps without any INL compensation. A digital calibration routine is also implemented,which ensures that the precision and accuracy of the converter vary by only a couple ofpicoseconds in a temperature range of -30C to 70C.

3.1 Paper II, Oscillator instability effects in long range TDCs

When short time intervals are measured with a TDC, the measurement precision istypically dominated by quantization noise and other noise sources which can be, ingeneral, modeled as gaussian noise sources with white spectral density. However, whenlong time intervals are measured the time base provided by the reference oscillator mayhave a significant impact on the measurement precision and accuracy.

The accuracy can be deterioted by a deterministic shift in the oscillator’s frequency,for example, due to temperature. Manufacturers typically specify frequency stability inunits of ppm in a certain temperature range. Now, a TDC using a reference oscillatormeasures time intervals by quantizing the phase of the reference oscillator at the timeinstants when the Start and Stop signals arrive. If the reference frequency is shifted by∆ f , the measured time interval is given by

∆̂T =fre f +∆ f

fre f∆T

= ∆T +∆ ffre f

∆T(17)

For example, a 100ppm frequency shift would result in a 10ps error if the measured timeinterval is 100ns. A TDC with a range in the order of microseconds, requires a referenceoscillator with very good frequency stability, i.e. an OCXO or a TCXO.

3.1.1 Phase noise as a power-law PSD and sources for different noiseprocesses

Random frequency instabilities are usually quantified in terms of phase noise, whichcan have a significant impact on the measurement precision of a TDC. Phase noise isusually measured in the frequency domain as a PSD and is expressed in units of dBc/Hz.The phase noise of a free running oscillator can be, in general, represented as a PSDconsisting of power-law noise processes whose spectral densities are proportional to1/ f β (β = 0,1,2,3, ..) [73].

40

The phase noise PSD of a free running oscillator typically consists of white phasenoise(β = 0), flicker phase noise(β = 1), white frequency noise(β = 2) and flickerfrequency noise(β = 3). Typically, the 1/ f 2 and 1/ f 3 slopes seen in a phase noise PSDarise from the intrinsic white noise and flicker noise sources of the oscillator, where theyare up-converted to 1/ f 2 and 1/ f 3 phase noise [74]. On the other hand, the white phasenoise floor and the flicker phase noise are created by clock buffers [75] and other noisesources that are not part of the oscillator’s intrinsic feedback loop. These phase noiseprocesses are illustrated in Fig. 20 and Table 1. In the following discussion, all the PSDsare treated as two-sided spectral densities if not stated otherwise.

∆f [Hz]

Sφ [

dB

c/H

z]

f-3

f-2

f-1

f0

Fig. 20. Phase noise processes in a free running oscillator.

Table 1. Power-law noise processes observed in a phase noise PSD of a free running oscil-lator.

β Sφ ( f ) Noise type

0 h0/ f 0 White phase noise

1 h1/ f 1 Flicker phase noise

2 h2/ f 2 White frequency noise/Random walk phase noise

3 h3/ f 3 Flicker frequency noise

41

3.1.2 Phase noise to jitter conversion

A major problem related to analyzing the higher order noise processes is that in the timedomain the noise processes are not statistically stationary. For example, the variance of a1/ f 2 noise process(random walk) grows linearly with respect to time. Because of this, anumber of stability metrics have been proposed to quantify the time domain instabilitiesin oscillators. These metrics include, for example, Allan variance [76], cycle-jitter andcycle-to-cycle jitter. All these metrics rely on making the time domain noise samplesstatistically stationary by differencing the sampled noise data. For example, cycle-jitteris proportional to the variance of the first difference of the phase noise. By differencingthe noise data once, the time series becomes stationary for all power-law noise processeshaving a β ≤ 2. Allan variance and cycle-to-cycle jitter metrics use the second differenceof the time domain noise data and therefore establish a convergent metric for β ≤ 4.

However, when time intervals are measured, we are looking at the difference betweenthe instantaneous phase at the end of the time interval and the phase at the start of thetime interval. Therefore, the time interval measurement is affected by the first differenceof the phase noise and the variance estimates are only convergent for β ≤ 2. This wouldindicate that 1/ f 3 noise will result in infinite jitter. In order to estimate the contributionof 1/ f 3 phase noise to time interval measurement, we also have to take into account thefact, that in the real world the noise process is only observed for a finite period of time.

Now, consider a TDC based on the Nutt interpolation method. The start signal arrivesat a time instant tstart and the stop signal at a time instant tstop. The main referenceclock counter starts from the following clock edge after the start signal, i.e. when thephase is equal to dφ(tstart)/(2π)e2π . The normalised time intervals measured by theinterpolators and the main clock counter can be written as follows

Nmain =

⌈φ(tstop)

2π

⌉−⌈

φ(tstart)

2π

⌉∆tstart =

⌈φ(tstart)

2π

⌉− φ(tstart)

2π

∆tstop =

⌈φ(tstop)

2π

⌉−

φ(tstop)

2π

(18)

42

The normalized time interval measured by the TDC is then given by

∆t = Nmain +∆tstart −∆tstop

=φ(tstop)

2π− φ(tstart)

2π

(19)

The above equation shows, that a Nutt TDC does not actually measure a time interval,but the phase difference of the reference clock at time instants defined by the Start andStop event, for which reason the stability of the reference clock is of great importance.The time interval can be expressed in seconds by simply dividing the result with thereference clock frequency, i.e. ∆T = ∆t/ fre f . The time interval variance due to thephase noise is given by

σ2∆T =Var

[φ(tstop)−φ(tstart)

2π fre f

]

=E[(φε(tstop)−φε(tstart))

2]

(2π fre f )2

= 2Rφ (0)−Rφ (∆T )

(2π fre f )2

(20)

Where φε is the phase error of the reference oscillator and Rφ (∆T ) denotes the autocor-relation of the phase noise with a lag of ∆T .

Autocorrelation is related to PSD through the Wiener-Khinchin theorem

R(τ) =∞∫−∞

S( f )e j2π f τ d f (21)

Substituting this into (20) we get

σ2∆T = 2

Rφ (0)−Rφ (∆T )

(2π fre f )2

=2

(2π fre f )2

∞∫−∞

Sφ ( f )(1− e j2π f ∆T )d f

=8

(2π fre f )2

∞∫0

Sφ ( f )sin2(π f ∆T )d f

(22)

Evaluating (22) with the power-law PSD values from Table 1 yields the results shown inTable 2. The integral does not converge for 1/ f 3 noise and results in infinite variance.

43

Table 2. Time interval jitter resulting from different power-law phase noise processes.

β Sφ ( f ) Time interval variance σ2∆T [s

2]

0 h0/ f 0 h0 fNBW(π fre f

)2

1 h1/ f 1 h1(π fre f

)2 (ln(2π fNBW ∆T )+ γ)

2 h2/ f 2 h2

f 2re f

∆T

3 h3/ f 3 ∞

fNBW is the noise bandwidth and γ is the Euler-Mascheroni constant(≈ 0.57721).

This would implicate that the oscillator’s frequency is unbounded due to the intrinsicflicker noise sources.

However, when real measurements are done, the measurement variance is observedonly for a finite period of time. Furthermore, the variance is measured by first removinga constant bias, i.e. the average of the observed time intervals, from each measurement.After that, the mean power for the resulting deviations can be calculated. Now, considerthat M consecutive time interval measurements are done with zero dead time in between.In terms of phase error, this M-sample variance can be written as

σ2M =

1M−1

M

∑i=1

(∆φε(i)2π fre f

− 1M

M

∑j=1

∆φε( j)2π fre f

)2

=1

M−1

M

∑i=1

(∆φε(i)2π fre f

)2

−

(1M

M

∑i=1

∆φε(i)2π fre f

)2

=1

M−1

(M

∑i=1

(∆φε(i)2π fre f

)2

− 1M

(φε(t +M∆T )−φε(t)

2π fre f

)2)

(23)

Where ∆φε(i) = φε(t + i∆T )−φε(t− (i−1)∆T ), i.e. the ith time interval measurementerror due to phase noise. The removal of the average time interval corresponds toanother difference operation, thus the M-sample variance is actually convergent for

44

1/ f 3 noise as well. Taking the expected value of (23) results in

E[σ2M] =

1M−1

(M

∑i=1

E[∆φ 2ε (i)](

2π fre f)2 −

1M

E[(φε(t +M∆T )−φε(t))2](

2π fre f)2

)

=1

M−1

(M

∑i=1

2Rφ (0)−Rφ (∆T )(

2π fre f)2 − 2

MRφ (0)−Rφ (M∆T )(

2π fre f)2

)

=1

M−1

(2M

Rφ (0)−Rφ (∆T )(2π fre f

)2 − 2M

Rφ (0)−Rφ (M∆T )(2π fre f

)2

)

=8(

2π fre f)2

MM−1

∞∫0

Sφ ( f )sin2(π f ∆T )d f −∞∫

0

Sφ ( f )sin2(π f M∆T )

M2 d f

=

8(2π fre f

)2M

M−1

∞∫0

Sφ ( f )sin2(π f ∆T )(

1− sin2(π f M∆T )M2sin2(π f ∆T )

)d f

(24)

Now, evaluating (24) with the power-law PSD values from Table 1 gives the resultsshown in Table 3. The M-sample jitter also depends on the number of measurements M,which can be also written in terms of observation time Tobs, i.e. M = Tobs/∆T . WhenTobs is taken to infinity, the results in Table 3 become equal to the previous estimatesshown in Table 2. However, the M-sample variance represents the true measured timeinterval deviation more accurately since it takes into account the finite observation time.

Table 3. M-sample time interval jitter resulting from different power-law phase noise pro-cesses.

β Sφ ( f ) M-sample time interval variance σ2∆T [s

2]

0 h0/ f 0 h0 fNBW(π fre f

)2M+1

M

1 h1/ f 1 h1(π fre f

)2M+1

M(ln(2π fNBW ∆T )+ γ− ln(M)

M2−1)

2 h2/ f 2 h2

f 2re f

∆T

3 h3/ f 3 2h3

f 2re f

ln(M)MM−1

∆T 2

fNBW is the noise bandwidth and γ is the Euler-Mascheroni constant(≈ 0.57721).

45

Hard limiting a clock signal

Converting a measured phase noise PSD to time domain jitter can be also complicatedby the fact that, typically, phase noise analyzers do not actually measure phase, butrather observe the voltage domain sideband power around the carrier. Furthermore, thenoise bandwidth, required by the jitter conversion of white/flicker noise, is typicallyunknown.

Moreover, a TDC only observes the zero crossings of the clock signal, whichcorresponds to sampling the phase(time) error at clock edges. However, the phasenoise PSD, Sφ ( f ), represents the PSD of a continuous process rather than a sampledprocess. In order to measure the sampled phase noise PSD, the sampling process canbe reproduced by hard limiting the clock signal before the phase noise measurement.The sampling process affects the noise floor due to aliasing and it also rejects anycyclostationary noise processes which have most of their noise power concentratedoutside clock transitions, e.g. amplitude modulating noise processes.

Typically, the phase noise PSD is approximated by measuring the single sidebandnoise spectral density around the carrier. The PSD is given in the units of decibels belowcarrier(dBc/Hz) and is defined as

L ( f ) =Sv1s( fc + f )

Pc≈ Sφ ( f ) (25)

where Sv1s( fc + f ) is is the one-sided PSD of the oscillator’s output and Pc is the carrierpower.

Now, it is assumed that a buffer acting as a hard limiter can be mathematicallydescribed by an odd function g(x), i.e. −g(x) = g(−x). The buffer is fed with a noisysine wave Asin(wct +φ(t)), and the output is given by g(Asin(wct +φ(t))). Assumingthat φ(t) is small, a first order Taylor series expansion yields

g(Asin(wct +φ(t)))≈ g(Asin(wct))+φ(t)Acos(wct)g′(Asin(wct)) (26)

As can be seen, at the buffer’s output, the noise voltage due to phase noise is furthermodulated by the term g′(Asin(wct)). Because of this, the phase noise will wrap aroundthe harmonics generated by the nonlinear g′(x), and therefore the phase noise at highoffset frequencies might fold back into the vicinity of the fundamental carrier frequency.This folded high frequency phase noise is generally white noise, thus, when phase noiseis measured according to (25), the buffered clock will exhibit different phase noisefloor than the original signal source. However, this does not mean that the buffer would

46

introduce any additional zero crossing jitter. Here, the buffer is assumed to be noiselessand to have an odd transfer function and therefore it does not affect the zero-crossingpoint of the clock signal.

The phase noise modulating function Acos(x)g′(Asin(x)) is an even function andcan be expanded as a Fourier series

Acos(x)g′(Asin(x)) =cφ (0)

2+

∞

∑n=1

cφ (n)cos(nx) (27)

Where the coefficients cφ (n) are given by

cφ (n) =1π

2π∫0

Acos(x)g′(Asin(x))cos(nx)dx

=1π

g(Asin(x))cos(nx)∣∣∣∣2π

0+

nπ

2π∫0

g(Asin(x))sin(nx)dx

=nπ

2π∫0

g(Asin(x))sin(nx)dx

(28)

The carrier, g(Asin(x)), is an odd function and its Fourier coefficients are given by

cc(n) =1π

2π∫0

g(Asin(x))sin(nx)dx (29)

where it can be seen that cφ (n) = ncc(n). According to the Wiener-Khinchin theorem,the two-sided PSD of a signal is given by the Fourier transform of the autocorrelation ofthe signal. Because the phase noise modulating function, Acos(x)g′(Asin(x)), and thephase error, φ(t), are independent, the voltage domain one-sided PSD, Sv1s( f ), is givenby

Sv1s( f ) = 2F{

Rcφ(τ)Rφ (τ)

}= 2F

{Rcφ

(τ)}∗F

{Rφ (τ)

}=

(∞

∑n=−∞

δ ( f −n fc)c2

φ(n)

2

)∗Sφ ( f )

=∞

∑n=−∞

c2φ(n)

2Sφ ( f −n fc)

=∞

∑n=−∞

n2 c2c(n)2

Sφ ( f −n fc)

(30)

47

where the asterisk(∗) denotes convolution.Carrier power Pc is now equal to c2

c(1)/2, thus the measured phase noise afterbuffering is given by

Sv1s( fc + f )Pc

=∞

∑n=−∞

n2(

cc(n)cc(1)

)2

Sφ ( f − (n−1) fc) (31)

Next, we assume that the buffer is an ideal hard limiter which converts a sine wave to asquare wave. The fourier coefficients of a square wave are given by

cc(n) =

0,n is even

Asq4π

1n,n is odd

(32)

where Asq determines the amplitude of the square wave. Substituting this into (31) yields

Sv1s( fc + f )Pc

=∞

∑n=−∞, n odd

n2(

4πAsq

4πAsq

1n

)2

Sφ ( f − (n−1) fc)

=∞

∑n=−∞, n odd

Sφ ( f − (n−1) fc)

=∞

∑n′=−∞

Sφ ( f +2n′ fc)

(33)

The above result means, that all the phase noise power is wrapped around the oddharmonics without any attenuation. For the white phase noise floor, the result meansthat all the noise power at large frequency offsets folds back into the vicinity of thefundamental frequency, and that all the original phase noise power can now be foundwithin a sideband bandwidth of fc. It should be noted that this is a small-signalapproximation, and in general the result does not hold for close-in phase noise, whosePSD typically approaches infinity for small frequency offsets.

Therefore, using a hard limiter to preprocess the clock signal before PSD measure-ments can be a helpful technique when estimating the jitter due to white phase noisewith an unknown noise bandwidth. When the clock is hard limited and the TDC’s timeinterval jitter is estimated by using the equations shown in Table. 3, the noise bandwidthparameter fNBW can be simply replaced by fre f .

Fig. 21 further illustrates the noise sampling process in the time domain. A hardlimiter effectively samples the noise at zero crossings, and therefore a hard limiteralso attenuates amplitude modulation. In general, any cyclostationary noise process

48

Original and buffered clock signals

Time variant phase noise to voltage coefficient

Fig. 21. Conversion of phase noise to noise voltage when using a hard limiter.

whose envelope is in-phase with the clock signal and has high noise power outside clocktransitions, is attenuated.

In the following section, these results are confirmed by actual measurementsconducted with one of the designed TDCs and a phase noise analyzer.

3.1.3 Clock jitter measurements with a long range TDC

Phase noise induced time interval jitter was studied with the Nutt interpolation methodbased TDC presented in paper I. Without INL compensation, the TDC has a single-shotprecision of about 2ps. Phase noise PSD measurements for various oscillators weremade with a R&S FSUP signal source analyzer.

The TDC uses a 200MHz XO with PECL outputs. The outputs were further bufferedwith a high-speed PECL buffer to ensure fast switching and to provide a hard limitingfunctionality which effectively down-converts all the high-frequency phase noise into afrequency range of fre f . The buffered clock’s phase noise is presented in Fig. 22.

49

The phase noise induced time interval jitter was then estimated using the equationsshown in Table 3. Only the jitter due to 1/ f 3 noise and white noise was evaluated. Since1/ f 3 noise is affected by the observation time, the time interval jitter was evaluated withdifferent observation times ranging from 60 seconds to 1000 years. For white noise, h0

was determined to be about −155dBc/Hz, and for 1/ f 3 noise, h3 was estimated to beabout −35dBc ·Hz2. Since a noise folding hard limiter was used when measuring thephase noise, the noise bandwidth for the white noise is equal to fre f .

The time interval jitter was then measured with the TDC. The input time intervalswere generated by an XO similar to the TDC’s reference clock. Assuming that the phaseerrors of the two clocks are not correlated, the resulting time interval jitter is

√2 times

larger than the jitter of the reference clock alone. Fig. 23 shows the estimated andmeasured time interval jitter for the reference clock. Note that the jitter floor for themeasurements is limited by the TDC’s single-shot precision. The estimated jitter showsthat the phase noise induced jitter floor is about 0.7ps. The very short time intervalswere averaged only for a few seconds and the longer time intervals, in the millisecondrange, were averaged for several minutes. As can be seen the estimated jitter matchesthe measured results quite well. Although the estimated jitter was calculated for variousaveraging times, there are no significant differences between the estimated curves if theobservation time is longer than a minute.

To illustrate the effect of hard limiting a clock signal, a signal generator was usedto generate a 100MHz sine wave and a 200MHz sine wave. A Noisecom UFX7112noise generator was then used to add an identical white noise floor to both sine waveswith high enough power so that the jitter is not masked by the TDCs quantization noise.The phase noise PSDs of the noisy clocks were then measured with and without aPECL clock buffer. The measurement results are shown in Fig. 24. As predicted, thebuffered 100MHz clock exhibits a 3dB higher noise floor than the buffered 200MHzclock, because the effective noise bandwidth is halved but the total noise power staysunchanged. The resulting time interval jitter was then estimated using the bufferedphase noise results. Fig. 25 shows the measured time interval jitter against the estimatedM-sample variance. For the 100MHz clock, the estimated h0 was −125.5dBc/Hz and h3

was−32dBc ·Hz2. For the 200MHz clock, h0 was−128.5dBc and h3 was−26dBc ·Hz2.The estimated time interval jitter uses an observation time of one hour. Again, themeasured jitter matches quite well with the values estimated from PSD measurements.Because the integrated total power of white noise is equal for both clocks, the timeinterval jitter for the 100MHz is two times larger than in the case of the 200MHz clock.

50

100

101

102

103

104

105

106

107

-160

-140

-120

-100

-80

-60

-40

-20

∆f [Hz]

Sφ [

dB

c/H

z]

Fig. 22. Measured phase noise of the 200MHz reference clock ([II], published by permissionof IEEE).

10-7

10-6

10-5

10-4

10-3

10-2

10-1

10-12

10-11

10-10

Time interval ∆T [s]

M-s

am

ple

tim

e in

terv

al jitt

er

σM

[s]

Tobs

=1 minute

Tobs

=1 day

Tobs

=1 month

Tobs

=1 year

Tobs

=10 years

Tobs

=1000 years

Measured

Fig. 23. TDC’s measured and estimated time interval jitter due to phase noise with differentobservation times. Measured jitter floor is limited by the TDC’s precision to about 2ps.

51

102

103

104

105

106

-140

-135

-130

-125

-120

-115

-110

-105

-100

Offset frequency ∆f [Hz]

Sφ [

dB

c/H

z]

200MHz w/o buffer

100MHz w/o buffer

200MHz with buffer

100MHz with buffer

Fig. 24. Measured phase noise PSD for the 100/200MHz clocks with, and without a LVPECLbuffer ([II], published by permission of IEEE).

10-7

10-6

10-5

10-4

10-3

10-2

10-12

10-11

10-10

10-9

Time interval ∆T [s]

M-s

am

ple

tim

e in

terv

al jitt

er

σM

[s]

Estimated 200MHz time interval jitter

Estimated 100MHz time interval jitter

Measured 200MHz

Measured 100MHz

Fig. 25. Measured and estimated time interval jitter for the 100/200MHz clocks. The jitter wasestimated by using the buffered phase noise results ([II], published by permission of IEEE).

52

Spurious tones

Spurious tones can arise in PLL based frequency synthesizers. These spurious tonesare usually located at offset frequencies equal to the operating frequency of the phasedetector and its harmonics. Suppose that a single phase modulating tone with a power ofA2

φrmsis located at an offset frequency of fspur. The resulting time interval jitter can be

then calculated as

σ2∆T =

8

(2π fre f )2

∞∫0

A2φrmsδ ( f − fspur)sin2(π f ∆T )d f

= A2φrms

8

(2π fre f )2 sin2(π fspur∆T ))

(34)

Where δ ( f − fspur) is the Dirac delta function. The resulting time interval jitter willrepeat itself with a period of fspur and the peak jitter occurs at time intervals being equalto (1+2n)/(2 fspur), where n is a natural number.

As an example, Fig. 26 shows the measured phase noise of a commercial Integer-NPLL with a 20MHz input and 194.4MHz output. The 9.72 frequency multiplicationgives a reference divider of 25 and an output divider of 243. This results in a phasedetector frequency of 800kHz, and therefore all the spurious tones in Fig. 26 are locatedat this frequency and its harmonics. Fig. 27 shows the measured and estimated timeinterval jitter, where it can be seen that the spurious tones result in periodic time intervaljitter. The estimated time interval jitter was calculated using (22) and it matches prettywell with the measured results.

3.2 Paper III, Thermal noise and nonlinearity limitations of anintegrated CMOS time-to-voltage converter

Although the measurement range of an interpolator in a Nutt TDC is limited toone reference clock period, time-to-voltage/time-to-amplitude converters are ratherchallenging to implement in modern CMOS processes when their range needs to coverseveral nanoseconds with a linear range close to 10 bits. The difficulties arise from thefinite output resistance of the current source, which makes the integrator lossy and limitsthe time constant associated with the integrator. For each additional bit of resolution, thetime constant needs to be roughly doubled. Furthermore, thermal noise constraints arealso quite strict. Each additional bit requires quadrupling the size of the capacitor andthe current.

53

101

102

103

104

105

106

107

-130

-120

-110

-100

-90

-80

-70

-60

-50

Sφ [

dB

c/H

z]

Offset frequency ∆f [Hz]

Fig. 26. Measured phase noise of a 194.4MHz frequency synthesizer with spurious tones atmultiples of 800kHz ([II], published by permission of IEEE).

10-8

10-7

10-6

10-5

10-4

10-3

10-2

10-12

10-11

10-10

10-9

Time interval ∆T [s]

M-s

am

ple

tim

e in

terv

al jitt

er

σM

[s]

Estimated time interval jitter

Measured time interval jitter

Fig. 27. Measured and estimated time interval jitter due to phase noise and PLL inducedspurious tones ([II], published by permission of IEEE).

54

I

C

ûTin

ADC

RST

inro

inrrrst

Fig. 28. Linearized nonidealities and noise sources in a time-to-voltage/time-to-amplitudeconverter.

Fig. 28 shows typical linearized nonidealities and dominant noise sources in aTVC/TAC. The finite output resistances of the current switch and the current sourceare lumped together as a single small-signal resistance ro. The thermal noise of thecharging current is typically determined by the current source, as the current switchingtransistors are common-gate connected when the current is fully steered to the capacitor,and therefore their noise contribution is small and can be neglected. The reset switch isalso noisy and it contributes a voltage variance of kT/C across the load capacitance.

3.2.1 Thermal noise in a constant current integrator

When aiming for more than 10 bits with a full scale input of several nanoseconds,thermal noise can become the limiting factor and the required capacitor sizes andcharging currents can become quite large for an integrated design. If the constant currentsource is a mosfet operating in the saturation region, the squared noise voltage at theoutput of the TVC due to thermal noise can be written as

v2n(∆T ) =

∫∆T

0

∫∆T

0

E[in(x)in(y)]C2 dxdy

=∫

∆T

0

∫∆T−x

−x

E[in(x)in(x+ τ)]

C2 dτdx

=∫

∆T

0

∫∆T−x

−x

i2n02

δ (τ)

C2 dτdx

=i2n02C2 ∆T =

2kT γgm

C2 ∆T =4kT γIVovC2 ∆T

(35)

55

where i2n0 is the single-sided PSD of the mosfet’s thermal noise in the saturation region.The capacitance and the current needs to be sized according to the full scale time intervaland full scale voltage requirements, i.e. I/C =VFS/∆TFS, thus the noise voltage canalso be written as

v2n(∆T ) =

4γVFS

Vov

∆T∆TFS

kTC

(36)

When the thermal noise of the reset switch is also taken into accout, the total squarednoise voltage at the output is

v2no(∆T ) =

(4γVFS

Vov

∆T∆TFS

+1)

kTC

(37)

The equivalent input-referred jitter is given by dividing the noise voltage by thetime-to-voltage gain VFS/∆TFS

σ2∆T = v2

no(∆T )(

∆TFS

VFS

)2

=∆TFS

VFS

(4γ

∆TVov

+∆TFS

VFS

)kTC

(38)

The maximum jitter is given when the time interval is equal to the full scale input ∆TFS.When the TVC is used as an interpolator and the measurements are asynchronous, theinput to the interpolator is uniformly distributed with an average of ∆T = TFS/2. TheSNR due to the thermal noise is then given by

SNRthermal =∆T 2

FS/12σ2

∆TFS/2=

∆T 2FS/12

v2no(

∆TFS2 )

(VFS

∆TFS

)2

=V 2

FS

12(

VFS2γ

Vov+1) C

kT> 2SQNR = 22B+1

(39)

which should be roughly about two times larger than the SNR due to the quantizationerror of the A/D converter in order not to degrade the total SNR of the converter toomuch. In order to keep the thermal noise below quantization noise, each bit requiresquadrupling the capacitance. The full scale voltage is also fixed due to the ADC, andtherefore the current also needs to be quadrupled. Because the capacitance(area) andcurrent(power) grow quadratically with respect to number of bits, an integrated CMOSTVC is typically best suited for applications that do not require a high number of bits.With modern CMOS technology, this problem can become even more pronounced whenthe full scale voltage range is limited.

As an example, Fig. 29 shows the minimum capacitance and the minimum chargingcurrent, when VFS = 1V, γ = 2/3, Vov = 200mV and ∆TFS = 5ns.

56

6 7 8 9 10 11 12 13 1410

-15

10-14

10-13

10-12

10-11

10-10

Number of bits

Ca

pa

cit

an

ce

[p

F]

6 7 8 9 10 11 12 13 1410

-6

10-5

10-4

10-3

10-2

10-1

Cu

rre

nt

[mA

]

Minimum capacitance

Minimum current

Fig. 29. Thermal noise limited minimum capacitance and minimum current for an N-bit TVC,when VFS = 1VVFS = 1VVFS = 1V, γ = 2/3γ = 2/3γ = 2/3, Vov = 200mVVov = 200mVVov = 200mV and ∆TFS = 5ns∆TFS = 5ns∆TFS = 5ns.

3.2.2 Nonlinearity due to the integrator’s finite time-constant

In terms of linearity, the current source in the time-to-voltage converter needs to havea very large output resistance in order to make the time constant associated with theintegrator large enough. Because of this, a high-resolution TVC can require the use of aMiller connected capacitor or gain boosting techniques in order to achieve the requiredlinearity.

When the integrator is modeled with a single time constant, the TVC’s output voltagefor an input ∆T is given by

∆V (∆T ) =IC

τ

(1− e−

∆Tτ

)(40)

where τ is the time constant roC. This voltage is then converted by an ADC, and theoutput is compensated for offset error and gain error. Neglecting the ADC’s quantizationerror, an estimate for the time interval is given by

∆T̂ = α∆V (∆T )−β (41)

where α is the estimated gain coefficient, and β is the estimated offset term. When theTVC is used as an interpolator and ∆T is uniformly distributed, the optimal values for α

57

and β are straightforwardly found by minimizing the mean squared error. In paper III itis shown, that when the gain coefficient and the offset term are optimally chosen, themeasurement error is given by

∆T̂ −∆T = τ +∆TFS

(12− e−

∆Tτ

1− e−∆TFS

τ

)−∆T (42)

The error variance is given by

σ2τ = E

[(∆T̂ −∆T

)2]−E

[∆T̂ −∆T

]2

= τ2

(1+

112

(∆TFS

τ

)2

− ∆TFS

2τcoth

(∆TFS

2τ

))

= ∆T 2FS

(1

720

(∆TFS

τ

)2

− 130240

(∆TFS

τ

)4

+1

1209600

(∆TFS

τ

)6

− ...

)

≈ ∆T 2FS

(1

720

(∆TFS

τ

)2),τ >> ∆TFS

(43)

The SNR due to the finite time constant is given by

SNRτ =∆T 2

FS/12σ2

τ

≈ 60(

τ

∆TFS

)2

> 2SQNR = 22B+1 (44)

which, again, should be about two times larger than the SNR due to the quantizationnoise of the converter. The time constant roC should be large enough to satisfy

τ >2B∆TFS√

30(45)

This means, that for each additional bit, the time constant should be doubled. As seen in(45), the requirements for the time constant can be also relaxed if the TDC’s referenceclock period, i.e. ∆TFS, can be kept small enough. However, when an external referenceclock is used in order to provide frequency stability, the reference period is usually a fewnanoseconds, at minimum. As an example, Fig. 30 shows the minimum time constantrequired, when ∆TFS = 5ns.

Although a high time constant alone is not too difficult to achieve, it needs to beachieved together with a rather high current, which is in turn required by the full scaleoutput swing and by the thermal noise limitations. For example, a simple solution seemsto be to increase the time constant by increasing the capacitance. However, when the full

58

6 7 8 9 10 11 12 13 1410

-8

10-7

10-6

10-5

10-4

Number of bits

Tim

e c

on

sta

nt

τ [

s]

Minimum time constant τ

Fig. 30. Minimum time constant for an N-bit TVC, when ∆TFS = 5ns∆TFS = 5ns∆TFS = 5ns.

scale voltage and full scale time interval are fixed, then also the ratio I/C is fixed. Thus,if the capacitance is doubled, the current also needs to be doubled, which unfortunatelyresults in a lowered drain resistance in CMOS technology. Assuming the use of longchannel devices, the output resistance is roughly inversely proportional to the current,ro ∝ 1/I. Therefore, the time constant formed by roC cannot be significantly increasedby simply increasing the capacitance. The capacitance should be sized according tothe thermal noise limitations and the linearity needs to be improved by using othertechniques. The time constant could be increased, for example, by using cascode currentsources, gain boosting techniques, or by using a Miller connected integrator capacitor.Some other solutions related to the finite time constant have also been proposed. Forexample, in [77], a pseudo-differential time-to-voltage converter is used to improve thelinearity.

59

60

4 Implemented long range time-to-digitalconverters

In this chapter, the implemented long range time-to-digital converters are presented.Two different Nutt TDCs were designed and tested over the course of this work, eachone of them using different techniques for realizing a high resolution interpolator.

Papers IV and V present an integrated CMOS TDC in 0.35um technology, whichuses cyclic/algorithmic interpolators based on switched-frequency ring oscillators.Whereas an analog time stretcher uses two different charging/discharging currents toamplify a time interval, a switched-frequency oscillator uses two different frequencies toprovide time amplification. This technique was used to replace the traditional TVC witha more robust ring oscillator based design to build a cyclic/algorithmic interpolator.

Paper I presents a TDC implementation based on interpolators using a time-to-voltage converter. The TVCs are implemented with discrete components and use aMiller integrator to improve the linearity of the interpolator.

4.1 Papers IV & V, 4.2ps(RMS) single-shot precision, 327µs rangeintegrated TDC with cyclic switched-frequency interpolators in0.35µm CMOS technology

The goal of this work was to design a high precision time-to-digital converter for apulsed laser radar in CMOS technology. Since a high measurement rate was not needed(10kHz..100kHz typically), mostly cyclic/algorithmic converter architectures werestudied. Initially, dual slope integrators were studied and simulated to achieve timeresidue amplification through the time stretching principle. However, designing aconstant current integrator with sufficient linearity giving more than 10 bits of resolutionseemed unfeasible. This issue would be even more significant, if the design is realizedin scaled technology.

Although the integrator forms the core of a time-stretcher, the integrator, however,does not necessarily have to be a current integrator. One possibility is to use an oscillator.The phase of an oscillator is the time integral of its frequency. Furthermore, the outputof the "frequency integrator"(oscillator), i.e. phase, can be easily quantized with acounter. Whereas the traditional dual slope time-stretcher achieves amplification by

61

switching the load current, an oscillator can achieve time amplification by switching thefrequency. This sparked the idea of using a switched-frequency ring oscillator (SRO) asa replacement for the traditional analog time-stretcher circuit.

Furthermore, with this approach, no traditional analog circuits are required and allcircuit blocks, apart from the ring oscillator, can be built using standard logic cells. Allthe signal processing is essentially digital-like, i.e. all the circuit blocks can be based onrail-to-rail logic level switching. Therefore, the design is suitable for any modern scaledCMOS technology, and significantly benefits from technology scaling in terms of areaand power similar to digital circuits in general.

4.1.1 Time-residue amplification with switched-frequency ringoscillators

For a given time time interval, the increment in phase is given by ∆φ = 2π f ∆T . Here,the frequency is an adjustable coefficient which can be used to change the slope of theintegrator and provide time stretching.

Consider an oscillator which has two operating frequencies, a high frequency fH anda low frequency fL, and whose phase is quantized by a digital clock counter. When atime interval starts, the oscillator is enabled and the phase starts to increase with a slopeof 2π fH . When the time interval ends, the frequency is switched to the lower frequencyfL. The low frequency is enabled until the phase of the oscillator reaches the end of itscurrent clock period. Now, the full periods captured by the counter can be written as

Nro = d fH∆Tine

= fH∆Tin + fL∆TR(46)

where ∆TR is the residual time that it takes for the oscillator to reach the end of its currentclock period after the time interval has ended. Since the quantization is done against thefrequency fH , all the time intervals are now normalized by 1/ fH , e.g. ∆t = fH∆T . Thequantization error can be written as

∆tQ = Nro−∆tin =fL

fH∆tR

⇔∆tR =fH

fL∆tQ

(47)

As can be seen, the time residue ∆tR is equal to the quantization error, ∆tQ, amplifiedby the frequency ratio fH

fL. Fig. 31 illustrates how the frequency switching results in

62

Start

ûtin

Stop

Full clock cycles: Nro=2

CLKro

2��

4��

ûtQ

¥ro

Slope: 2�fH

Full clock cycles: Nro=2

CLKro

2��

4��

ûtR=ûtQ*fH/fL

¥ro

Slope: 2�fH

Slope: 2�fL

With residue amplification

Without residue amplification

Measurement

phase

Residue

generation phase

Fig. 31. A timing diagram illustrating the amplification of quantization error through fre-quency switching ([V], published by permission of IEEE).

amplified time residue. Fig. 32 shows the amplified time residue and the quantizationerror versus input time interval. This frequency switching is the main idea behind thecyclic interpolators used in this work.

Another advantage of the SRO based time residue amplifier is that the input range isonly limited by the size of the clock counter. An analog integrator would require sizingthe load capacitance and the charging current according to the available voltage swingand the required input range.

In order to build a cyclic converter around this amplification mechanism, theamplified time residue needs to be quantized again. A true cyclic converter would usethe same quantizer (i.e. the same SRO and counter) to measure the new time residue.

63

1/fH0 2/fH

0

1/fH

1/fL

ûTin

n/fH

Nro=1 Nro=2 Nro=3 Nro=n...

...

ûT

Q / û

TR

Fig. 32. Time residue and quantization error versus input time interval.

However, the same SRO cannot be used, because it is still busy generating the amplifiedresidue with the lower frequency. A practical converter could use another SRO tomeasure the amplified residue with the higher frequency. This operation is illustrated inthe timing diagram shown in Fig. 33. Here the first SRO is started when the Start edgearrives. The second SRO is started when the Stop edge arrives. After the initial inputtime interval has been quantized by the first SRO, the two SROs are used to quantizeeach other’s amplified time residues. The Fctrl signals control the frequency of each ringoscillator. Because the signal transitions of Fctrl are always synchronous to either of thering oscillators, Fctrl can be generated by simple synchronous digital logic.

Now, assuming that the ring oscillator frequencies are well matched, the counteroutput for the ith quantization cycle can be written as

Nro(0) =∆tin +fL

fH∆tR(0) , i = 0

Nro(i) =∆tR(i−1)+fL

fH∆tR(i) , i > 0

(48)

Solving this recursive equation for ∆tin gives the following result after n quantizationcycles

∆̂t in =n−1

∑i=0

Nro(i)(−β1)i = ∆tin +∆tQ(n−1)(−β1)

n−1 (49)

where β1 is the reciprocal of the time residue gain fH/ fL. The final measurement erroris given by ∆tQ(n−1)(−β1)

n−1.

64

Fc

trl1

Fc

trl2

¥ro

1/¥

ro2

2�

4�

CL

Kro

1

CL

Kro

2

Sta

rt

Sto

p

ût i

nû

t R(0

)û

t R(1

)û

t R(2

)û

t R(3

)

Nro

(0)=

2N

ro(2

)=1

Nro

(4)=

2

Nro

(1)=

1N

ro(3

)=2

f H f L f H f L

Me

as

ure

me

nt

ph

as

eR

es

idu

e g

en

era

tio

nM

ea

su

rem

en

t

ph

as

eR

es

idu

e g

en

era

tio

nM

ea

su

rem

en

t p

ha

se

Me

as

ure

me

nt

ph

as

eR

es

idu

e

ge

ne

rati

on

Me

as

ure

me

nt

ph

as

eR

es

idu

e g

en

era

tio

n

Fig. 33. Timing diagram for a cyclic TDC using two switched-frequency ring oscillators ([V],published by permission of IEEE).

65

4.1.2 Architecture

The architecture of the designed CMOS TDC is shown in Fig. 34. The input latchesconsist of DFFs with their clock inputs tied to Start/Stop signals. This is done to makesure that the Start and Stop signals used for measurement stay high for the duration ofthe whole measurement regardless of the actual pulse widths at the input pins.

Because a Nutt type TDC uses the interpolators only to measure the fractional partsof the reference clock period, the cyclic converters have been slightly modified fromwhat was described in the previous section. The main idea of the residue amplification,however, is the same. Instead of using two SROs, the interpolators rely on a single SROwhose amplified time residues are measured by a reference clock counter rather thananother SRO. Since the reference frequency cannot be switched, amplification is onlyprovided by the ring oscillator and therefore the number of quantization cycles needs tobe doubled in order to achieve the same resolution if two SROs are used.

The traditional synchronization block(see Fig. 2) used in a Nutt type TDC is replacedby two control/synchronization blocks, one for each interpolator. Fig. 35 shows adetailed view of the control/synchronization block and all the counters required bythe TDC. The control/synchronization block is used to generate the frequency controlsignal(Fctrl) for the SRO, and Rre f/ro signals which are used to sample and reset theinterpolator’s counters during measurement.

Only the ring oscillators and the control/synchronization blocks were customdesigned and manually laid out. The counters, shift register banks and read-out logicwere synthesized as digital logic. The design also includes logic used for calibration.The purpose of calibration is to find the interpolator’s actual frequency ratios which areused to resolve the measured time interval. The calibration routine is based on a residuemodulation and correlation method proposed in [78] to calibrate pipeline ADCs. Theactual post processing and digital calibration algorithms are implemented on an FPGAto allow for flexible development of the calibration routines.

4.1.3 Cyclic interpolators

Fig. 36 shows the switched-frequency ring oscillator and the schematic of a single delaystage. The pseudo-differential ring oscillator consists of coupled delay stages to achievedifferential operation. The differential architecture was chosen based on simulations toprovide linear residue amplification. The ring oscillator is reset when the Start signal is

66

6WDUW¶

6WRS¶

Inp

ut

La

tch

es

Sh

ift

reg

iste

r

ba

nk

Sta

rt c

han

ne

l

co

un

ters

Main

co

un

ter

Sto

p c

ha

nn

el

co

un

ters

Sta

rt c

han

ne

l

sy

nc

hro

niz

er/

co

ntr

ol

Sto

p c

ha

nn

el

sy

nc

hro

niz

er/

co

ntr

ol

Dig

ital

po

st-

pro

ces

sin

g

an

d

ca

lib

rati

on

Nre

f(sta

rt)

Nro

(sta

rt)

Nm

ain

Nre

f(sto

p)

Nro

(sto

p)

FP

GA

Fctr

l(sta

rt)

Fctr

l(sto

p)

Sta

rt

Sto

p

CL

Kro

(sta

rt)

CL

Kro

(sto

p)

Rro

(sta

rt)

Rro

(sto

p)

Rre

f(sto

p)

Rre

f(sta

rt)

CL

Kre

f

Sy

nth

es

ize

d

SR

O

SR

O

Fig. 34. Architecture of the CMOS TDC with switched-frequency ring oscillator based inter-polators ([V], published by permission of IEEE).

67

Rre

f(s

top

)

DF

F

DQ

DF

F

DQ

CL

Kre

f

CL

Kre

f

CL

Kre

fN

ma

in

Ma

in c

ou

nte

r

CT

R

ENC

CT

Nre

f

CL

Kre

f

Rre

f(s

tart

)

RE

G

Da

ta

EN

CL

Kre

f

Rre

f(s

tart

)

Nro

CL

Kro

Rro

(sta

rt)

RE

G

Da

ta

EN

CL

Kro

Rro

(sta

rt)

CT

R

CT

=0

CC

T

CT

R

CT

=0

CC

T

Sta

rt c

ha

nn

el

co

un

ters

Sto

p c

ha

nn

el

CL

Kro

CL

Kro

Fc

trl(

sta

rt)

Rre

f(s

tart

)

Rro

(sta

rt)

DF

F1b

DQ

R

DF

F1

a

DQ

R

Sta

rtS

tart

Sta

rtS

tart

DF

F2

b

DQ

R

DF

F2a

DQ

R

CL

Kre

fC

LK

ref

Sta

rt

Sta

rt c

ha

nn

el

sy

nc

hro

niz

er/

co

ntr

ol

Sto

p c

ha

nn

el

Rre

f(s

tart

)

Nre

f

Nro

Fig. 35. Synchronization/control block and the counters used by the TDC ([V], published bypermission of IEEE).

68

Vdd

Vss

Start

Start

Start

FCtrl

FCtrl

Inn-1

Inn-1

Inn-2

Inn-2

Outn

Inn-2 Inn-1

Inn-1Inn-2

Outn

11.2/0.352.8/0.35 3/0.35

6/0.35 6/0.35 6/0.356/0.35

3/0.7 3/0.73/0.73/0.7

1.4/0.7 5.6/0.71.5/0.7

Start

Fig. 36. Pseudo-differential startable switched-frequency ring oscillator used for residueamplification and quantization ([V], published by permission of IEEE).

low, which forces all the node voltages to either VDD or GND. This ensures that thering oscillator always starts from a well defined initial phase. The Fctrl controls thefrequency of the ring oscillator. The frequency switching mechanism should be fast,and it should not introduce any additional phase shifts. Here, the frequency control isrealized by switches which control the effective output resistance of an inverter. WhenFctrl is high, the switches are closed and their resistance lowers the total resistance of theinverter, thus increasing frequency. The switches were sized to give a frequency ratioslightly larger than 2. The frequency switching could be also realised by controlling theload capacitance for each delay stage. If this is realised by disconnecting and connectingcapacitors to the delay stage load, it must be made sure that the capacitors are dischargedwhen they are disconnected. Otherwise the phase information would be stored in thedisconnected capacitors, which would in turn introduce additional phase shifts when the

69

capacitors are connected back to the delay stage output. For this reason, the simplicityof a resistive frequency control seemed more attractive.

The timing diagram of the cyclic interpolator is shown in Fig. 37. First, when theStart edge arrives, the switched-frequency ring oscillator is enabled. The Start signalalso releases the reset for the DFFs used in the control/synchronization block as shownin Fig. 35. After the reset for the DFFs is released, the inverting output of DFF2bstarts to propagate around the synchronization loop, where the signal in the DFFs datapath is alternately synchronized either to the ring oscillator’s clock domain or to thereference clock domain. The Fctrl signal is then generated by a XOR gate connected toappriopriate DFF outputs. The counters are sampled and reset by the synchronous Rre f

and Rro signals.The modified cyclic interpolator operates as follows. First, ∆tstart is quantized by the

switched-frequency ring oscillator. After normalising the time interval by the referenceclock frequency fre f (i.e. ∆t = fre f ∆T ), the output of the ring oscillator counter can bewritten as

Nro(0) =fH

fre f∆tstart +

fL

fre f∆tRro(0)

⇔ ∆tstart =fre f

fHNro(0)−

fL

fH∆tRro(0)

= β2Nro(0)−β1∆tRro(0)

(50)

The ring oscillator’s time residue, ∆tRro(0), is then quantized by the reference clockcounter.

Nre f (0) = ∆tRro(0)+∆tRre f (0)

⇔ ∆tRro(0) = Nre f (0)−∆tRre f (0)(51)

Substituting this result back into (50) gives

∆tstart = β2Nro(0)−β1∆tRro(0)

= β2Nro(0)−β1Nre f (0)+β1∆tRre f (0)(52)

The following cycle would then continue by measuring ∆tRre f (0) with the switched-frequency ring oscillator. In general, for ∆tstart and for all the subsequent referenceclock residues, ∆tRre f (i), we can write

∆tstart = β2Nro(0)−β1Nre f (0)+β1∆tRre f (0)

∆tRre f (i−1) = β2Nro(i)−β1Nre f (i)+β1∆tRre f (i)(53)

70

Me

as

ure

me

nt

ph

as

eR

es

idu

e g

en

era

tio

nM

ea

su

rem

en

t p

ha

se

Re

sid

ue

ge

ne

rati

on

Me

as

ure

me

nt

ph

as

e

ût s

tart

ût R

ro(0

)û

t Rre

f(0

)û

t Rro

(1)û

t Rre

f(1)

ût s

tart

Nro

(0)=

2N

ro(1

)=1

2�

4�

¥re

f/¥

ro

Sta

rt

CL

Kre

f

CL

Kro

Fc

trl

Me

as

ure

me

nt

ph

as

eR

es

idu

e g

en

era

tio

nM

ea

su

rem

en

t

ph

as

eR

es

idu

e

ge

ne

rati

on

Nre

f(0

)=2

Nre

f(1

)=1

Fig. 37. Timing diagram for a cyclic interpolator using only one switched-frequency ringoscillator ([V], published by permission of IEEE).

71

Now the measurement result ∆̂tstart can be written as

∆̂tstart =n−1

∑i=0

(β2Nro(i)−β1Nre f (i)

)β

i1

= ∆tstart −∆tRre f (n−1)β n1

(54)

where ∆tRre f is the error of the nth cycle, which can have any value between 0 and 1. Inpractice, the frequency ratio parameters β1 and β2 are also affected by PVT variationsand therefore a foreground calibration routine is used to resolve and track the frequencyratios.

4.1.4 Digital calibration

The interpolators’ digital output is calculated according to Eqn. (54). In order toaccurately measure the time intervals, the frequency ratio parameters β1 and β2 needto be precisely known. The ring oscillator frequencies could be locked to an externalreference with a PLL, but incorporating an additional frequency control loop around thefrequency switching mechanism would be complex. Instead of locking the ring oscillatorfrequencies to predefined β1 and β2, the ring oscillator is a free running oscillator and acalibration routine is used to resolve and track the frequency ratios in digital domain.The operating principle of this calibration routine is similar to the digital backgroundcalibration method proposed in [78] to calibrate pipeline ADCs. The main concept ofthis method is to modulate the quantization errors and then correlate the converter outputwith the same modulating sequence in the digital domain. One significant property ofthis calibration method is that the residue modulation does not introduce any additionalerrors if the parameters have been correctly estimated. This means that the method canbe used flexibly for both, foreground and background, calibration purposes.

Fig. 38 shows a modified version of the synchronization and calibration block,which now has an additional DFF on each side of the loop for residue modulation. WhenCALro or CALre f signal is high, an additional offset of one clock cycle is added to theirrespective residues.

Now, ∆tstart , ∆tRro and ∆tRre f are rewritten as

∆t ′start = ∆tstart +CALre f

∆t ′Rro(i) = ∆tRro(i)+β2

β1CALro

∆t ′Rre f (i) = ∆tRre f (i)+CALre f

(55)

72

CLKro CLKro

Fctrl(start)

Rref(start)

Rro(start)

DFF1c

D QR

DFF1a

D QR

Start Start

Start Start

DFF2c

DQR

DFF2a

DQR

DFF1b

QR

SDSE

D

CLKref CLKrefCLKref

DFF2b

QR

SDSE

D

CLKro

CALref

CALro

Start

Start

Start

Fig. 38. A modified synchronization and control block used for residue modulation ([V],published by permission of IEEE).

The idea is to use CALre f ,ro to modulate ∆t ′Rro(i) and ∆t ′Rre f (i), and then correlate thedigital output of the converter with the same modulating sequence. The time intervalmeasured by the Start channel interpolator, given in (53), is rewritten as follows

∆̂tstart =n−1

∑i=0

(β̂2Nro(i)− β̂1Nre f (i)

)β̂

i1−CALre f (56)

The interpolator counter outputs Nro(i) and Nre f (i) are now given by

Nro(i) =

∆t ′start

β2+

β1

β2∆t ′Rro(i) , i = 0

∆t ′Rre f (i−1)

β2+

β1

β2∆t ′Rro(i) , i≥ 1

Nre f (i) = ∆t ′Rro(i)+∆t ′Rre f (i)

(57)

73

where ∆t ′Rro(i) and ∆t ′Rre f (i) are the ith time residues which are modulated by theadditional DFFs. Substituting these back into Eqn. (56) we get

∆̂tstart =β̂2

β2∆t ′start −CALre f

+β1

(β̂2

β2− β̂1

β1

)n−1

∑i=0

∆t ′Rro(i)β̂i1

+ β̂1

(β̂2

β2−1

)n−2

∑i=0

∆t ′Rre f (i)β̂i1

(58)

where β1,2 are the real parameters and β̂1,2 are the estimated parameters. An importantthing to notice is that the time residues, ∆t ′Rro(i) and ∆t ′Rre f (i), are multiplied by the terms(

β̂2β2−1)

and(

β̂2β2− β̂1

β1

). These two terms will be zero if the estimated parameters β̂1,2

are equal to the actual parameter values β1,2. When the digital output of the converter iscorrelated with the modulating bit sequences, the two terms can be independently solvedin the digital domain and driven to zero by adjusting the parameters accordingly.

Substituting the modulated time residues from (55) into (58) gives the following forthe interpolator’s output

∆̂tstart =β̂2

β2∆tstart

+

(β̂2

β2− β̂1

β1

)n−1

∑i=0

∆tRro(i)β̂ i1

+ β̂1

(β̂2

β2−1

)n−2

∑i=0

∆tRre f (i)β̂ i1

+CALro

(β̂2

β2− β̂1

β1

)β2

n−1

∑i=0

β̂i1

+CALre f

(β̂2

β2−1

)n−1

∑i=0

β̂i1

(59)

Assuming that CALro,re f does not correlate with ∆tstart ,∆tRre f or ∆tRro, the parameter er-ror terms

(β̂2β2−1)

and(

β̂2β2− β̂1

β1

)can be solved by simply correlating the interpolator’s

digital output with the modulating sequence CALro,re f . The modulating bit sequencesshould be chosen so that, CALre f and CALro also do not correlate with each other. Inbackground calibration mode, a pseudo-random sequence should be used so that thebit sequence does not correlate with ∆tstart . Because ∆tstart can be totally random, i.e.

74

uniformly distributed over a reference clock cycle, background calibration requires along averaging time with a small update step size in order to attenuate ∆tstart . However,when foreground calibration is used, ∆tstart is generated from the main reference clock,i.e. ∆tstart can be made constant and synchronous to the reference clock. In this case theparameters can be rapidly resolved with a shorter modulating sequence since the input isnow static rather than noisy. In this work, only the foreground mode is used.

On the FPGA, the interpolator result is first calculated according to Eqn. (56). Thisresult is then used to update the parameter values as follows

β̂1(n+1) = β̂1(n)+

{+α∆̂tstart(n),CALro = 1

−α∆̂tstart(n),CALro = 0

β̂2(n+1) = β̂2(n)+

{−α∆̂tstart(n),CALre f = 1

+α∆̂tstart(n),CALre f = 0

(60)

where α is the update step-size. When correlating the output with CALro,re f , nomultiplication is actually needed as CALro,re f only controls the sign of the update step.

4.1.5 Measurement results

A photograph of the TDC circuit, fabricated in 0.35µm CMOS technology, is shown inFig. 39. The total area without the pad ring is 0.61mm2, which also includes a largenumber of bypass capacitors which were used to fill areas not occupied by the activecircuitry. The interpolators, including the SROs and the control/synchronization logic,take up about 25% of the area. The rest of the area is taken up by the synthesizedcounters and a large shift register bank which temporarily stores the raw results. Theregister bank alone uses about 0.36mm2 of the area. The TDC operates with a 3.3Vsupply and the total power consumption is about 80mW at an 800kHz measurement rate.The combined power consumption of the two interpolators is about 20mW. 60mW isconsumed by the synthesized logic. Out of the 60mW, about 48mW is consumed by thelarge 338-bit shift register bank, which temporarily stores all the raw data producedby the interpolators and the main clock counter. The large power consumption can beexplained by the used technology and the fact that no special techniques, such as clockgating, were used for the digital part of the circuit. Fig. 40 also shows a photograph ofthe designed PCB used for the measurements and characterizing the TDC’s performance.

The nominal frequencies for the ring oscillators were designed to be about 300MHzand 140MHz, giving a frequency ratio slightly above 2. A 200MHz external reference

75

Fig. 39. The chip micrograph of the designed TDC ([V], published by permission of IEEE).

Fig. 40. A photograph of the test PCB used for measurements and characterizing the TDC.

76

was used for the main clock counter. The reference frequency could be significantlysmaller if required. The reference frequency is constrained by the size of the countersused by the interpolators. Here, the counters were rather conservatively sized as 5 bitswide. The wide counters also give plenty of headroom for PVT variations which affectthe ring oscillator frequencies. Taking into account the additional offset introduced bythe synchronization block with calibration DFFs, the lower and upper bound for thereference frequency is given by

3 fH

2Bro −3< fre f < fL

(2Bre f

3−1)

31MHz < fre f < 1.35GHz(61)

Interpolator nonlinearity and single-shot precision

When measuring asynchronous time intervals, the static linearity of a Nutt methodTDC is inherently guaranteed. However, the interpolator nonlinearities appear as anoise-like dynamic error. The interpolator nonlinearity was measured by asynchronousmeasurements. Since the arrival time of the input pulse is random with respect to thereference clock, the interpolator results are uniformly distributed between 0 and Tre f .The DNL and INL can be then easily calculated from the collected result distribution.Fig 41 shows the measured nonlinearity for both interpolators. The peak value ofthe nonlinearity is about ±4.5ps and the effective number of bits is 9.27 for the Startchannel, and 9.52 for the Stop channel. The nonlinearity is almost identical in bothinterpolators, thus the nonlinearity probably stems from some deterministic error sourcerather than random mismatch errors.

Fig. 42 shows the measured single-shot precision(σ -value) for the full TDC, whenthe inputs were asynchronous with respect to the reference clock, and the time intervalwas swept over a full reference clock cycle. The RMS value along the full clock periodis about 4.2ps. Since the nonlinearity of both interpolators is almost identical, theminimum single-shot precision is achieved when the input time interval is an integermultiple of the reference clock period when the interpolator nonlinearities cancel out.

Fig. 43 illustrates the impact of interpolator nonlinearity on single-shot precision.First, a look-up table consisting of the interpolator INL was collected. This look-up tablewas then used to compensate for the nonlinearity errors. By using INL compensation,the single-shot precision in Fig. 42 is improved close to 1ps, which now mostly consistsof only random jitter (noise) and quantization error.

77

0 1000 2000 3000 4000 5000 6000 7000 8000-0.5

0

0.5

BIN #

DN

L [ps]

Start

Stop

0 1000 2000 3000 4000 5000 6000 7000 8000-5

0

5

BIN #

INL [ps]

Fig. 41. DNL and INL for the Start and Stop channel interpolators ([V], published by permis-sion of IEEE).

Calibration and temperature stability

The digital calibration routine is handled on an FPGA. Only the foreground calibrationmethod is used in this work. Fig. 44 shows the estimated parameter values after start-upwhen the parameters were first initialized with β1 = 0.5 and β2 = 1. It takes roughlyabout 15000 calibration measurements for the parameters to converge to their finalvalues. The digital calibration also ensures that the TDC’s temperature dependence isminimal. Fig. 45 shows the estimated parameter values when the TDC was placed in atemperature test chamber and the temperature was swept from −30◦C to 70◦C. Sincethe ring oscillator’s frequency is highly temperature dependent, β2(i.e. fre f / fH ) is seento vary almost ±11% through the whole temperature range. β1(i.e. fL/ fH), however,remains almost constant throughout the entire temperature range.

78

55 55.5 56 56.5 57 57.5 58 58.5 59 59.5 600

1

2

3

4

5

6

7

8

Time interval [ns]

Sin

gle

-sh

ot

pre

cis

ion

[p

s]

Single-shot precision

INL compensated precision

Fig. 42. Asynchronous single-shot precision over a full reference clock period with andwithout INL compensation ([V], published by permission of IEEE).

34.975 34.98 34.985 34.99 34.995 35 35.005 35.010

0.05

0.1

0.15

0.2

0.25

0.3

0.35

Time interval [ns]

Hits(n

orm

aliz

ed

)

Raw results, σ=1.944ps

INL compensated, σ=0.925ps

Fig. 43. Single-shot precision when INL errors are compensated. The blue curve representsraw TDC results and the red curve has been INL compensated ([V], published by permissionof IEEE).

79

0 0.5 1 1.5 2

x 104

0.4

0.5

0.6

0.7

0.8

0.9

1

Calibration measurement #

Pa

ram

ete

r va

lue

β1

β2

Fig. 44. Parameters β1β1β1 and β2β2β2 after start-up ([V], published by permission of IEEE).

-30 -20 -10 0 10 20 30 40 50 60 700.45

0.5

0.55

0.6

0.65

0.7

0.75

0.8

Temperature [C]

Para

mete

r valu

e

β1

β2

Fig. 45. Interpolator parameters when the temperature was swept from -30C to 70C.

80

-30 -20 -10 0 10 20 30 40 50 60 7020.04

20.045

20.05

20.055

Temperature [C]

Tim

e inte

rval [n

s]

-30 -20 -10 0 10 20 30 40 50 60 701

1.5

2

2.5

Sin

gle

-shot

pre

cis

ion [

ps]

Time interval

Single-shot precision

Fig. 46. Single-shot precision and mean time interval when the temperature was swept from-30C to 70C ([V], published by permission of IEEE).

Fig. 46 shows the mean time interval and single-shot precision during the temperaturesweep. The mean time interval varies only ±2.5ps through the whole temperaturerange, representing very good temperature stability. Some of this drift is caused bythe temperature dependence of the reference oscillator. If the reference frequencychanges by ∆ fre f , the measured time interval will change by (∆ fre f / fre f )∆Tin. The usedreference oscillator is specified for ±25ppm frequency stability in the used temperaturerange, thus it does not completely explain the drift. Other sources for this error could bein the signal path of the Start/Stop channels, where coaxial cables were used to createthe measured time interval. The temperature test chamber also heats the coaxial cables,which will affect the delay of the cables and the time interval under measurement. Thesmall variations in the single-shot precision can be explained by the drift in absolute ringoscillator frequencies, which can potentially affect the nonlinearity of each interpolator.

Linearity

As discussed in Section 2.2, a Nutt method TDC should be inherently linear withasynchronous measurements. The nonlinearity of the full TDC was measured by havingan asynchronous Start signal and a fixed frequency Stop signal. Thus, all the measured

81

0 100 200 300 400 500 600 700 800 900 1000-5

-4

-3

-2

-1

0

1

2

3

4

5

Time interval [ns]

INL[p

s]

Fig. 47. Measured INL of the full TDC in a range of 900ns ([V], published by permission ofIEEE).

time intervals are uniformly distributed within the period of the Stop signal. Then ausual code density testing was used to find the nonlinearity of the whole TDC. However,it should be noted that this method requires a large number of measurements when themeasurement range is long. It is shown in [79] that the uncertainty of the estimated INLis proportional to Trange

2√

N, where Trange is the range of the uniform distribution and N is

the number of measurements. Here, the frequency of the Stop pulse was set to about1.11MHz in order to limit Trange to 900ns. This was done to reduce the uncertainty,and the measurement time. About 30e9 measurements were done, which gives anuncertainty of about 2.6ps. The measured nonlinearity is shown in Fig. 47. The peakvalue is close to −3ps, which can be explained by the uncertainty of the measurementmethod.

4.2 Paper I, 2ps single-shot precision, 84ms range discrete TDCwith interpolators based on a time-to-voltage conversion

4.2.1 Architecture

Fig. 48 shows the architecture of the designed time-to-voltage based Nutt TDC. TheTDC is constructed using discrete components, and it uses a 200MHz reference clock

82

with two TVCs as interpolators. Since the TVC was designed using discrete components,the capacitor and current could be more flexibly chosen compared to an integratedCMOS realization. Furthermore, in order to boost the linearity, a Miller-integrator basedtopology was chosen.

High-speed comparators with differential PECL outputs are used at the inputs ofthe TDC. The threshold voltage is set by a DAC, which in turn is controlled by anFPGA. In order to achieve good jitter performance, the synchronizer is constructed usingdifferential LVPECL components. Since the PECL components consume a lot of power,all other logic was located on the FPGA. The main counter on the FPGA was nominallyset to 16 bits, which can be easily increased by reprogramming. Other than that, theFPGA mainly acts as a high-speed controller which is interfaced to a PC through a USBbus. The comparator threshold voltage, ADC reference voltage, TVCs’ offset trimmingvoltage and the TVCs’ charging current can be controlled through the FPGA and a PCtest software. On the FPGA, a circular buffer uses on-chip RAM to temporarily store theresults before they are read out by the PC through the USB interface. The measurementrate is limited to about 150kHz by the full-speed USB interface(FT245R) which onlysupports speeds up to 1MB/s.

The TDC uses two identical TVCs as interpolators. A detailed view of the TVC’sschematic is shown in Fig. 49. A 1GHz GBW operational amplifier(ADA4817) withFET inputs is used as a Miller-integrator. An operational amplifier with FET inputs isrequired, since any input bias current would cause additional charge on the feedbackcapacitance. As discussed in paper III, the linearity requirements for a TVC can be quitestrict, for which reason a Miller-integrator was used to ensure linearity by boosting theeffective time constant. The TVC’s capacitor is 100pF, while a charging current ofabout 30mA is used. This gives a full scale voltage swing of 3V, when also taking intoaccount the additional one clock cycle offset introduced by the synchronizer. Anotheroperational amplifier is used to subtract the offset and amplify the TVC’s output voltageto cover the full scale of the A/D-converter’s input. The A/D converters are AD7980with 16 bits of resolution and use an SPI interface to connect with the FPGA.

83

Fig. 48. Architecture of the discrete TDC with time-to-voltage converters ([I], published bypermission of IEEE).

84

Fig. 49. Schematic of the time-to-voltage converter ([I], published by permission of IEEE).

4.2.2 TVC calibration

The TDC’s output is calculated according to

∆̂t = Nre f + ∆̂tstart − ∆̂tstop (62)

where Nre f is the reference counter output and ∆̂tstart and ∆̂tstop are the interpolatoroutputs. If we consider the start channel interpolator, the TVC’s ADC output, xadc,is assumed to be linearly proportional to the time interval ∆tstart , i.e. the interpolatoroutput is calculated according to ∆̂tstart = αxadc−β , where α is the estimated gaincoefficient and β is the estimated offset term, which need to be resolved.

The parameters are chosen so that the mean squared error is minimized whenasynchronous measurements are made, i.e. when ∆tstart and ∆tstop are uniformlydistributed between 0 and 1. Differentiating the expected squared error with respect tothe parameters gives

ddα

E[(

∆̂tstart −∆tstart

)2]= 2E

[αx2

adc−βxadc−∆tstartxadc

]= 0

ddβ

E[(

∆̂tstart −∆tstart

)2]=−2E

[αxadc−β −∆tstart

]= 0

(63)

85

Solving the parameters yields

α =Cov[xadc,∆tstart ]

Var[xadc]

β = αE[xadc]−E[∆tstart ]

(64)

The covariance of xadc and ∆tstart could be solved by collecting the INL table for theinterpolator, however, the covariance can be also approximated with a more simpleapproach. Suppose that the ADC output xadc can be split into a linear part and a nonlinearpart, xadc = xlin + xinl . The linear part is approximated as xlin = ∆tstart/α + xos, wherexos is an offset term. Assuming that xinl is small and does not correlate with ∆tstart , (64)can be rewritten as

α =Cov

[∆tstart

α+ xinl + xos,∆tstart

]Var[xadc]

α =

√Var[∆tstart ]+αCov[xinl ,∆tstart ]

Var[xadc]

≈

√Var[∆tstart ]

Var[xadc]=

12√

3Var[xadc]

β = αE[xadc]−E[∆tstart ]

=12

(E[xadc]√3Var[xadc]

−1

)(65)

In order to resolve the parameters, asynchronous measurements are used to determinethe mean value and the variance of xadc. The time interval under measurement does notaffect the calibration result as long as the measurements are asynchronous, i.e. when∆tstart and ∆tstop are uniformly distributed.

4.2.3 Measurement results

Fig. 50 shows a photograph of the designed TDC with analog TVCs. The PCB is about10.5cm x 11cm. After calibration, the TVCs’ INL was obtained by code density testing.An asynchronous and constant time interval was measured, thus the fractional timeintervals measured by the TVCs were uniformly distributed and the INL could be easilycalculated. The INL results are shown in Fig. 51, where it can be seen that the peaknonlinearity error is about ±2.5ps.

86

Fig. 50. Photograph of the designed TDC with analog TVC interpolators ([I], published bypermission of IEEE).

Fig. 52 depicts the measured single-shot precision with and without INL correction.The INL corrected results were obtained by first collecting the discrete probabilitydistribution of the TVC results. A look-up table was then constructed by calculating thediscrete cumulative distribution function.

CDF(i) =i

∑j=0

n( j)N

(66)

where n( j) is the number of results accumulated in channel j and N is the total numberof measurements. This CDF corresponds to the transfer function of the TVC, thus it issuitable for correcting the nonlinearity related errors. As can be seen in Fig. 52, usingonly the linear parameters α and β , the peak single-shot precision is about 1.8ps whenF = 1/2. When the CDF LUT is used, the single-shot precision is dominated by thermalnoise and jitter, which results in a uniform single-shot precision of 1ps.

87

0 0.2 0.4 0.6 0.8 1−4

−2

0

2

4

Fractions of full clock cycle

TA

C1 IN

L [ps]

0 0.2 0.4 0.6 0.8 1−4

−2

0

2

4

Fractions of full clock cycle

TA

C2 IN

L [ps]

Fig. 51. INL of the TVC based start and stop interpolator channels ([I], published by permis-sion of IEEE).

370 371 372 373 374 3750.8

1

1.2

1.4

1.6

1.8

2

Time interval [ns]

Sin

gle

−shot pre

cis

ion [ps]

Ideal gain & offset

CDF LUT

Fig. 52. Single-shot precision of the TDC with and without INL correction ([I], published bypermission of IEEE).

88

Fig. 53 and Fig. 54 shows the accuracy and single-shot precision of the TDCwhen temperature was swept from 0C to 50C. After the TDC was calibrated at roomtemperature, the temperature was swept and results were collected using the linearparameters. Fig. 53 depicts the results collected when the time interval was an integermultiple of the reference clock cycle. Fig. 54, on the other hand, was collected when thetime interval’s fractional part F was equal to 1/2.

Since the TVCs are rather well matched, the mean value of results changes only alittle during the sweep. However, when the single-shot precision is considered, theeffective precision deteriorates quickly, because the gain parameter α varies withtemperature and the precalibrated parameter no longer matches the real value.

Fig. 55 shows the static nonlinearity of the full TDC in the range of 50ns whenasynchronous measurements are made. The results were collected by using an asyn-chronous start signal and a stop signal with a fixed frequency of 20MHz. This way,the time intervals measured by the TDC are uniformly distributed between 0 and 50nsand the nonlinearity can be solved. The high nonlinearity when measuring short timeintervals is probably due to cross-talk between the start and stop channels when bothchannels are working at the same time. The peak error is about ±10ps and after about10ns, the nonlinearity drops below ±1ps.

0 10 20 30 40 50−5

0

5

Temperature [C]

Err

or

of

the

me

an

[p

s]

0 10 20 30 40 500

10

20

Temperature [C]

Sta

nd

ard

de

via

tio

n [

ps]

Fig. 53. Accuracy and single-shot precision of the TDC during a temperature sweep andwhen F = 0 ([I], published by permission of IEEE).

89

0 10 20 30 40 50−5

0

5

Temperature [C]

Err

or

of

the

me

an

[p

s]

0 10 20 30 40 500

10

20

Temperature [C]

Sta

nd

ard

de

via

tio

n [

ps]

Fig. 54. Accuracy and single-shot precision of the TDC during a temperature sweep andwhen F = 1/2 ([I], published by permission of IEEE).

0 10 20 30 40 50−15

−10

−5

0

5

10

15

Time interval [ns]

INL

[p

s]

Fig. 55. Static nonlinearity of the full TDC in the range of 50ns ([I], published by permissionof IEEE).

90

5 Discussion

TDCs, and time-mode signal processing in general, have been gaining a lot of interestin the past few years due to new application areas, technology scaling and due to thepotential advantage of processing digital-like time-mode signals, where pulse lengths, orthe relative phase between signals, are processed instead of voltage or amplitude levels.Some of the emerging applications for TDCs are, for example, frequency synthesis,sensor arrays(FLIM, TOF-PET, Raman spectroscopy), A/D conversion, etc. Many ofthese applications require only a short measurement range. Some other applicationshowever, such as ToF based pulsed laser radar, require a longer measurement range withstability requirements that are difficult to achieve with a fully integrated CMOS solution.These long range TDC architectures usually have to rely on the Nutt interpolationmethod, where an external high quality oscillator can be used to provide the requiredstability and low jitter, and where the short range TDC architectures are utilized asinterpolators providing the picosecond level resolution.

The aim of this work was to study and develop techniques related to the Nutt interpo-lation method in order to achieve a measurement range of hundreds of microsecondswith a precision of a few picoseconds. The developed new interpolator architectures,combined with the Nutt method, allow for both of these goals to be achieved. Itis important to note that the Nutt interpolation method differs significantly from aconventional data converter. The ability to conduct asynchronous measurements can beused to scramble quantization related errors, which improves linearity and makes itpossible to filter out the interpolators’ static errors.

Part of this work also focuses on the reference oscillator related errors, whicharise from the different phase noise processes associated with the oscillator. In theliterature, typically only thermal noise induced phase noise( f−2 noise) is consideredwhen time-interval jitter is estimated. However, a phase noise PSD can also consist ofseveral other power-law noise processes. In this work, the conversion of power-lawnoise to time-interval jitter is thoroughly analyzed and the results can be used to ease theprocess of evaluating oscillator jitter when long range time-interval measurements areconsidered.

Two time-to-digital converter architectures have been developed in the course ofthis work. Both of the TDCs have a range exceeding several hundred of microseconds

91

and their measurement precision is in the range of few picoseconds. The first oneis based on using a TAC and an ADC as an interpolator. The interpolators are builtout of discrete components while other functionality is implemented on an FPGA.The second TDC is implemented in 0.35µm CMOS technology and utilizes switched-frequency ring oscillators to build a cyclic/algorithmic interpolator. A digital calibrationroutine was also developed, which is suitable for both, background and foregroundcalibration. The calibration routine guarantees that the TDC’s accuracy is stabilizedagainst temperature and voltage variations. Although it is important to stabilize a TDCagainst PVT variations, temperature and voltage variations are quite often ignoredin publications, although the basic building block for any CMOS TDC, i.e. a delayline/ring oscillator, can have a significant temperature dependence.

5.1 Performance summary and comparison

Table 4 summarises the performance and provides a comparison of the cyclic CMOSTDC of Papers IV and V against other integrated long range TDCs based on the Nuttinterpolation method. Apart from [80], the cyclic TDC achieves better single-shotprecision and INL than any other design. [80] uses DNL calibration by having a 5-bitbinary scaled load capacitance matrix on each delay cell to compensate for delaymismatches. This, however, requires the authors of [80] to first measure a large DNLlook-up table for each interpolator, after which the TDC can be reprogrammed tocompensate for the DNL.

The total power consumption of the designed TDC is about 80mW. The twointerpolators consume about 20mW, and 60mW is taken by the synthesized digital logic.Out of the 60mW, about 48mW is consumed by a large 338-bit shift register bank, whichtemporarily stores all the raw data produced by the interpolators and the main clockcounter. The large power consumption can also be explained by the used technology andthe fact that no special low power techniques, such as clock gating, were used for thedigital part of the circuit. Most of the circuit area is also taken up by the shift registerbank. However, the core area of the TDC could have been also made smaller than itcurrently is. Because the design was pad limited, the TDC’s floorplan was stretched touse all the available area inside the pad-ring, with empty spaces being filled with bypasscapacitors.

Table 5 compares the performance of a single interpolator of the cyclic CMOSTDC to various recently published short-range TDCs which are not based on the Nutt

92

interpolation method. The area and power of the interpolator are partially estimated,since the interpolator’s counters are mixed with other non-related synthesized digitallogic in the actual circuit. The designed TDC is the only design realized in 0.35µmtechnology, which partially explaines the larger area and power of the TDC. The lowestabsolute INL values are achieved by using a TAC+ADC, however, this is achieved at thecost of a very limited dynamic range, which relieves the linearity requirements for aconstant current integrator quite significantly. The designed TDC achieves the highestnumber of linear bits of all the designs in the comparison table. However, it should benoted, that the number of linear bits is probably not suitable for comparing all kindsof TDC architectures. For example, a simple counter based TDC can be designed tohave a very wide dynamic range by simply increasing the size of the counter, which inturn does not affect the INL. Because of this, the number of linear bits can be madearbitrarily high. Moreover, many of the designs in the comparison table are aimed atfrequency synthesis, where the linear range of the converter does not have to exceed therange of few hundred picoseconds.

Table 6. compares the performance of the TAC based discrete TDC (Paper I) withother Nutt interpolation method based designs using either discrete components or anFPGA. Usually FPGA TDCs are based on delay lines, with a resolution limited by thegate propagation delays. Although the gate propagation delays in modern FPGAs can berelatively short(≈ 30ps), TAC based designs can still provide better performance in termsof precision. On an FPGA, it is difficult to maintain propagation delay homogeneityalong a delay line, which results in a large INL that can be close to ±100ps. Somespecial techniques have been introduced, for example, in [46, 47, 90] to improve theresolution and INL beyond the gate delay limit. For example, in [46, 47], an interpolatorconsists of several independent delay lines in parallel, and this redundancy is used toimprove the effective bin widths beyond the gate delay limit. Nonetheless, an INLcompensation scheme is still required in order to bring down the single-shot precisioncloser to the levels achieved with a discrete TAC realization.

93

Table4.C

omparison

with

integratedlong

rangeTD

Cs.

Reference

Tech.Type

Range[µs]

LSB

[ps]IN

L[ps] (1)

σssp [ps]

Area[m

m2]

Power[m

W]

PaperIV

&V

0.35µmC

yclic327

0.61±

4.54.2/1.1

(2)

0.61/0.25(8)

80/32(8)

[43]0.35µm

Vernier0.16

10N/A

17.20.3

80[81]

0.35µmVernier

>0.05

37.5

±13.1

37.50.22

150[71]

0.35µmS

AR

3271.22

±20

11/3.2

(2)

4.454

33[9]

0.35µmP

arallelscaleddelay

lines74

8.88±

128.6/8

(2)

8.88(3,4)

85(3)

[82]0.6µm

Parallelscaled

delaylines

49629.6

±35

27.5/16

(2)

N/A

50[80]

0.13µmD

elayline

&resistive

interpolationN/A

5±

4(6)

3.45(6)

1.29(7)

335(7)

[83]0.35µm

Segm

enteddelay

lines1000

7.5±

407.5

(2)

9.3(4)

N/A

[7]0.13µm

Tappedring

oscillator0.100

13N/A

201.69

4,5

45(5)

[84]0.18µm

Tappedring

oscillator18

41±

27N/A

0.0925

[85]0.18µm

BiC

MO

SA

nalogtim

estretcher

1882.9−

11.4±

1512

7.84(5)

148(5)

[61]0.8µm

BiC

MO

SA

nalogtim

estretcher

2.5

32N/A

3011.9

350[62]

0.35µmm

Analog

time

stretcher0.25

50±

55N/A

0.230.75

[86]0.35µm

Analog

time

stretcher>

1.46357

±250

N/A

0.1261.22

(1)InterpolatorINL.

(2)INL

compensated

precision.(3)A

rea/Powerw

ith7

interpolators.(4)Includes

areataken

bypad

ring.(5)A

rea/Powerofa

ToFreceiverfront-end

+TD

C.

(6)AfterD

NL

calibration.(7)A

rea/Powerw

ith8

interpolators.(8)E

stimated

area/powerw

ithoutthe338-bitreadoutregisterbank.

94

Tabl

e5.

Inte

rpol

ator

com

pari

son

with

inte

grat

edsh

ortr

ange

TDC

s.

Ref

eren

ceTe

ch.

Type

Ran

ge[n

s]B

itsLS

B[p

s]IN

L[ps

]Li

near

Bits

(3)

Are

a[m

m2 ]

Pow

er[m

W]

Pap

erIV

&V

0.35

µmC

yclic

513

0.61

±4.

59.

930.

036+

0.04

3(2)

10+

6(1)

[69]

0.13

µmC

yclic

0.32

81.

25±

2.5

6.41

0.07

4.3

[70]

28nm

Cyc

lic2.

612

0.63

±2.

49.

730.

010.

82[6

5]65

nmP

ipel

ine

0.57

91.

12±

27.

520.

1414

[67]

0.13

µmP

ipel

ine

1.8

101.

76±

3.3

8.47

2.83

115

[68]

0.13

µmP

ipel

ine

1.3

110.

63±

3.8

8.18

0.32

10.5

[72]

65nm

SA

R10

109.

8±

178.

550.

119.

6[6

3]90

nmTw

o-st

ep0.

649

1.25

±3.

86.

980.

63

[66]

65nm

Two-

step

0.48

73.

75±

7.5

5.42

0.02

3.6

[52]

0.13

µmVe

rnie

r32

.812

8N/A

N/A

0.26

7.5

[54]

65nm

2D-V

erni

er0.

617

4.8

±9.

65.

410.

021.

7[8

7]0.

13µm

3D-V

erni

er14

.311

7±

10.5

9.68

0.28

0.33

[57]

90nm

TAC

+AD

C±

0.26

91

±1.

57.

680.

3120.4

[77]

65nm

TAC

+AD

C0.

329

0.63

±1.

96.

990.

063.

73[8

8]65

nmTA

C+A

DC

0.22

80.

84±

1.7

6.4

0.06

2.47

[89]

90nm

Res

istiv

ein

terp

olat

ion

0.6

74.

7±

4.7

60.

02N/A

(1)E

stim

ated

pow

erof

inte

rpol

ator

coun

ters

with

outt

he33

8-bi

trea

dout

regi

ster

bank

.(2

)Est

imat

edar

eaof

inte

rpol

ator

coun

ters

.(3

)Nli

n=

Bit

s−lo

g 2(I

NL/

LSB+

1)[6

5]

95

Table 6. Comparison with discrete and FPGA based long range TDCs.

Reference Type CLK[MHz] Range[µs] LSB[ps] INL[ps](1) σssp[ps]

Paper I TAC+ADC 200 84e3(5) 0.1 ±2.5 1.8/1(2)

[8] TAC+ADC 100 2.55 10.5 N/A 14[91] TAC+ADC 100 ±21.47e6 3 ±19 47/12(2)

[44] Delay lines(FPGA)

120 N/A 30 ±110 15(2)

[45] Delay lines(FPGA)

100 N/A 51.1 ±77 40/20(2)

[46] Equivalentcoding lines

(FPGA)

500 10e6 2.87(3) ±17 5.5(2)

[47] Averageddelay lines

(FPGA)

160 N/A 3.93(3,4) ±34(4) 6(2,4)

[90] Wave unionaverag-

ing(FPGA)

100 N/A 12(3) ±100 9(2)

(1) Interpolator INL(2) INL compensated single-shot precision.(3) Equivalent bin width.(4) With 8 averaged delay lines.(5) 328µs in the paper. Afterwards extended to 84ms.

96

6 Summary

The time-to-digital converter architectures presented in this work are aimed for applica-tions requiring a long measurement range of tens of microseconds and a high precisionin the range of a few picoseconds. Typically, integrated TDCs employ either delaylines or ring oscillators as core building blocks, which are used to construct differenttypes of converter architectures such as flash, vernier, pipeline/cyclic, etc. Althoughvery high resolution stand-alone TDCs can be built solely based on free running ringoscillators/delay lines, the thermal noise induced phase noise/jitter and area constraintsusually make them only suitable for short-range time interval measurement in the rangeof a few tens of nanoseconds at most.

This work uses the Nutt interpolation method to solve this problem by combininga global reference clock counter with two short-range TDCs, which are used asinterpolators whose measurement range only has to cover a full reference clockperiod. In the Nutt method, the global reference clock is usually a very stable externalXO/TCXO/OCXO, which determines the long range stability and jitter of the TDC. Onthe other hand, the resolution and short term precision of a Nutt TDC is determined bythe interpolators’ resolution.

The characteristics of a Nutt interpolation method TDC differs significantly fromtraditional data converters. For example, when asynchronous measurements areconsidered, a TDC based on the Nutt interpolation method is inherently linear. Theasynchronous time measurement principle effectively converts all the static errors of theinterpolator, including quantization and nonlinearity errors, into dynamic noise-likeerrors. Since the Nutt interpolation TDC is free of static quantization and nonlinearityerrors, the effective resolution and precision can be improved in the digital domain byfiltering/averaging.

The measurement uncertainty induced by the reference clock has been relatively littlestudied before. Phase and frequency instabilities and their conversion to time domainmetrics, such as Allan-variance, have been studied before by the frequency and timemetrology community [73], however many of those results cannot be directly applied toTDCs based on the Nutt interpolation method. This work presents a thorough analysis ofthe impact of a reference oscillator’s frequency instability on the measurement precision.These instabilities consist not only of frequency drifting, but also deterministic and

97

random phase modulation processes. Conversion of power-law noise processes into timeinterval jitter is presented and confirmed by measurements utilising one of the designedhigh precision TDCs. One of the difficulties associated with the jitter estimation isthat the higher order phase noise processes are not strictly stationary. Because of this,when estimating the jitter due the higher order noise processes the observation time alsoneeds to be taken into account. Furthermore, any nonlinear clock buffer will affect themeasured noise floor of the clock, which, however, does not necessarily mean that thezero crossing jitter is also affected. This is demonstrated by analyzing a simple hardlimiter and confirmed by measurements conducted with one of the designed TDCs. It isalso demonstrated that a hard limiter can actually be used to simplify the process ofestimating the jitter due to a white phase noise floor.

The two time-to-digital converter architectures presented in this work have ameasurement range of several hundred microseconds and a measurement precision inthe range of a few picoseconds, thus making them very suitable for pulsed laser rangingapplications.

The interpolators in the discrete TDC are based on the traditional time-to-voltageconversion followed by an ADC. The TACs utilize Miller connected load capacitors,improving the INL of the interpolators below ±2.5ps. This designed TDC was also usedto verify the analysis of converting various phase noise processes to time interval jitter.

Initially, the time-to-voltage time stretching technique was considered to be used asa building block to design an integrated CMOS TDC with cyclic interpolators. However,as the design work progressed, the linearity limitations of the time-to-voltage conversionbecame evident as the resolution of a few picoseconds would have required around 10bits of linear range which seemed unfeasible to achieve with an integrated CMOS TVCas discussed in paper III. Because of this, other solutions were studied, which resulted inthe TDC with switched-frequency ring oscillators. To the authors knowledge, this TDCis the first of its kind to use frequency modulation to achieve time residue amplification.

The integrated CMOS TDC, designed in 0.35µm technology, uses a cyclic conversionmethod, where time residue amplification is realised by utilising a switched-frequencyring oscillator. The TDC is absent of any traditional analog circuit blocks, which makesit very simple to realise in any modern CMOS process. Only the switched-frequency ringoscillator requires manual design, while the rest of the circuit can be simply synthesizedusing a hardware description language. The RMS single-shot precision of the cyclicTDC is about 4.2ps, which represents state-of-the-art performance when compared toother long-range integrated TDCs based on the Nutt interpolation method. Although

98

designed in 0.35µm technology, the TDC’s resolution and precision is also comparableto state-of-the-art short-range TDC designs using much more modern technology. Aforeground calibration algorithm ensures that the accuracy of the TDC varies only±2.5ps in the temperature range of −30◦C to 70◦C. The area and power consumptionof the TDC could be improved significantly as the current version is very conservativelydesigned and mainly aimed to be a proof-of-concept for the new time amplificationmechanism. Furthermore, since the TDC mostly consists of standard digital logic gates,the area and power consumption could be improved significantly if the design would betransferred to a more modern CMOS technology.

99

100

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Original publications

I Keränen P, Määttä K & Kostamovaara J (2011) Wide-range time-to-digital converter with1-ps single-shot precision. IEEE Transactions on Instrumentation and Measurement 60(9):3162–3172.

II Keränen P & Kostamovaara J (2013) Oscillator instability effects in time interval measure-ment. IEEE Transactions on Circuits and Systems I: Regular Papers 60(7): 1776–1786.

III Keränen P & Kostamovaara J (2013) Noise and nonlinearity limitations of time-to-voltagebased time-to-digital converters. Proc IEEE Nordic-Mediterranean Workshop on Time-to-Digital Converters (NoMe TDC). Perugia, Italy: 1–6.

IV Keränen P & Kostamovaara J (2013) Algorithmic time-to-digital converter. Proc IEEENORCHIP Conference (NORCHIP). Vilnius, Lithuania: 1–4.

V Keränen P & Kostamovaara J (2015) A wide range, 4.2ps(rms) precision CMOS TDC withcyclic interpolators based on switched-frequency ring oscillators. IEEE Transactions onCircuits and Systems I: Regular Papers 62(12): 2795-2805.

Reprinted with kind permission from IEEE (I, II, III, IV, V).

Original publications are not included in the electronic version of the dissertation.

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