Ota000004 Sdh Principle Issue 2.2

SDH PrincipleUpon completion of this course, you will be able to:
Understand the basic of SDH multiplexing standard
Know the features, applications and advantages of SDH based equipment
HUAWEI TECHNOLOGIES CO., LTD.
Chapter3 Overhead & Pointers
---- It defines frame structure, multiplexing method, digital rates hierarchy and interface code pattern.
Why did SDH emerge?
---- Need for a system to process increasing amounts of information.
---- New standard that allows mixing equipment from different suppliers.
Electrical interfaces
--- Only regional standards. 3 PDH rate hierarchies for PDH: European (2.048 Mb/s), Japanese, North American (1.544 Mb/s).
Optical interfaces
--- No standards for optical line equipments, manufacturers develop at their will.
SDH
Optical interfaces
Can not be connected to multiple vendors’ optical transmission equipments.
PDH : Asynchronous Multiplexing
The location of low-rate signals in high-rate signals is neither regular nor predictable.
140 Mb/s
34 Mb/s
34 Mb/s
8 Mb/s
8 Mb/s
2 Mb/s
140 Mb/s
byte interleaved multiplexing method
( STM-1→STM-4→STM-16→STM-64 )
--- Synchronous multiplexing method and flexible mapping structure
--- Use multistage pointer to align PDH loads in SDH frame, thus, dynamic drop-and-insert capabilities
What about PDH?
PDH
SDH
Low bandwidth utilization ratio.
STM-64
STM-16
STM-4
STM-1
Glossary
Mapping - A process used when tributaries are adapted into VCs by adding POH information
Aligning - This process takes place when a pointer is included in a Tributary Unit (TU) or an Administrative Unit (AU), to allow the 1st byte of the VC to be located
Multiplexing - This process is used when multiple low-order path signals are adapted into a higher-order path signal, or when high-order path signals are adapted into a Multiplexing Section
Back
Rectangular block structure 9 rows and 270 columns(STM-1)
Each unit is one byte (8 bits)
Transmission mode: Byte by byte, row by row, from left to right, from top to bottom
Frame = 125 us
1 2 3 4 5 6 7 8 9
270 Columns
9 rows
270 Columns
9 rows
√ Used to transport low speed tributary signals
√ Contains low rate signals and Path Overhead (POH)
√ Location: rows #1 ~ #9, columns #10 ~ #270
9
MSOH
AU-PTR
Payload
RSOH
9
Location:
MSOH
AU-PTR
Location:
J1
AU-PTR
150.91Mbps
AU-PTR
AU-4
10
270
A1 = f6H (11110110), A2 = 28H (00101000)
In STM-N: (3XN) A1 bytes, (3XN) A2 bytes
STM-N
STM-N
STM-N
STM-N
STM-N
STM-N
RS-DCC – D1 ~ D3 – 192 kbit/s ( 3X64 kbit/s )
MS-DCC – D4 ~ D12 – 576 kbit/s ( 9X64kbit/s )
TMN
Digital telephone channel
A parity code (even parity), used to check the
transmission errors over the RS
B1 BBE is represented by RS-BBE( performance event)
Tx
Bit interleaved Parity Code (MS BIP-24) Byte
BIP-24 is used to check the bit errors over the MS
B2 BBE is represented by MS-BBE( performance event)
The mechanism of B2 is same as B1
Multiplexing Section Remote Error Indication Byte
A return message from Rx to Tx ,when Rx find B2 bit errors
A count of BIP-24xN (B2) bit errors
Tx generate corresponding performance event MS-FEBBE
Traffic
Tx
Rx
Generate
MS-FEBBE
MS-REI
Transmitting APS protocol
Generate
MS-AIS
Start
Detect
(b5~ b8)
bit 5 ~ 8
0010
1111
1 2 3 4 5 6 7 8 9 10
J1
B3
C2
G1
F2
H4
F3
K3
N1
> User-programmable
Next process
Detect J1
Mechanism is same as B1and B2
Next process
Verify B3
> 00 H Unequipped
Detect C2
> Indicated by TU-PTR
Functions: Error checking, Signal Label and Path Status of VC-12
b1- b2 Error Performance Monitoring (BIP-2)
b3 Return Error detected in VC-12 (LP-REI)
b4 Return Failure declared in VC-12 (LP-RFI)
b5 ~ b7 Signal Label for VC-12
b8 Indicate Defect in VC-12 path (LP-RDI)
Overhead & Pointers
696¡ª¡ª 697¡ª¡ª------782¡ª¡ª
0¡ª ¡ª 1¡ª ¡ª ------ 86¡ª¡ª
1
9
270
1
4
9
1
4
9
125us
250us
------ 521¡ª¡ª
Negative
justification
Positive
justification

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Ota000004 Sdh Principle Issue 2.2