Figure 4.8. Interrupt priority schemes.

(b) Arrangement of priority groups

Device Device

circuitPriority arbitration

Proc

esso

r

Device Device

(a) Daisy chain

Proc

esso

r

Device 2

INTR

INTA

INTR1

INTR p

INTA1

INTA p

Device nDevice 1

OSINIT Set interruptvectors:Time-sliceclock SCHEDULERSoftwareinterrupt OSSERVICESKeyboard interrupts IOData

...OSSERVICES Examinestack todeterminerequestedoperation.

Callappropriateroutine.SCHEDULER Saveprogramstate.

Selectarunnableprocess.Restoresaved context ofnewprocess.Push new values for PSand PConstack.Returnfrom interrupt.

(a) OS initialization, services, and scheduler

IOINIT Setprocessstatusto Blocked.Initializememorybufferaddresspointerandcounter.Calldevicedriver toinitializedeviceandenableinterruptsinthedevice interface.

Returnfromsubroutine.IODATA Polldevicestodeterminesourceof interrupt.

Callappropriatedriver.If END=1, thensetprocessstatus toRunnable.

Returnfrom interrupt.

(b) I/O routines

KBDINIT Enableinterrupts.Returnfromsubroutine.

KBDDATA Checkdevicestatus.Ifready,thentransfercharacter.If character = CR,then {set END = 1;Disableinterrupts }else set END= 0.

Returnfromsubroutine.

(c) Keyboard driver

Figure 4.10. A few operating system routines.

Figure 4.12. Accessible registers in different modes of the ARM processor.

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R13

R14

R15

User FIQ Supervisor Abort UndefinedIRQ

R15 R15 R15 R15 R15

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R0

R1

R2

R3

R4

R5

R6

R7

R8

R9

R10

R11

R12

R0

R1

R2

R3

R4

R5

R6

R7

General-purpose registers and program counter

Processor status register

CPSR CPSR CPSR CPSR CPSR CPSR

SPSR_fiq SPSR_irq SPSR_svc SPSR_abt SPSR_und

R8_fiq

R9_fiq

R10_fiq

R11_fiq

R12_fiq

R13_fiq

R14_fiq

R13-svc

R14_svc

R13_abt

R14_abt

R13_und

R14_und

R13_irq

R14_irq

Mainprogram

MOV R0,#0STR R0,EOL Clear EOL flag.ADR R1,DATAIN LoadaddressofRegisterDATAIN.LDRB R0,[R1,#3] Getcontents of CONTROLregister.ORR R0,R0,#4 Setbit KEN inregisterCONTROLSTRB R0,[R1,#3] toenable keyboardinterrupts.MOV R0,#&50 Enable IRQ interrupts in processorMSR CPSR,R0 andswitch to user mode....

IRQ Interrupt-serviceroutine

READ STMFD R13!,{R0 R2,R14irq} Save R0,R1,andR14 irq on thestack.ADR R1,DATAIN Loadaddressof register DATAIN.LDRB R0,[R1] Get inputcharacter.LDR R2,PNTR Loadpointer value.STRB R0,[R2],#1 Storecharacterandincrementpointer.STR R2,PNTR Update pointer value in thememory.CMPB R0,#&0D Check ifCarriageReturn.LDMNEFD R13!,{R0 R2,R14irq} If not,restoreregistersSUBNES PC,R14irq,#4 andreturn.LDRB R0,[R1,#3] Otherwiseget CONTROLregister.AND R0,R0,#&FB Clear bit KENSTRB R0,[R1,#3] todisablekeyboard interrupts.MOV R0,#1 Set EOLflag.STR R0,EOLLDMFD R13!,{R0-R2,R14} RestoreregistersSUBS PC,R14irq,#4 andreturn.

Figure 4.13. An ARM interrupt-service routine to read an input line from a keyboard based on Figure 4.9.

DATAIN

Keyboarddata

ValidStatusflag

Read-

1Slave-

Read-

SIN

ready

A31

A1

A0

Addressdecoder

Q7 D7

Q0 D0

D7

D0

R/ W

Figure 4.29. Input interface circuit.

datastatus

ready

Master-

DATAIN

1

SIN

Ready

A31

A1

A0

Addressdecoder

D7

D0

R/ W

Figure 4.33. Combined input/output interface circuit.

A2

DATAOUT

Inputstatus

BusPA7

PA0

CA

PB7

PB0

CB1

CB2

SOUT

D1

RS1

RS0

My-address

Handshak econtrol

Master-

ReadySla ve-

DATAIN

DATAOUT

DataDirectionRegister

Register

select

Statusand

control

AcceptReady

R/WRS0RS1RS2

My-address

INTR

C1

C2

P7

P0

D7

D0

Figure 4.34. A general 8-bit parallel interface.

Handshak econtrol

DATAOUT

Printerdata

Idle

Valid

Read Load

SOUT

ready

A31

A1

A0

Addressdecoder

D7 Q7

D0 Q0

D7

D0

Figure 4.35. A parallel point interface for the bus of Figure 4.25,with a state-diagram for the timing logic.

status data

D1 Q1D0

TimingLogic

Clock

My-address

R/W

Sla ve-

Idle Respond

My-address

Go

Go=1

INTR

Chip andregisterselect

Statusand

control

Accept

Ready

R/W

RS0

RS1

My-address

Receiving clock

Transmission clock

Figure 4.37. A serial interface.

D7

D0

Output shift register

DATAOUT

DATAIN

Input shift register

Serialoutput

Serialinput

memoryProcessor

Bridge

Processor bus

PCI bus

Main

memoryAdditional

controllerCD-ROM

controllerDisk

Disk 1 Disk 2 ROMCD-

SCSIcontroller

USBcontroller

Video

K eyboard Game

diskIDE

SCSI bus

Figure 4.38. An example of a computer system using different interface standards.

ISAinterf ace

Ethernetinterf ace

Host computer

Roothub

Hub

Figure 4.43. Universal Serial Bus tree structure.

I/Odevice

Hub I/Odevice

I/Odevice

Hub

I/Odevice

I/Odevice

I/Odevice

Host computer

RootHub

Hub A

Device

Figure 4.44. Split bus operation

D

F/LS

HS HS

HS

HS - High speed

F/LS - Full/Low speed

Hub B

DeviceC

PID0 PID1 PID2 PID3 PID0PID0 PID1 PID2 PID3

(a) Packet identifier field

PID ADDR ENDP CRC16

8 7 4 5Bits

(b) Token packet, IN or OUT

PID DATA CRC16

8 0 to 8192 16Bits

(c) Data packet

Figure 4.45. USB packet format.

ACK

Token

Data0

Token

Data1

Figure 4.46. An output transfer.

Host Hub I/O Device

Token

Data0

ACK

ACK

Token

Data1

ACK

Time

PID Frame number CRC5

8 11 5Bits

(a) SOF Packet

Figure 4.47. USB frames.

S T3 D S

1-ms frame

T7 D T3 D

S - Start-of-frame packet

T n- Token packet, address = n

D - Data packet

A - ACK packet

(b) Frame example

Table 4.4 The SCSI bus signals.

Category Name FunctionData DB(0) to

DB(7)Datalines:Carryonebyteofinformationduringtheinformationtransferphaseandidentify deviceduringarbitration,selectionandreselectionphases

DB(P) Parity bit for thedatabusPhase BSY Busy:Assertedwhenthebus isnotfree

SEL Selection:Assertedduringselectionandreselection

Informationtype

C/D Control/Data:Assertedduringtransferofcontrol information(command,statusormessage)

MSG Message:indicatesthattheinformationbeingtransferredis amessage

Handshake REQ Request:Assertedby atargettorequestadatatransfercycle

A CK Acknowledge:Assertedbytheinitiatorwhenithascompleteda datatransferoperation

Directionoftransfer

I/O Input/Output:Assertedtoindicateaninputoperation(relative to theinitiator)

Other A TN Attention:Assertedby aninitiatorwhenitwishestosendamessageto atarget

RST Reset:Causesalldevicecontrols todisconnectfromthebus andassumetheirstart-upstate

–

–

–

–

–

–

–

–

–

–

–

–