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Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 1

Chapter 9: Memory Management

Background

Address Binding - Linking and Loading

Swapping

Contiguous Allocation

Paging

Segmentation

Segmentation with Paging

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Background

CPU scheduling (chapter 6) improves CPUutilization and the speed of the computersresponse to its users.

To realize this goal memory must be shared bymultiple processes

How to manage that sharing is the topic of thischapter

CPU goes through an instruction-execution cycle

Instruction fetched from memory and decodedresulting in possible retrieval of operands frommemory

Instruction executed and results may be storedback in memory

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Multistep Processing of a User Program

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Address Binding

Input queue collection of processes on thedisk that are waiting to be brought into memoryto run the program.

One of these processes is selected to be loadedinto memory, run and, when terminated,removed from memory

A process can reside in any part of the physical

memory. The first address of the user processdoes not have to be the first address of thecomputer

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Binding of Instructions and Data to Memory

Compile time If memory location known atcompile time then absolute code can be generated;must recompile code if starting location changes.

Load time Must generate relocatable code ifmemory location is not known at compile time butis finalized at load time.

Execution time Binding delayed until run time ifthe process can be moved during its execution fromone memory segment to another. Need hardwaresupport for address maps (e.g., base and limitregisters).

Address binding of instructions and data to memory addresses

can occur at three different stages.

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Linking and Loading

Typical scenario the application consists of a number of compiled orassembled modules in object form

They are linked to resolve any references between modules

References to library routines are resolved

Loader places the load module in main memory starting at location x

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7/59Silberschatz / OS Concepts / 6e - Chapter 9 Memory Management Slide 7

Linking and Loading

When an active process is loaded into main memory a processimage is created

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The Linking Function

The linker takes a collection ofobject modules and producesa load module consisting of anintegrated set if programs anddata modules

In each object module theremay be address references to

locations in other modulesThe linker creates a singleload module that is thecontiguous joining of all of theobject modules Symbolic address references

must be changed to alocation within the overallload module

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Absolute and Relocatable Load Modules

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Logical vs. Physical Address Space

The concept of a logical address space that isbound to a separatephysicaladdress space iscentral to proper memory management. Logical address generated by the CPU; also

referred to as virtual address.

Physical address address seen by the memoryunit, loaded into the MAR

Logical and physical addresses are the same incompile-time and load-time address-binding

schemesLogical (virtual) and physical addresses differ inexecution-time address-binding scheme.

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Memory-Management Unit (MMU)

Hardware device that performs run-time mappingbetween virtual and physical address.

In MMU scheme, the value in the relocationregister is added to every address generated by auser process at the time it is sent to memory.

The user program deals with logicaladdresses; itnever sees the realphysical addresses.

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Dynamic Loading

Routine is not loaded until it is calledBetter memory-space utilization; unused routineis never loaded.

Useful when large amounts of code are needed to

handle infrequently occurring cases.All routines are kept on disk in a relocatable loadformat

No special support from the operating system isrequired, implemented through program design.

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Dynamically Linked Libraries

Static linking system language libraries are combined bythe loader into the binary program image

Dynamic linking - linking postponed until execution timeso that routines referenced by the program are not includedin the executable image

Small piece of code,stub, used to locate the appropriatememory-resident library routine.

Stub replaces itself with the address of the routine, andexecutes the routine.

All processes that use a language library execute only one

copy of the library codeUnlike dynamic loading, dynamic linking requires theassistance of the OS to check if routine is in anotherprocess memory space or allow multiple processes to sharethe same memory address

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Overlays for a Two-Pass Assembler

Enables a process to be larger than the amount of memory

allocated to it Keep in memory only those instructions and data that are needed at

any given time.

When other instructions are needed, they are loaded into spaceoccupied previously by instructions no longer needed.

Implemented by user; programming design of overlay structure iscomplex No special support needed from operating system

Example, two-pass assembler

1st

pass: constructs symbol table 2nd pass: generates machine language code

Partition into pass1 code (70KB), pass 2 code(80KB), symbol table(20KB) and common support routines(30KB) used in both passes limited to 150KB (total of all components is 200KB)

Overlay driver handles the switching (requires its own memory)

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SwappingA process can be swappedtemporarily out of memory to a

backing store, and then brought back into memory forcontinued execution.

Backing store fast disk, large enough to accommodatecopies of all memory images for all users; must providedirect access to these memory images.

Roll out, roll in swapping variant used for priority-basedscheduling algorithms; lower-priority process is swapped outso higher-priority process can be loaded and executed.

Major part of swap time is transfer time; total transfer timeis directly proportional to the amountof memory swapped.

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SwappingContext-switch time in a swapping system is fairly high

Process 1MB, backing store transfer rate of 5MB/sec yieldsapproximately 200 msec for one way swap (add on avg latencytime of 8 msec).

For efficient utilization, the execution time of a process shouldbe long relative to the swap time

Standard swapping is used in few systems as it requires toomuch swapping time and provides too little execution time

Modified versions of swapping are found on many systems, i.e.,UNIX, Linux, and Windows.

UNIX:Swapping normally disabled unless many processes were

running and memory usage was reaching a threshold level MS Windows 3.1: user, not dispatcher, preempts process and

decides what is swapped in and out

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Schematic View of Swapping

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Memory ProtectionMain memory usually into two partitions:

Resident operating system, usually held in low memory withinterrupt vector.

User processes then held in high memory.

Enables OS to change size dynamically code for drivers istransient and only brought into memory when required.

Each process is contained in a single contiguous section ofmemory Relocation-register scheme used to protect user processes

from each other, and from changing operating-system codeand data.

Relocation registercontains value of smallest physical address Limit registercontains range of logical addresses each

logical address must be less than the limit register.

As part of the context-switch, the dispatcher loads therelocation and limit registers with the correct values for that

process

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Hardware Support for Relocation and Limit Registers

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Memory AllocationMultiple-partition allocation

Hole block of available memory; holes ofvarious size are scattered throughout memory.

When a process arrives, it is allocated memoryfrom a hole large enough to accommodate it.

Operating system maintains information about:a) allocated partitions b) free partitions (hole)

OS

process 5

process 8

process 2

OS

process 5

process 2

OS

process 5

process 2

OS

process 5

process 9

process 2

process 9

process 10

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Dynamic Storage-Allocation Problem

First-fit: Allocate the firsthole that is big enough

Next-fit: look for first-fit from last allocation

Best-fit: Allocate the smallesthole that is big

enough; must search entire list, unless ordered bysize. Produces the smallest leftover hole.

Worst-fit: Allocate the largesthole; must alsosearch entire list. Produces the largest leftover hole.

First-fit and worst-fit are better than worst-fit interms of decreasing both time and storage utilization

Neither first-fit or best-fit is clearly better for storageutilization but first-fit is generally faster

How to satisfy a request of size n from a list of free holes.

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Dynamic Storage-Allocation Problem

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Fragmentation

External Fragmentation free memory space isbroken non-contiguous pieces, none big enough tosatisfy a request

Internal Fragmentation allocated memory may beslightly larger than requested memory; this size

difference is memory internal to a partition, but notbeing used.

Reduce external fragmentation by compaction

Shuffle memory contents to place all free memorytogether in one large block., this can be expensive

Compaction is possible onlyif relocation is dynamic,and is done at execution time.

Or, use Paging

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PagingLogical address space of a process can be noncontiguous;

process is allocated physical memory whenever the latter isavailable.

Dividephysicalmemory into fixed-sized blocks calledframes (size is power of 2, between 512 bytes and 8192bytes).

Divide logicalmemory into blocks of same size calledpages.

Keep track of all free frames.

To run a program of size n pages, need to find n free frames

and load program.Set up a page table to translate logical to physicaladdresses.

Contains the base address of each page in physical memory

Internal fragmentation.

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Address Translation Scheme

Address generated by CPU is divided into: Page number(p) used as an index into apage

table which contains base address of each page inphysical memory.

Page offset(d) combined with base address todefine the physical memory address that is sent tothe memory unit.

If the size of the logical address space is 2m and

page size is 2n

then the high order m-n bits of thelogical address designate the page number and then low order bits designate the page offset

page number (p) page offset(d)

m-n n

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Address Translation Architecture

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Paging Model

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Paging ExamplePage size = 4 bytes

Physical memory = 32 bytes (8 pages)

Page 0 is in frame 5 which is physicaladdress 20

Logical address 3 (page 0 offset 3) is

mapped to frame 5 offset 3 which isphysical address 23

Paging is similar to using a table of baseregisters, one for each frame of memory

To reduce internal fragmentation, someOSs support multiple page sizesSolaris 8KB and 4MB

Research on variable, on-the-fly pages

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Paging

OS keeps track of which frames are allocated and which areavailable in the frame table

Frame table has one entry for each physical page frame,indicating if its is free or allocated. If allocated, it also tracks

which page of which process

A copy of the page table for each process is maintained bythe OS.

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Free Frames

Before allocation After allocation

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Implementation of Page Table

Page table can be implemented as a set of dedicatedregisters with very high speed logic. Reloaded by the CPUdispatcher. Good for reasonably small page tables (256entries)Large page tables (1 million entries) are kept in mainmemory. Page-tablebase register (PTBR) points to the page table. Page-table length register(PTLR) indicates size of the page

table so as to minimize the amount of memory needed ratherthan allocate space for the full table

In this scheme every data/instruction access requires twomemory accesses. One for the page table and one for thedata/instruction.The two memory access problem can be solved by the useof a special fast-lookup hardware cache called associativememoryor translation look-aside buffers(TLBs)

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Associative MemoryAssociative memory parallel search (key and tag)

Address translation (A, A)

If A is in associative register, get frame # out. Otherwise get frame # from page table in memory

Hardware is expensive, typical number of entries is between 64and 1,024

If TLB miss, add page/frame pair to the TLB

Some entries are wired down (can not be removed e.g., kernelcode entries)

Some TLBs store address-space identifiers (ASIDs) which allowsmultiple processes to be in the TLB at the same time. If not, TLBmust be flushed when another page table is selected

Page # Frame #

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Paging Hardware With TLB

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Effective Access Time

Associative Lookup =

time unitAssume memory cycle time is x microsecond

Hit ratio percentage of times that a page number isfound in the associative registers; ratio related to numberof associative registers.

Hit ratio =

Effective Access Time (EAT)

EAT = (x + ) + (2x + )(1 )

= 2x x +

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Effective Access Time

80% hit ratio20 nanosec to search TLB, 100 nanosec to access memory

TLB hit 20ns+100ns = 120ns

TLB miss20ns + 100ns(page table lookup) +100ns(physical memory lookup) = 220ns

Effective access time = .8*120 + .2*220 = 140 ns (40%slowdown in access time)

98% hit ratio .98*120 + .02*220 = 122ns (22%slowdown in access time)

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Memory Protection

Memory protection in a paged environment isimplemented by associating a protection bit witheach frame. Specifies execute-only, read-only, read-write or

any combination

Valid-invalidbit attached to each entry in thepage table: validindicates that the associated page is in the

process logical address space, and is thus a legal

page. invalidindicates that the page is not in the

process logical address space.

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Valid (v) or Invalid (i) Bit In A Page Table

Page size 2KB, 14 bit address space addresses 0 to 16,383

Program addresses 0 to 10,468 which is in frame 5, frames 6 and 7 areinvalid

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Page Table Structure

Hierarchical Paging

Hashed Page Tables

Inverted Page Tables

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Hierarchical Page Tables

Most computers support a large logical addressspace (232 to 264) page table becomesexcessively large

32-bit logical address space with page size of 4KB

(212) results in a page table of 1 million entries(232/212=1,048,575).

If each entry is 4 bytes, then each process may needup to 4MB of physical address space just for the

page tableBreak up the logical address space into multiplepage tables.

A simple technique is a two-level page table.

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Two-Level Paging Example

A logical address (on 32-bit machine with 4K page size) is

divided into: a page number consisting of 20 bits.

a page offset consisting of 12 bits.

Since the page table is paged, the page number is furtherdivided into: a 10-bit page number.

a 10-bit page offset.

Thus, a logical address is as follows:

where p1 is an index into the outer page table, andp2 is thedisplacement within the page of the outer page table.

page number page offset

p1 p2 d

10 10 12

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Two-Level, Forward-Mapped Page-Table Scheme

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Address-Translation SchemeAddress-translation scheme for a two-level 32-bit

paging architecture (forward mapped page table)32 bit Motorola 68030 architecture supports a four-levelpaging scheme

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Hashed Page Tables

Common in address spaces > 32 bits.

The virtual page number is hashed into a pagetable. This page table contains a chain ofelements hashing to the same location.

Each element consists ofa) virtual page number

b) value of the mapped page frame

c) pointer to the next element in the linked list

Virtual page numbers are compared in thischain searching for a match. If a match isfound, the corresponding physical frame isextracted.

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Hashed Page Table

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Inverted Page TableUsually, each process has an associated page table. Each

page table may consist of millions of entries consuminglarge amounts of physical memory.

Inverted page table uses one entry for each real frame ofmemory.

Entry consists of the virtual address of the page stored in

that real memory location, with information about theprocess that owns that page (ASID)

Only one page table in the system, but increases timeneeded to search the table when a page reference occurs.(64bit UltraSPARC)

Since may need to search the whole table for a match, usehash table to limit the search to one, or at most a few,page-table entries.

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Inverted Page Table Architecture

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Shared PagesShared code One copy of read-only (reentrant) code shared among

processes (i.e., text editors, compilers, window systems).

Shared code must appear in same location in the logicaladdress space of all processes.

Important in time-sharing environments if 40 users

execute a text editor that is 150KB of code and 50KB ofdata we would need 8,000KB of memory. By sharing there-entrant code we reduce 6,000KB to 150KB

Private code and data

Each process keeps a separate copy of the code and data. The pages for the private code and data can appear

anywhere in the logical address space.

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Shared Pages Example

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Segmentation

Memory-management scheme that supports user view ofmemory.A program is a collection of segments. A segment is alogical unit such as:

main program,

procedure,function,

method,

object,

local variables, global variables,

common block,

stack,

symbol table, arrays

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Users View of a Program

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Logical View of Segmentation

1

3

2

4

1

4

2

3

user space physical memory space

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Segmentation Architecture

Logical address consists of a two tuple:

,Segment table maps two-dimensional physicaladdresses; each table entry has:

base contains the starting physical address where

the segments reside in memory. limit specifies the length of the segment.

Segment-table base register (STBR) points to thesegment tables location in memory.

Segment-table length register (STLR) indicates number ofsegments used by a program; segment number s is legalifs < STLR.

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Segmentation Architecture (Cont.)

Protection. With each entry in segment tableassociate:

validation bit = 0 illegal segment

read/write/execute privileges

Protection bits associated with segments; codesharing occurs at segment level.

Since segments vary in length, memory allocationis a dynamic storage-allocation problem.

External fragmentation

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Example of Segmentation253 or 2,53 refers to

segment 2 byte 53which is mapped to4353

0,1222 results in atrap to the OS as thesegment is only

1,000 bytes long

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Sharing of Segments

C bi d P i & S t ti

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Combined Paging & Segmentation Paging and segmentation have their strengths

Paging transparent to the user, eliminates external fragmentation

The pieces moved in and out of main memory are of fixed, equal size which enables thedevelopment of sophisticated algorithms that exploit this feature

Segmentation visible to the programmer, can grow dynamically, enables sharing andprotection by segment

To combine the two, a users address space is broken up into a number of

segments at the discretion of the programmer

Each segment is broken up into a number of fixed size pages, equal in length toa page frame

Each segment has an associated page table

When a process is running, a register holds the starting address of the segmenttable

The segment number potion of the VA indexes into the process segment table tofind the page table for that segment

Then the page number portion of the VA is used to index the page table and look

up the page frame number

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Combined Paging & Segmentation

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Combined Paging & Segmentation

Virtual Address

Segment # Page # Offset

Segment table entryControl bits Length Segment base

Page table entryPresentbit

Modified bit Other control bits Frame #

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