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March the 13 th , 2001. Orsay’s proposition for the L2 trigger system. detailed description of the architecture distribution of the work costs schedule firmware. Bernard Lavigne, Philippe Cros, Pierre Petroff, Laurent Duflot. Trigger Crate. L2 trigger mosaic of boards. CPU board - PowerPoint PPT Presentation
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Orsay’s proposition for the L2 trigger system
• detailed description of the architecture• distribution of the work• costs• schedule• firmware
Bernard Lavigne, Philippe Cros, Pierre Petroff, Laurent Duflot
March the 13th, 2001
CPU boardProcessor : Pentium III 850 MHz
Dimensions : 6UMake : VMIC
Type : VMIVME-7740
CPU boardProcessor : Pentium III 850 MHz
Dimensions : 6UMake : VMIC
Type : VMIVME-7740
Trigger CrateTrigger Crate
Trigger adaptation boardFunction : interface between the trigger crate and the processor board
Trigger adaptation boardFunction : interface between the trigger crate and the processor board
PCI bus
33 MHz, 32 bits
VME bus
Magic bus
128 data bits
32 add bits
20 MHzECL signals
L2 trigger mosaic of boards
6U board6U board366 mm
160 mm
400 mm
233 mm
9U board
Dimensions
Hard drive
The proportions of the boards are respected
6U board9U board
mezzanineboard
Geometry of the boards
The proportions of the boards are respected
6U board9U board
Geometry of the boards (profile view)
Hard drive
9U board
PCI interface
6U components side mezzanine components side
9U components side(a few thin (height : 1.20 mm) TTL drivers
will be on the other side)
TT
L drivers
~12mm
Hard drive
6U board9U board
Add-on
Magicbus
PCI
VME
EIDE
mezzanineboard
driv
ers
: ele
ctri
cal
isol
atio
n
VME
elec
tric
al c
onve
rsio
n to
EC
L
Display
The proportions of the boards are respected
Electronics functions
FIF
Os
: DM
A s
tori
ng
PCI / Add-on interface
Add-on / Magic bus interface &PCI / Magic bus arbitration
FPGA
20 MHz
33 MHz
33 MHz
Hard drive
6U board9U board
Add-on
Magicbus
PCI
Controlsignals
VME
EIDE
mezzanineboard
Altera APEX 20K200Fineline BGA 484
AMCC S5935PQFP 160
TTLdriver
TTLdriver
TTLdrivers
FIFOs
VME
clk40MHz
EPROM
ECLdrivers
Display
The proportions of the boards are respected
Electronics placement
FPGA
• pin limited• wide logics capacity (8320 cells, 13 kB mem)• high rate• low voltage• BGA package• unique FPGA flexibility• inputs-outputs known beforehand
Magicbus
Control signals from J1 and J2 connectors
FIFOs output dataand control signals
ECL drivers dataand control signals
Display
FPGA details
195
32 +5
TTL drivers control signals5
Altera APEX 20K200Fineline BGA 484
20
Add-on bus
60
32+ 2
EPROM5
5
Clock1
Switches4
Total : 366 signals out of 376 available
when unclear, the given countis approximative by excess
23.2 mm
23.2 mm
height : 1.86 mm
the geomtry of the input/output pins is not respected
The proportions of the boards are respected
9U board from the factory
Add-on
Magicbus
EIDE
Altera APEX 20K200Fineline BGA 484
TTLdriver
TTLdriver
TTLdrivers
FIFOs
clk40MHz
EPROM
ECLdrivers
The proportions of the boards are respected
most components are assembled
Add-on
Magicbus
EIDE
Altera APEX 20K200Fineline BGA 484
TTLdriver
TTLdriver
TTLdrivers
FIFOs
clk40MHz
EPROM
ECLdrivers
The proportions of the boards are respected
the inside cut is sawed, the VME connectors are soldered
Add-on
Magicbus
EIDE
Altera APEX 20K200Fineline BGA 484
TTLdriver
TTLdriver
TTLdrivers
FIFOs
clk40MHz
EPROM
ECLdrivers
The proportions of the boards are respected
the front pannel and support bars are screwed
PCI
the mezzanine board is relatively simple
AMCC S5935PQFP 160
add-on
EPROM
If all signals don’t pass through 2 PMC connectors,the board is enlarged to receive a 3rd one
The proportions of the boards are respected
6U board9U board
mezzanineboard
Grounding of the boards
backplane
PCBs and hardware to design
• a 9U board• a mezzanine board• the 9U front panel• the aluminium support bars• no modification on the 6U board
Manpower at Orsay
• schematics, firmware :Bernard Lavigne, Philippe Cros (+ a technician if necessary)
• tests :Bernard Lavigne, Philippe Cros, Pierre Petroff, Laurent Duflot
• PCB design :board design group
• front panel, support bars, mechanics questions :mechanics group
• production, assembly : private companies
Costs (US $)
prototype (3) production (30)
PCB 1700 1100Components 900 500
Assembly 200400
Total 20003350
Whole budget : $ 70000The front panel and mechanics components are taken in account in the components budget
The costs don’t count the CPU board, neither the engineering cost which is around $20000
PCB 250 150Components 100 50
Assembly 00 assembled at Orsay
nota :
9U
mezzanine
Schedule for the prototype
march april may june july august september
schematics
PCB design production
tests
software
assembly
schematics
PCB design production
firmware
assembly
9U
l2 system
mezzanine
front panel / bars
Firmware
• composed of blocks : necessity of a documentation with input-outputs-functionality of each block
• distribution of the blocks :Maryland : Magic bus, PIO, TSI, DMAOrsay : Add-on, DMA ?
• common language : Verilog, AHDL, VHDL ?• most complex part of the project,
the development should start soon
FIFOs output dataand control signals
ECL drivers dataand control signals
Display
FPGA blocks
control signals from P1/P2 connectors
Altera APEX 20K200Fineline BGA 484
Add-on bus
EPROM
Clock
Switches
Add-on bus interface TSI
PIO
MB interface
local bus
DMA
ECLsignals
Magic bus
the geomtry of the input/output pins is not respected
Other
TTL drivers control signals
Conclusion :
The solution we propose :
• cheap
• realistic schedule
• manpower and experience
• technically reliable
• flexible
• developments equally shared
