Organic double-gate field-effect transistors: Logic-AND operationLay-Lay Chua, Richard H. Friend, and Peter K. H. Ho Citation: Applied Physics Letters 87, 253512 (2005); doi: 10.1063/1.2149351 View online: http://dx.doi.org/10.1063/1.2149351 View Table of Contents: http://scitation.aip.org/content/aip/journal/apl/87/25?ver=pdfcov Published by the AIP Publishing Articles you may be interested in Large tunneling magnetoresistance in a field-effect transistor with a nanoscale ferromagnetic gate Appl. Phys. Lett. 92, 253101 (2008); 10.1063/1.2951901 Bandstructure effects in ultra-thin-body double-gate field effect transistor: A fullband analysis J. Appl. Phys. 103, 114503 (2008); 10.1063/1.2937186 Device physics and guiding principles for the design of double-gate tunneling field effect transistor with silicon-germanium source heterojunction Appl. Phys. Lett. 91, 243505 (2007); 10.1063/1.2823606 Characterization of functionalized pentacene field-effect transistors and its logic gate application J. Appl. Phys. 100, 044511 (2006); 10.1063/1.2335378 Double-gate organic field-effect transistor Appl. Phys. Lett. 87, 153511 (2005); 10.1063/1.2103403

This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP:

69.166.47.134 On: Wed, 26 Nov 2014 08:18:31

Organic double-gate field-effect transistors: Logic-AND operationLay-Lay ChuaCavendish Laboratory, University of Cambridge, Madingley Road, Cambridge, CB3 0HE, United Kingdomand Department of Physics, National University of Singapore, Lower Kent Ridge Road, S117542,Singapore

Richard H. Frienda�

Cavendish Laboratory, University of Cambridge, Madingley Road, Cambridge CB3 0HE, United Kingdom

Peter K. H. Hob�

Department of Physics, National University of Singapore, Lower Kent Ridge Road, S117542, Singapore

�Received 5 October 2005; accepted 15 November 2005; published online 15 December 2005�

A unipolar double-gate field-effect transistor �DG-FET� with AND logic functionality isdemonstrated. This operation regime arises through a symmetric electrostatic coupling of twoconduction channels via the intrinsic semiconductor layer. According to simulation, this mode ofoperation is general and not limited to organic devices. These DG-FETs provide for two-signalmodulation in a single device of a shared active region, and are thus versatile building blocks forlogic, memories, sensing, data transmission and light-emitting FETs. When the two gates are tiedtogether somewhat reminiscent of Si FinFETs, these devices can achieve considerably deeper gatemodulation than possible with single gating. © 2005 American Institute of Physics.�DOI: 10.1063/1.2149351�

Double-gate field-effect transistors �DG-FETs�1 withlightly doped or intrinsic Si have been proposed to overcomeshort-channel effects and extend Si complementing metal-oxide-semiconductor technologies beyond the 50 nm gate-length node.2 However, practical fabrication challenges haveonly recently been surmounted through clever FinFETs,3 inwhich a single gate bias is applied to the surround gate. Werealized, however, that if the gates could be separated andoperated independently, the phenomenon of electrostatic gatecoupling should give rise to an interesting mode of transistoroperation for intrinsic semiconductor devices. In particular,the required architecture could be readily fabricated in or-ganic devices4 to give organic DG-FETs by additive layer-by-layer processing5 or ink-jet printing.6

While preparing our manuscript, Iba et al.7 and Gelinck,Van Veenendaal, and Coehoorn8 published their work on or-ganic DG-FETs. In both reports, the organic semiconductorwas pentacene, but the top conduction channel was almostcompletely degraded by surface roughness which is knownto impact strongly on carrier mobility beyond a criticalvalue.9 As a result, only threshold shifts by the distant gatewere observed.7,8 Here the devices are fabricated from poly-mers, which yield considerably smoother top surfaces, andboth conduction channels are active. Thus we could achieverobust modes of device operation as AND logic and obtainextremely deep current modulation. This is useful in appli-cations in which a control signal is required to gate the datasignal, such as sensor10,11 arrays, data12 transmission,memory cell13 readout, or to create output gray scale.

The schematic diagram of organic DG-FET is shown inthe inset of Fig. 1�a�. Carriers are injected from the sourceelectrode into each of the two separate conduction channelsthat are formed at these interfaces depending on the state ofthe gate voltages. We fabricated diagnostic DG-FETs with

matched top- and bottom-gate capacitances �1.7�10−8 F cm−2� using SiO2/Si as convenient bottomdielectric-gate system �organic dielectrics can alsobe used� and cross-linked divinyltetramethyldisiloxane-bis�benzocyclobutene� �BCB� / surfactant-ion-exchang-ed-poly�3,4-ethylenedioxythiophene�–poly�styrenesulfonate��PEDT:PSSR�14 as the robust top dielectric-gate system. A40-nm-thick film of poly�9,9-dioctylfluorene-co-�phenylene-�N-4-sec-butylphenyl�-iminophenylene��TFB� was depos-ited in between as the p-channel semiconductor, with stan-dard gold interdigitated source and drain array electrodes.15

To obtain an insight into the operation of these devices,the Poisson-continuity equations were solved for a unipolarfour-terminal device using reasonable values for the physicalparameters of the organic semiconductor with only the mo-bile charge term incorporated to represent carrier accumula-tion in an intrinsic semiconductor material.16 Without loss ofgenerality, we assumed constant charge-carrier mobility, de-spite the importance of its field dependence and carrier-density dependence.17 Solutions to the charge density andelectric field across the semiconductor body thus obtainedfor different Vg2 for a given Vg1=−60 V �ON� and channelpotential Vch=−30 V are shown in Figs. 1�a� and 1�b�, re-spectively. These demonstrate clearly that when both gatesare ON �e.g., Vg2=−60 V�, two parallel conduction channelsare formed in the device. The accumulation width is only afew angstroms wide with the bulk of the semiconductor bodyscreened by these two channels. As Vg2 leaves the ON stateand approaches the OFF state, its channel gets emptied ofcarriers and eventually shuts OFF. As Vg2 swings deeper intothe OFF state, the reverse gate field grows, penetrating thesemiconductor body to disperse carrier density accumulatedat the opposite interface, closing down that channel. Whenthe local neutrality point is reached, given by Vg2=−�Vg1

−Vch� for thin semiconducting body, that conduction channelgets shut OFF, too. At this point the electric field completelypenetrates the body of the semiconductor from the top to the

a�Electronic mail: rhf10@cam.ac.ukb�Electronic mail: phyhop@nus.edu.sg

APPLIED PHYSICS LETTERS 87, 253512 �2005�

0003-6951/2005/87�25�/253512/3/$22.50 © 2005 American Institute of Physics87, 253512-1 This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP:

69.166.47.134 On: Wed, 26 Nov 2014 08:18:31

bottom gate. This coupling is predicted to weaken with in-creasing d3 /d where d=d1+d2+d3.

Figure 1�c� shows the computed areal charge density dis-tribution ��� between the source and drain for different statesof Vg2 with Vg1=−60 V �ON�. When Vg2 is also ON, thecharge density is double that of a single-gate device becausethe two gates are independent. As the Vg2 is switched OFF, �approaches the single-gate limit and then drops to zero as Vg2reaches even deeper OFF. Therefore, in unipolar four-terminal devices with thin intrinsic semiconductor body, thesource-drain conductance can be strongly modulated by thefirst gate even while the second gate remains ON. Figure 1�d�provides a schematic illustration of these cases.

The experimental results are in general accord with thesepredictions. The Is−Vd output characteristics of the TFB DG-FET are shown in Fig. 2�a�. When both gates are biased intoconduction with Vg1=Vg2=−60 V, the drain current exceeds30 �A at Vd=−60 V. Well-defined saturation is observed forVd�Vg1. Leakage current was typically less than 10 nA. Thesaturation mobility evaluated here using channel width astwice the physical width is 5�10−4 cm2/V s, similar to thereference single-gate FET value of 7�10−4 cm2/V s. Theslight lowering is due to the 290 °C rapid thermal annealrequired to fabricate the DG-FET, and is found also insingle-gate devices subjected to such anneals �3±1�10−4 cm2/V s�.9 When either of the gates is biased away

from conduction, the overall source-drain current can be at-tenuated by several orders of magnitude. For Vg1� +10 V,the device is completely OFF with drain current below leak-age. The ON-OFF ratio of �104 here is limited only byleakage. It is clear that the channels in these devices do notbehave as independent conduction paths. The top and bottomchannel potentials are coupled and the electrical characteris-tic of one channel is markedly modulated by the bias appliedto the opposite gate as predicted. The Is−Vg1−Vg2 surface isnearly symmetrical with respect to interchange of Vg1 andVg2, as a result of the near matching of the respective gatecapacitance and proper operation of both the channels. Whenthe respective gate capacitances are not matched, the Is−Vg1−Vg2 surface becomes skewed and the gate with thelower dielectric capacitance exerts a stronger effect on theoverall channel conductance as expected.

The log-lin Is−Vd output characteristics taken for syn-chronous Vg1=Vg2 sweeps are shown in Fig. 2�b� and com-pared with data for conventional single-gate FETs with TFBas the semiconductor. Here the results show up a furtherunexpected advantage: the drain current can be more deeplymodulated by the gate voltage in double-gate than in thesingle-gate FETs. This is ascribed to screening of the longi-tudinal source-drain electric field at the drain end by theequipotential volume setup by the two identical gate volt-ages, which suppresses the carrier velocity through the“pinch-off” region in the saturation regime. This suggests anovel means to circumvent inadvertent channel doping andto achieve very high ON-OFF ratios useful for semiconduc-tors that are particularly susceptible to ambient doping, e.g.,polythiophenes.

Figure 3 shows AND logic operation using these DG-FETs whereby the logic states �1 or 0� are input directly toeach of the two gates. HIGH �−60 V� and LOW �+20 V�inputs are applied in sequence and the drain current moni-tored as output. When both inputs are HIGH, the device con-ductance is HIGH �5�10−7 S�. When either or both inputs

FIG. 1. Double-gate field-effect-transistor �DG-FET� device simulationbased on Poisson-continuity equations: w=1 cm, L=5 �m, tdie 1= tdie 2

=200 nm,�semicond=3.00, �die 1=�die 2=2.65, ni=4�1020 cm−3 ,y0=−y0=20nm, �=−2.8 V, T=298 K, �=8�10−4cm2/V s �see Ref. 16�. �a� Com-puted charge carrier density as a function of channel distance �y� with Vch

=−30 V and Vg1=60 V for different values of Vg2. Inset: Schematic diagramof DG-FET. �b� Computed electric field as a function of y with Vch=−30 V and Vg1=−60 V. �c� Computed areal charge density as a function ofchannel location �x� with Vd=−30 V,Vg1=−60 V. �d� Schematic illustrationof the operation of DG-FETs. Upper: When both gates are ON, strong carrieraccumulation forms two well-defined and well-screened channels. Lower:When one gate is sufficiently OFF, the disappearance of carriers in theassociated channel allows the electric field to penetrate and shut off theopposite channel as well.

FIG. 2. Is-Vd output characteristics of the TFB DG-FET: d1=200 nm, d2

=135 nm, d3=40 nm, w=2 cm, L=5 �m, C1=C2=1.72�10−8 F cm−2. (a)Vg2=−60 V and Vg1 varies from 10 to −60 V. (b) Vg1 and Vg2 are synchro-nously stepped from −20 to −60 V �open circles�. The Is-Vd output charac-teristics of a TFB single-gate FET are shown for comparison�closed circles�: d1=200 nm, d3=40 nm, w=2 cm, L=5 �m, C1=1.7�10−8 F cm−2. The saturation hole mobility of this device is 7�10−4 cm2/V s, which decreases to 5�10−4 cm2/V s during the rapid ther-mal anneal. The characteristics of the DG-FETs have been offset by anapparent threshold of −5 V for comparison.

253512-2 Chua, Friend, and Ho Appl. Phys. Lett. 87, 253512 �2005�

This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP:

69.166.47.134 On: Wed, 26 Nov 2014 08:18:31

are low, the device conductance is LOW ��10−11 S�. Theachieved modulation is over four orders of magnitude andthe operation of this logic gate is robust. The device herepresents several advantages over single-gate architecturesowing to halved real estate area and more perfect character-istics matching. We also expect that DG-FETs can be fabri-cated for the n-channel organic transistors that have recentlybeen demonstrated.18,19

To prove that the coupling is of an electrostatic nature,we fabricated a device with two gating electrodes but withonly one active channel at the bottom interface by depositinga 1.4-�m-thick TFB film. In this case, the top channel be-comes inactive because of space-charge injection resistancethrough the bulk of the film. Therefore, the top gate behavesonly as a secondary �distant� gate without a conduction chan-nel. We found that this secondary gate can still, albeit muchless strongly than before, modulate the conductance of thebottom channel gated by the primary gate, and show thethreshold shifts as described in the Iba7 and Gelinck8 reports.

In conclusion, we have demonstrated an interesting re-gime of operation for double-gate FETs with proper opera-tion of both the conduction channels, and achieved robustAND logic functionality and considerably deeper gate modu-lation than previously possible.

The authors thank Henning Sirringhaus for discussions.L.-L.C. thanks Cavendish Laboratory for financial support.L.-L.C. and P.K.H.H. thank National University of Singaporefor financial support.

1F. Balestra, S. Cristoloveanu, M. Benachir, J. Brini, and T. Elewa, IEEEElectron Device Lett. 8, 410 �1987�.

2J. D. Meindl, Q. Chen, and J. A. Davis, Science 293, 2044 �2001�.3D. Hisamoto, W.-C. Lee, J. Kedzierski, E. Anderson, H. Takeuchi, K.Asano, T.-J. King, J. Bokor, and C. Hu, IEDM Technical Digest, 1032�1998�.

4C. D. Dimitrakopoulos and P. R. L. Malenfant, Adv. Mater. �Weinheim,Ger.� 14, 99 �2002�.

5Y. L. Loo, R. L. Willett, K. W. Baldwin, and J. A. Rogers, J. Am. Chem.Soc. 124, 7654 �2002�.

6C. W. Sele, T. Von Werne, R. H. Friend, and H. Sirringhaus, Adv. Mater.�Weinheim, Ger.� 17, 997 �2005�.

7S. Iba, T. Sekitani, Y. Kato, and T. Someya, Appl. Phys. Lett. 87, 023509

�2005�.8G. H. Gelinck, E. Van Veenendaal, and R. Coehoorn, Appl. Phys. Lett. 87,073508 �2005�.

9L. L. Chua, P. K. H. Ho, H. Sirringhaus, and R. H. Friend, Adv. Mater.�Weinheim, Ger.� 16, 1609 �2004�.

10B. Crone, A. Dodabalapur, A. Gelperin, L. Torsi, H. E. Katz, A. J. Lov-inger, and Z. Bao, Appl. Phys. Lett. 78, 2229 �2001�.

11Z. T. Zhu, J. T. Mason, R. Dieckmann, and G. G. Malliaras, Appl. Phys.Lett. 81, 4643 �2002�.

12B. Crone, A. Dodabalapur, Y. Y. Lin, R. W. Filas, Z. Bao, A. LaDuca, R.Sarpeshkar, H. E. Katz, and W. Li, Nature �London� 403, 521 �2000�.

13R. C. G. Naber, C. Tanase, P. W. M. Blom, G. H. Gelinck, A. W.Marsman, F. J. Touwslager, S. Setayesh, and D. M. De Leeuw, Nat. Mater.4, 243 �2005�.

14L. L. Chua, P. K. H. Ho, H. Sirringhaus, and R. H. Friend, Appl. Phys.Lett. 84, 3400 �2004�.

15A p-doped Si wafer with 200-nm of thermal oxide was used as a conve-nient bottom gate electrode and dielectric couple. 3-nm Cr and 30-nm Auinterdigitated source-drain electrodes were then fabricated by standardphotolithography lift-off. The electrode patterns were then cleaned in oxy-gen plasma, water rinse, followed by nitrogen blow-off, and then trim-ethysilylated with hexamethyldisilazane at 120°C for 10-min. 40-nm-thickTFB film was then deposited from a mesitylene solution and annealed at130°C for 15-min in N2. 135-nm-thick BCB was then deposited from adecane solution at 45°C and thermally crosslinked at 290°C for 25s in N2.10 �m-thick PEDT:PSSR was then deposited over the interdigitated arrayand annealed at 180°C for 2min in N2 to give the top-gate contact. Thedevices were then measured in nitrogen in a semiconductor parameteranalyser �Keithley SCS4200�.

16The Poisson and electric field equations:

d2�

d2y=

e

�semicond�oniexp� e�� − Ef�

kT�

d�

dy= − E

were solved numerically using standard boundary conditions:

��semicondd�

dy�

y0

= �die1Vg1 − ��y0� + �g1

tdie 1

��semicondd�

dy�

−y0

= − �die 2Vg2 − ��− y0� + �g2

tdie 2

where � is potential of the charge carrier; y is thickness of semiconductor�spanning +y0 to −y0�; ni is effective density of states; Ef is channel Fermipotential; �semicond is semiconductor dielectric constant; �0 is permittivityof free-space; �die�1,2� is the respective gate-insulator dielectric constant,tdie�1,2� is the respective gate-insulator thickness; �i is contact potentialbetween the gate electrode and the semiconductor. Together with thecurrent continuity equation, we solved for the potential and charge den-sity across the channel in a first-order description of the device perfor-mance which provides all the essential inputs to understanding of theelectrostatic coupling between the two channels:

Ids =w

L��

Vs

Vd

n�Vch�dVch

where w is channel width; L is channel length; � is field-effect mobility; nis channel areal charge density; Vch is channel Fermi level.17W. F. Pasveer, J. Cottaar, C. Tanase, R. Coehoorn, P. A. Bobbert, P. W. M.

Blom, D. M. De Leeuw, and M. A. J. Michels, Phys. Rev. Lett. 94,206601 �2005�.

18E. J. Meijier, D. M. De Leeuw, S. Setayesh, E. Van Veenendaal, B. H.Huisman, P. W. M. Blom, J. C. Hummelen, U. Scherf, and T. M. Klapwijk,Nat. Mater. 2, 678 �2003�.

19L.-L. Chua, J. Zaumseil, J.-F. Chang, E. C.-W. Ou, P. K.-H. Ho, H.Sirringhaus, and R. H. Friend, Nature �London� 3376, 195 �2005�.

FIG. 3. An AND logic element from a single four-terminal DG-FET. (a)Gives the input trace applied to Vg1. (b) Gives the input trace applied toVg2�HIGH=−60 V, LOW= +20 V�. (c) Shows the Id output trace.

253512-3 Chua, Friend, and Ho Appl. Phys. Lett. 87, 253512 �2005�

This article is copyrighted as indicated in the article. Reuse of AIP content is subject to the terms at: http://scitation.aip.org/termsconditions. Downloaded to IP:

69.166.47.134 On: Wed, 26 Nov 2014 08:18:31