Upload
mave
View
50
Download
0
Embed Size (px)
DESCRIPTION
Optimization of Verification Effort using Reusable Sequence Collection. Dipesh Handa Gaurav Chugh Gaurav Minda Kumar Rajeev Ranjan. Authors. Gaurav Minda CAE + 91-11-49233952 [email protected] Kumar Rajeev Ranjan CAE + 91-11-49233955 [email protected]. - PowerPoint PPT Presentation
Citation preview
Optimization of Verification Effort using
Reusable Sequence Collection
Dipesh HandaGaurav ChughGaurav Minda
Kumar Rajeev Ranjan
Authors
Dipesh Handa : R & D Engineer +91-11-49233970 [email protected]
Gaurav Chugh
Manager CAE +91-11-49233980 [email protected]
Gaurav Minda
CAE +91-11-49233952 [email protected]
Kumar Rajeev Ranjan CAE +91-11-49233955 [email protected]
Agenda
• Introduction Reusable sequence collection Guidelines to develop reusable sequences
• Use model
• Benefits
Reusable Sequence Collection
• It is a set of configurable sequences with different level of complexities.
• Depending on requirement, user can use different level of sequences.
• Different levels can be –
Level 0 - Sequences to model functionality check for basic operations
Level 1 - Sequences to model functionality check for basic scenarios Level 2 - Sequences to model functionality check for complex scenarios
• Sequence collection should be implemented in layered architecture
NOTE : Levels may increase as per requirement of complexity.
Level 2
Level 1
Level 0
COMPLEXITY
Guidelines : Reusable Sequence Collection
Sequence collection should be implemented in layered architecture
Level 1 sequences will use Level 0 sequences and Level 2 sequences will use level 1 sequences and so on
Level 0 sequences : Model basic scenarios like Single READ, Single WRITE. Identify configurable properties of transaction class and declare them
as local properties Configuration mechanism to get value of local properties and assign the
local properties to transaction properties
Level 1 sequences : Model intermediate scenarios like READ followed by WRITE. Declare local properties in Level 1 sequence to map with the Level 0
sequence properties Configuration mechanism to get value of local properties and assign the
local properties to sequence 0 properties
Better Understanding of Implementation and Guidelines
Scenario : Multiple number of Write -> Read operation between Master and Slave
Master transaction class :
MASTER SLAVE
Clock
data
Class master_transaction extends uvm_transaction; rand bit [7:0] address = 8’h01; rand bit [7:0] data = 8’h00; rand bit [1:0] command; bit enable; bit reset;
constraint valid_cmd { command inside {READ, WRITE}; }constraint valid_data {data inside {[8’h00:8’hff]};}constraint valid_addr {address inside {[8‘h00, 8’h04]};}endclass : master_transaction
Out of 5 properties only 2 properties (address and data) can be reused.
Commonly used in all scenariosCommonly used in all scenarios
Constraints to provide control on range
Class wr/rd_seq_level0 extends uvm_sequence #(master_transaction) rand bit [7:0] address = 8’h01; rand bit [7:0] data = 8’h00;constraint valid_range {address inside {[8’h00: 8’h04]}} // controlled value of local variables ------------------------ ------------------------virtual task body();// getting values in local variables from test case leveluvm_config_db#(bit[7:0]) :: get (null, get_full_name(),”address” , address);uvm_config_db#(bit[7:0]) :: get (null, get_full_name(),”data” , data);
`uvm_do_with(req, { req.address == address; req.data == data; req.command == WRITE/READ; }) // Write transactionendtask: bodyendclass : wr_seq_level0
Level 0 Sequence for Write and Read transfer
Declaration and initialization of Local properties of random type
Apply constraint on local properties
UVM Configuration setting to get value from test case
level
Applying local properties as constraints to generate
transaction
Class wr_rd_seq_level1 extends uvm_sequence #(master_transaction) rand int unsigned count = 1; rand bit [7:0] address = 8’h01; rand bit [7:0] data = 8’h00; constraint valid_range (address inside {[8’h00: 8’h04]}; count inside {[0:10]}; ) // controlled value of local variables ------------------------ wr_seq_level1 wr; // handle of Level 0 write sequence rd_seq_level1 rd; // handle of Level 0 read sequence ------------------------virtual task body();// getting values in local variables from higher leveluvm_config_db#(bit[7:0]) :: get (null, get_full_name(),”address” , address);uvm_config_db#(bit[7:0]) :: get (null, get_full_name(),”data” , data);uvm_config_db#(int unsigned) :: get (null, get_full_name(),”count” , count);
for(int i =0; i<count; i++) // no. of iteration begin `uvm_do_with(wr, { wr.address == address; wr.data == data; }) // Write transaction `uvm_do_with(rd, { rd.address == address;}) // Read transaction endendtask: bodyendclass: wr_rd_seq_level1
Level 1 Sequence for multiple Write-Read transaction
Local properties of level 1 sequenceLocal properties of level 1 sequence
Handles of level 0 sequences
Handles of level 0 sequences
Configuration mechanism to get
the value from test case
Configuration mechanism to get
the value from test case
Applying local properties as constraints to generate
transaction
Count to generate multiple transaction
Class seq_test extends uvm_test; ----------------------- ------------------------virtual function void build_phase(uvm_phase phase);
// Apply the master sequence to the master sequenceruvm_config_db#(uvm_object_wrapper)::set(this,"env.master.sequencer.main_phase", "default_sequence", wr_rd_seq_level1 ::type_id::get());
// Apply directed values to local variables of sequence uvm_config_db#(int unsigned)::set(this,"env.master.sequencer.wr_rd_seq_level1",“count", 2);uvm_config_db#(bit [7:0])::set(this, "env.master.sequencer.wr_rd_seq_level1",“address", 8‘h02);uvm_config_db#(bit [7:0])::set(this,"env.master.sequencer.wr_rd_seq_level1",“data", 8’hff);
endfunction: build_phaseendclass: seq_test
Test to provide configuration information to sequence
Configuration setting to set default sequence on manster
sequencer
Configuration setting to pass directed value to sequence
properties
Captured Configurable Fields from various protocols
AXI
UART
IdAddressBurst_lengthBurst_sizeBurst_typeCmd_typeDataWrite_strob etc.
count_packetrts_delaycts_delaydelay_packetspayload etc.
MIPI CSI2
Virtual_channel_idNum_data_linesNum_embedded_linesNum_data_pixelsNum_embedded_pixelsNum_frames etc.
Benefits
It optimizes the verification process by reducing Number of sequences Time span Manual Efforts Engineering Cost
In Terms of With Reusability Without Reusability
Number of Test & Sequences required
~5 Reusable Sequences ~30 Normal Directed Sequences
• Comparative Study
Abstract
As a result of increasing complexity of Designs, majority of verification effort goes into stimulus pattern generation by writing UVM/OVM sequences and tests. Sometimes there is no reuse across common type of sequences which results in code duplication and verification closure time is on higher side
This paper showcases the concept of building reusable UVM/OVM sequences which can be used to generate different stimulus patterns by configuring the reusable sequences. Reusability reduces code verification efforts and verification closure time. Code snippet of sample reusable sequences are shown to help verification engineers to apply the same concepts while building the reusable sequences for different protocols like AMBA, UART, MIPI