OPTICAL NEW QUADRUPLE UNIVERSAL GATE (QUG) USING SLM …

DOI:10.21884/IJMTER.2018.5021.0IQCP 125

OPTICAL NEW QUADRUPLE UNIVERSAL GATE (QUG) USING SLM BASED

SAVART PLATE

Animesh Bhattacharya1, Goutam K Maity

2 and Amal K Ghosh

3

1Department of Applied Electronics and Instrumentation Engineering, Netaji Subhash Engineering College,

Techno City, Garia, Kolkata-700152, India 2Department of Physics, Pingla Thana Mahavidyalaya, Maligram, Paschim Medinipur – 721140, India

3Department of Applied Electronics and Instrumentation Engineering Netaji Subhash Engineering College,

Techno City, Garia, Kolkata-700152, India

Abstract- The advantages of technology during the last two decades have generated a large demand for

handling large volumes of data at high speed. To meet up the requirements, the concept of multi valued

logic (MVL) came forward from the status of the two-valued or binary logic system in the one hand and

on the other, these include the idea of optical processor for switches. The conventional binary system

has reached its saturation point in terms of complexity and data-handling. MVL system consists of a

number of intermediate states between the true and false state instead of the conventional binary logic

which consists of only two states „true‟ and „false‟. In quadruple valued logic (QVL) system the

additional two intermediate states are denoted as „partially known‟ and „partially unknown‟. In this

paper we have designed and implemented Optical New Quadruple Universal Gate (QUG) using Spatial

Light Modulator (SLM) and Savart Plate. We have also explained their principles of operation used a

theoretical model to fulfill this task, finally confirming through numerical simulations.

Keywords- MVL, QUG, QVL, Savart Plate, SLM.

I. INTRODUCTION

The multi valued logic (MVL) system is the most suitable in optical computation for handling

huge volumes of data at high speed. High-speed arithmetic computing system is developed utilizing the

parallelism of optics. The parallel operation can be easily performed using optical processors. Using the

polarization states of light along with its presence or absence, it is also possible for implementation of

MVL in optical system [1]. The Avizienis introduced a signed digit number as the parallelism of optical

beam [2]. The modified signed digit [3-5] or modified trinary [6-8] number system also suggested the

carry free operation. However, the ternary logic system based on three states was introduced by

Lukasiewicz [9]. After that the trinary logic system is modified to the four states logic for better

proposition. The quadruple-valued logic (QVL) system based on four state logic using SLM and Savart

Plate is already implemented in our earlier paper [10-12]. The SLM and Savart plate take an important

role for optical implementation. The purpose of savart plate is to split the light into two orthogonal

components whereas SLMs block or pass the light depending on the electrical signals applied on it. The

property of negative SLM is just the opposite of positive SLM. Here the input is considered as in the

form of di-bit (two bits) representation. The different states of QVL system are implemented in the form

of di-bit representation using two orthogonal polarization states of light beam with their presence and

absence [11].

The available universal gates are NAND and NOR Gates. The NAND gate is already

implemented by SOA‐based Mach–Zehnder interferometer (MZI) [13-14] in binary domain. With this

aim, we have presented Optical new quadruple universal gate (QUG) using SLM and Savart Plate in this

International Journal of Modern Trends in Engineering and Research (IJMTER)

Volume 05, Issue 1, [January– 2018] ISSN (Online):2349–9745; ISSN (Print):2393-8161

@IJMTER-2018, All rights Reserved 126

paper. All the basic quadruple logic gates are implemented using this QUG in this paper also. The

superiority of the proposed scheme is verified by simulation results.

The paper is organized as follows: Section 2 represents the basic principals of optical new

Quadruple universal Gate. Implementation of Different Quadruple Logic Gates using new Quadruple

universal Gate are reported in Section 3. Section 4 presents the simulation result of all designed gates.

Section 5 contains the final Concluding remarks.

II. OPTICAL NEW QUADRUPLE UNIVERSAL GATE (QUG)

In this section we have proposed a new quadruple universal gate as shown in the Figure 1. By

using this gate we can easily implement the operation of all other logic gates like NOT, AND, OR,

NAND, NOR, XOR and XNOR.

Figure 1. Basic diagram of New Quadruple Universal Gate

We are considering A and B as inputs of our proposed new QUG and F= .B as the output. The

block diagram of the gate is shown in the Figure 2.

Figure 2. Block diagram of New Quadruple Universal Gate

Now, we are going to represent the new quadruple universal gate optically using SLM (Spatial

Light Modulator) and Savart plate. Here the input A is considered in its di-bit form as A1 and A2 and B

as B1 and B2. The New Quadruple Universal Gate has been optically synthesized in Figure 3. In the

circuit the savart plates S1,S2,S3,S4 and S5 form the NOT gate and savart plates S7,S8,S9 and S10

constitute the AND gate.

Figure 3. Optical New Quadruple Universal Gate




The light from the laser source after being polarized at an angle 45 degrees with respect to the

crystal axes is incident on the beam splitter BS1, where the light ray is split into two directions: one of

which is incident on beam splitter BS2 and another after getting reflected by mirror M6 is incident on

savart plate S7, as shown in Fig 3. The other beam splitter BS2 again splits the polarized light ray into

two directions: one of which is incident on the savart plate S1 and the other one being reflected by the

mirror M1 is incident on S4. The light incident on the savart plate S1 will be shifted into two orthogonal

components and comes out of them in two parallel beams with a spatial shift in between them (where the

first ray is considered to have the horizontal polarization state and the other ray having vertical

polarization state). The electrically addressable positive SLMs – P1 and P2 are controlled by the input A

(A1, A2). The output beams are then combined by using a second Savart plate S2 whose crystal axes are

in opposite to that of first Savart plate S1 and in the light coming out of the savart plate S2, the essential

components of the polarized beams are present accordingly. Now it is allowed to pass through the savart

plate S3, where, the opto-electrical converters (O/E) C1 and C2 are used in the path of the rays to convert

the light signal into electric voltage – which are fed to the negative SLMs P3 and P4 to control the

polarized components of the beam coming out of the savart plate S4. The savart plate S5 is used to re-

unite the final components and get the final output, which is simply the complement of the input A. This

output is passed through the O/E convertors C3 and C4 to convert optical signal into electric voltage to

control one of the inputs of the AND gate through the positive SLMs P5 and P6 and modulate the two

orthogonal components coming out from the savart plate S7. The light rays are reunited by S8. The light

ray is incident in next savart plate S9 and similarly modulated by the positive SLMs P7 and P8,

depending on the other input B (B1, B2). The rays are finally recombined by S10 to produce the final

output .B.

III. IMPLEMENTATION OF DIFFERENT QUADRUPLE LOGIC GATES USING NEW

QUADRUPLE UNIVERSAL GATE

In this section all the basic quadruple logic gates are implemented using the Optical New

Quadruple Universal Gate.

3.1 Implementation of Quadruple NOT Gate

Quadruple NOT gate using the new quadruple universal gate is shown in the Figure 4. Here, we

are considering X (X1, X2) as one input and the other input is 3(1, 1). The NOT gate gives the output

or the complement of the input X.

Figure 4. Block diagram of Quadruple NOT gate using New Quadruple Universal Gate

The truth table for the Quadruple NOT gate for all the possible combinations of the input X is shown in

the Table 1.

Table 1. Truth table of Quadruple NOT gate using New Quadruple Universal Gate INPUTS OUTPUT

X X1 X2 Y Y1 Y2 F1 F2 F

0 0 0 3 1 1 1 1 3

0 0 0 3 1 1 1 1 3




0 0 0 3 1 1 1 1 3

0 0 0 3 1 1 1 1 3

1 0 1 3 1 1 1 0 2

1 0 1 3 1 1 1 0 2

1 0 1 3 1 1 1 0 2

1 0 1 3 1 1 1 0 2

2 1 0 3 1 1 0 1 1

2 1 0 3 1 1 0 1 1

2 1 0 3 1 1 0 1 1

2 1 0 3 1 1 0 1 1

3 1 1 3 1 1 0 0 0

3 1 1 3 1 1 0 0 0

3 1 1 3 1 1 0 0 0

3 1 1 3 1 1 0 0 0

Now, we are going to represent quadruple NOT gate using the New Quadruple Universal Gate

optically by using SLM (Spatial Light Modulator) and Savart plates as shown in Figure 5.

Figure 5. Optical Quadruple NOT gate using New Quadruple Universal Gate

The NOT gate works on same principle as the basic block of the universal gate except that an

input of 3 (1, 1) is given to the positive SLMs P7 and P8 respectively. Hence the Output is controlled

only by the input X (X1, X2).

When the input is X=1(X1 = 0, X2 = 1), then the positive SLMs P1 will block the horizontal

polarized state of light and P2 will allow only the vertical polarized state of light. The output from S2

will consist of only the vertically polarized light. No light ray is incident on M2. Light ray with vertically

polarized light only will be incident on M3. P3 will receive no electrical signal and P4 will receive signal

with high voltage. Since negative SLM is used, it will allow horizontally polarized light and block the

vertical one. Thus ray from S5 will consist only of the horizontally polarized light. The horizontally

polarized light is reflected by M2 and no light ray will be reflected by M5. P5 will receive signal with

high voltage and P6 will receive no electrical signal. Since high voltage is already received by both

SLMS P7 and P8, so it will allow the respective two components of light to pass through them. As only

horizontally polarized light is present at the output of savart plate S8 so the final output consists of only

horizontally polarized light i.e. F=2(F1 = 1, F2 =0).




When X= 3 (X1 = 1, X2 = 1), then there will be no light at the final output i.e. F=0(F1 = 0, F2 =0).

Similarly for the other different combinations of X, the results can be verified.

3.2 Implementation of Quadruple AND Gate

Quadruple AND gate using the new quadruple universal gate is shown in the Figure 6. Here, two

new quadruple universal gates are used to design the Quadruple AND gate where „1‟ represents the first

block corresponding to the 1st new quadruple universal gate and „2‟ represents the second block

corresponding to the 2nd

new quadruple universal gate. The inputs of the first block are X (X1, X2) and

3 (1, 1). It gives the output (F1) of complemented X which is again fed as the first input to the next

block. The second input of the second block is Y (Y1, Y2). The second block produces the final output F2

= X.Y.

Figure 6. Block diagram of Quadruple AND gate using New Quadruple Universal Gate

The truth table for the Quadruple AND gate for all the possible combinations of the inputs X and

Y is shown in the Table 2.

Table 2. Truth table of Quadruple AND gate using New Quadruple Universal Gate INPUTS OUTPUT

X X1 X2 Y Y1 Y2 F21 F22 F2

0 0 0 0 0 0 0 0 0

0 0 0 1 0 1 0 0 0

0 0 0 2 1 0 0 0 0

0 0 0 3 1 1 0 0 0

1 0 1 0 0 0 0 0 0

1 0 1 1 0 1 0 1 1

1 0 1 2 1 0 0 0 0

1 0 1 3 1 1 0 1 1

2 1 0 0 0 0 0 0 0

2 1 0 1 0 1 0 0 0

2 1 0 2 1 0 1 0 2

2 1 0 3 1 1 1 0 2

3 1 1 0 0 0 0 0 0

3 1 1 1 0 1 0 1 1

3 1 1 2 1 0 1 0 2

3 1 1 3 1 1 1 1 3

The quadruple AND gate using the new quadruple universal gate has been represented optically in

Figure 7.

The savart plates S1, S2, S3, S4, S5, S6, S7, S8, S9 and S10 along with the positive SLMs P1, P2, P5,

P6, P7, P8 and negative SLMs P3 ,P4 constitute the 1st new quadruple universal gate (denoted as block 1

in Figure 6), whose first input X (X1, X2) is fed through the positive SLMs P1 and P2 and the other

input 3 (1, 1) is fed through positive SLMs P7 and P8 to produce the output F1= .




The savart plates S12, S13, S14, S15, S16, S17, S18, S19, S20 and S21 along with the positive SLMs P9,

P10, P13, P14, P15, P16 and negative SLMs P11, P12 constitute the 2nd

new quadruple universal gate

(denoted as block 2 in Figure 6) used whose first input (output from the first New Quadruple

Universal Gate ) is fed through the positive SLMs P9 and P10 and the other input Y (Y1, Y2) is fed

through positive SLMs P15 and P16 to produce the final output F2=X.Y

Figure 7. Optical Quadruple AND gate using New Quadruple Universal Gate

The light output of the laser source after being polarized at an angle 45 degrees with respect to

the crystal axes is incident on the beam splitter BS1, where the light ray is split into two directions: one

of which is incident on beam splitter BS2 and another after getting reflected by mirror M6 is incident on

savart plate S7 as shown in Figure 7. The complement of A is the output of the savart plate S5. This

output is fed to the savart plate S11 along with the O/E convertors C5 and C6 that are used provide the

electrical input (the complemented X in di-bit form) to the next universal gate through the positive

SLMs P9 and P10 . The other input Y (Y1, Y2) is given to the gate through the positive SLMs P15 and P16.

The savart plate S21 provides the final output.

Let us consider a case for the inputs X= 1(X1 = 0, X2 = 1) and Y= 2 (Y1 = 1,Y2 = 0), as X1 and X2

are given through the positive SLMs P1 and P2, so P1 will block the horizontally polarized light and P2

will allow the vertically polarized light only. The output from S3 consists of only vertically polarized




light ray. C1 produces no electrical output and C2 produces an electrical output with high voltage. They

are fed to the negative SLMs P3 and P4 respectively. P3 will allow the horizontally polarized light and P4

will block the vertically polarized light. The output from S5 consists of only the horizontally polarized

light. C3 will produce high electrical voltage and C4 will produce zero voltage. So P5 receiving the input

from C3 will allow the horizontally polarized light and P6 receiving the input from C4 will block the

vertically polarized light. Since P7 and P8 both receive high voltage input, and since they are positive

SLMs, they will allow the components as received from the Savart plates S9. Similarly C5 will produce

high electrical voltage and C6 will produce zero voltage. P9 receiving the input from C5 will allow the

horizontally polarized light and P10 receiving the input from C6 will block the vertically polarized light.

C7 will produce high electrical voltage and C8 will produce zero voltage. P11 receiving the input from C7

will block the horizontally polarized light and P12 receiving the input from C8 will allow the vertically

polarized light (since P11 and P12 are negative SLMs). Thus output from S16 consists of only the

vertically polarized light. It is then fed to the Savart plate S17. The O/E convertors C9 will produce no

voltage and C10 will produce high voltage. Thus P13 receiving input from C9 will block horizontally

polarized light and P14 will allow the vertically polarized light. Thus output from S19 consists of only the

vertically polarized light. The other input Y is given through the positive SLMs P15 and P16. Thus P15

supposed to allow the horizontally polarized light and P16 supposed to block the vertically polarized

light won‟t allow any component to pass, because the output from S19 consists only the vertically

polarized light which later gets blocked by the positive SLM P16. No light component is incident on the

savart plate S21.Thus the final output consists of none of the two light components ie, F2=0 (F21 =0 and

F22 = 0). Hence the output from the Table 2 is verified for the inputs X=1 and Y=2.

For the inputs X=0 (X1= 0, X2= 0) and Y=3 (Y1=1, Y2=1) there will be no light present at the

final output, leading to F2=0(F21= 0, F22= 0).

For the inputs X=2 (X1= 1, X2= 0) and Y=2 (Y1=1, Y2=0), the final output consists of only

horizontally polarized light i.e. F2=2(F21= 1, F22= 0).

For the inputs X=3 (X1= 1, X2= 1), and Y=1 (Y1=0, Y2=1), the final output consists of only vertically

polarized light i.e. F2= 1(F21= 0, F22= 1).

Similarly, for other different combinations of inputs X and Y, the results can be verified

according to Table 2.

3.3 Implementation of Quadruple OR Gate

Quadruple OR gate using the new quadruple universal gate is shown in the Figure 8. Here, three

new quadruple universal gates are used to design the Quadruple OR gate where „1‟ represents the first

block corresponding to the 1st new quadruple universal gate, „2‟ represents the second block


new quadruple universal gate and „3‟ represents the third block corresponding

to the 3rd

new quadruple universal gate.

We are considering Y (Y1, Y2) as one of the inputs to the first block and the other input is 3 (1,

1). The output (F1) of this first block is complemented Y that is again fed as the second input to the

second block. The first input of this block is X (X1, X2). The output of this second block is F2= . This

output is fed as first input of the third block. The second input of this block is 3 (1, 1). The output of this

block gives the final output F3 = X+Y.

Figure 8. Block diagram of Quadruple OR gate using New Quadruple Universal Gate




The truth table for the Quadruple OR gate for all the possible combinations of the inputs X and Y is

shown in the Table 3.

Table 3. Truth table of Quadruple OR gate using New Quadruple Universal Gate

INPUTS OUTPUT

X X1 X2 Y Y1 Y2 F31 F32 F3

0 0 0 0 0 0 0 0 0

0 0 0 1 0 1 0 1 1

0 0 0 2 1 0 1 0 2

0 0 0 3 1 1 1 1 3

1 0 1 0 0 0 0 1 1

1 0 1 1 0 1 0 1 1

1 0 1 2 1 0 1 1 3

1 0 1 3 1 1 1 1 3

2 1 0 0 0 0 1 0 2

2 1 0 1 0 1 1 1 3

2 1 0 2 1 0 1 0 2

2 1 0 3 1 1 1 1 3

3 1 1 0 0 0 1 1 3

3 1 1 1 0 1 1 1 3

3 1 1 2 1 0 1 1 3

3 1 1 3 1 1 1 1 3 Now, we are going to represent the quadruple OR gate using the New Quadruple Universal Gate



P6, P7, P8 and negative SLMs P3, P4 constitute the 1st New Quadruple Universal Gate (denoted as block

1 in Figure 8), whose first input Y (Y1, Y2) is fed through the positive SLMs P1 and P2 and the other

input 3 (1, 1) is fed through positive SLMs P7 and P8 to produce the output F1= .

The savart plates S12 ,S13, S14, S15, S16, S17, S18, S19, S20 and S21 along with the positive SLMs P9,


New Quadruple Universal Gate

(denoted as block 2 in Figure 8), whose first input X (X1, X2) is fed through the positive SLMs P9 and

P10 and the other input ( output from the first New Quadruple Universal Gate ) is fed through positive

SLMs P15 and P16 to produce the output F2= .


P18, P21, P22, P23, P24 and negative SLMs P19 ,P20 constitute the 3rd


(denoted as block 3 in Figure 8), whose first input (output from the second New Quadruple

Universal Gate ) is fed through the positive SLMs P17 and P18 and the other input 3 (1, 1) is fed through

positive SLMs P23 and P24 to produce the final output F3= X+Y.




Figure 9. Optical Quadruple OR gate using New Quadruple Universal Gate

The light output from the laser source after being polarized at an angle 45 degrees with respect to



savart plate S7. The other input Y (Y1, Y2) is given through the positive SLMs P1 and P2 and the other

input of this gate is 3 (1, 1) that is fed through the positive SLMs P7 and P8. The output of this gate is

(complemented Y) fed to the savart plate S11 along with the O/E convertors C5 and C6 that provide one

of the electrical inputs to the second universal gate through the positive SLMs P15 and P16. BS3 receives

the light input from the mirror M6 and splits the ray into two directions: one of which is incident on the

savart plate S7 and other one which is incident on M9 provides light for operation of second universal

gate. The other input of this second universal gate is X (X1, X2) that is given through the positive SLMs




P9 and P10 respectively. The output of this gate is fed to the savart plate S22 along with O/E convertors

C11 and C12 to provide one of the electrical inputs to the third universal gate through the positive SLMs

P17 and P18 respectively. BS6 that receives the reflected ray from the mirror M15, divides the ray in two

directions: one of which is incident on the savart plate S18 and other part is incident on the mirror M20 to

provide light for the operation of the third universal gate. The other input 3 (1, 1) of this gate is fed

through the positive SLMs P23 and P24. The output from this gate provides the final output.

Let us consider a case, when the inputs are X= 1(X1 = 0, X2 = 1) and Y= 2(Y1 = 1, Y2 = 0)

respectively. The positive SLMs P1 and P2 are affected by the input Y. P1 will allow the horizontally

polarized light and P2 will block the vertically polarized light. As a result the output from the savart

plate S2 consists of only the horizontally polarized light which is fed to the next savart plate S3 along

with O/E convertors C1 and C2. C1 produces high voltage and C2 produces zero voltage that is fed to the

negative SLMs P3 and P4 respectively. Thus P3 will block the horizontally polarized light and P4 will

allow the vertically polarized light. Output from S5 consists of only the vertically polarized light which

is fed to the savart plate S6 along with the O/E convertors C3 and C4. C3 produces zero voltage and C4

produces high voltage that is fed to the positive SLMs P5 and P6 respectively. Thus the P5 will block the

horizontally polarized light and P6 will allow the vertically polarized light. The output from S8 consists

of only the vertically polarized light which is fed to next savart plate S9. Since both the positive SLMs P7

and P8 receive high voltage, it will allow the vertically polarized light to pass through it. The output

from the savart plate S10 consists of only the vertically polarized light. It is then fed to S11 along with the

O/E convertors C5 and C6. C5 produces zero voltage and C6 produces high voltage output that are fed to

the positive SLMs P15 and P16 respectively. The input X is given through the positive SLMs P9 and P10.

Thus P9 will block the horizontally polarized light and P10 will allow the vertically polarized light. The

output from the savart plate S13 consists of only the vertically polarized light which is fed to the next

savart plate S14 along with O/E convertors C7 and C8. C7 produces zero voltage and C8 produces high

voltage that is fed to the negative SLMs P11 and P12 respectively. As a result P11 will allow the

horizontally polarized light coming from the S15 and P12 will block the vertically polarized light. Output

from S16 consists of only the horizontally polarized light which is fed to the savart plate S17 along with

the O/E convertors C9 and C10. Thus C9 produces high voltage and C10 produces zero voltage that is fed

to positive SLMs P13 and P14 respectively. Thus it will allow the horizontally polarized light incident

from the savart plate S18 and block the vertically polarized light . So the output from the savart plate S19

consists of only the horizontally polarized light which is fed to the next savart plate S20. P15 and P16

receiving zero and high voltage respectively will block the incoming horizontally polarized light. The

output from the savart plate S21 consists of no light components. The O/E convertors C11 and C12 both

produces zero voltage output that is fed to the positive SLMs P17 and P18 respectively. Thus both will

block the incoming light components from S23. Since no light ray is incident on output S24 and the O/E

convertors C13 and C14 produces zero output voltage that are fed to the negative SLMs P19 and P20. Thus

both P19 and P20 will allow both the horizontal and vertically polarized light incident from the savart

plate S26 to pass through respectively. Thus the output from S27 consists of the orthogonal components

which are incident on the savart plate S28 along with the O/E convertors C15 and C16. Both these

convertors will produce high voltage output. It is fed to the positive SLMs P21 and P22 respectively. Thus

both P21 and P22 will allow both the horizontal and vertical light components incident from the savart

plate S29 to pass through. Thus both the light components are present in the output from S30 which are

fed to the next savart plate S31. Since both the positive SLMs P23 and P24 receive high voltage input, it

further allows both the incoming light components. Both polarization states of light are incident on the

savart plate S32. Thus final output consists of both the polarization states of light i.e.F3= 3( F31=1 and

F32= 1). Hence the output from Table 3 is verified for the inputs X=1 and Y=2 respectively.




For the inputs X=0 (X1= 0, X2= 0), and Y=2 (Y1=1, Y2=0), the final output consists of only horizontally

polarized light, leading to F2=2 (F31= 1 and F32= 0).

In the similar way the other different cases can be explained according to Table 3.

3.4 Implementation of Quadruple NAND Gate

Quadruple NAND gate using the new quadruple universal gate is shown in the Figure 10. It is

just combination of AND and followed by NOT gate. Here, three new quadruple universal gates are

used to design the Quadruple NAND gate where „1‟ represents the first block corresponding to the 1st

new quadruple universal gate, „2‟ represents the second block corresponding to the 2nd

new quadruple

universal gate and „3‟ represents the third block corresponding to the 3rd


We are considering X(X1, X2) as one of the inputs of the first block and the other input is 3(1, 1). The

output (F1) of the first block is which is fed as the first input to the second block. The second input is

Y(Y1,Y2). The output of this block is F2= X.Y which is fed as the first input to the third block. The

second input of this block is 3. The output of this third block is F3 = .

Figure 10. Block diagram of Quadruple NAND gate using New Quadruple Universal Gate

3.5 Implementation of Quadruple NOR Gate

Quadruple NOR gate using the new quadruple universal gate is shown in the Figure 11. Here,

two new quadruple universal gates are used to design the Quadruple NOR gate where „1‟ represents the

first block corresponding to the 1st new quadruple universal gate and „2‟ represents the second block


new quadruple universal gate. We are considering Y (Y1, Y2) as one of the

inputs of the first block. The other input of this block is 3 (1, 1). The output (F1) of this block is which

is fed as the second input to the second block. The first input of this second block is X (X1, X2). The

output of this second block is F2 =

Figure 11. Block diagram of Quadruple NOR gate using New Quadruple Universal Gate

3.6 Implementation of Quadruple XNOR Gate

Quadruple XNOR gate using the new quadruple universal gate is shown in the Figure 12. Here,

four new quadruple universal gates are used to design the Quadruple XNOR gate where „1‟ represents

the first block corresponding to the 1st new quadruple universal gate, „2‟ represents the second block


new quadruple universal gate, „3‟ represents the third block corresponding to

the 3rd

new quadruple universal gate and „4‟ represents the fourth block corresponding to the 4th

new

quadruple universal gate.




We are considering that X (X1, X2) is fed as the first input and Y(Y1, Y2) as the second input to

the first block which produces the output F1 = . Again in the second block Y is fed as the first input

and X is fed as the second input that produces the output F2 = The output of the first block is fed as

the first input of the third block whose second input is 3(1,1) and it produces a output of F3 = . The

output of the second block is fed as the first input of the fourth block. The output F3 is again fed to the

second input of the fourth block that produces the output F4= ( ).

Figure 12. Block diagram of Quadruple XNOR gate using New Quadruple Universal Gate

The truth table for the Quadruple XNOR gate for all the possible combinations of the inputs X

and Y is shown in the Table 4.

Table 4. Truth table of Quadruple XNOR gate using New Quadruple Universal Gate INPUTS OUTPUT

X X1 X2 Y Y1 Y2 F41 F42 F4

0 0 0 0 0 0 1 1 3

0 0 0 1 0 1 1 0 2

0 0 0 2 1 0 0 1 1

0 0 0 3 1 1 0 0 0

1 0 1 0 0 0 1 0 2

1 0 1 1 0 1 1 1 3

1 0 1 2 1 0 0 0 0

1 0 1 3 1 1 0 1 1

2 1 0 0 0 0 0 1 1

2 1 0 1 0 1 0 0 0

2 1 0 2 1 0 1 1 3

2 1 0 3 1 1 1 0 2

3 1 1 0 0 0 0 0 0

3 1 1 1 0 1 0 1 1

3 1 1 2 1 0 1 0 2

3 1 1 3 1 1 1 1 3

Now, we are going to represent quadruple XNOR gate using the New Quadruple Universal Gate



P6, P7, P8 and negative SLMs P3, P4 constitute the 1st New Quadruple Universal Gate (denoted as block

1 in Figure 12), whose first input X (X1, X2) is fed through the positive SLMs P1 and P2 and the other

input Y (Y1, Y2) is fed through positive SLMs P7 and P8 to produce the output F1= .







(denoted as block 2 in Figure 12), whose first input Y (Y1, Y2) is fed through the positive SLMs P9 and

P10 and the other input X (X1, X2) is fed through positive SLMs P15 and P16 to produce the output F2=

.


P18, P21, P22, P23, P24 and negative SLMs P19, P20 constitute the 3rd


(denoted as block 3 in Figure 12), whose first input (output from the first New Quadruple Universal

Gate ) is fed through the positive SLMs P17 and P18 and the other input 3 (1, 1) is fed through positive

SLMs P23 and P24 to produce the output F3 = .


P26, P29, P30, P31, P32 and negative SLMs P27, P28 constitute the 4th


(denoted as block 4 in Figure 12), whose first input (output from the second New Quadruple

Universal Gate ) is fed through the positive SLMs P25 and P26 and the other input (output from the

third New Quadruple Universal Gate ) is fed through positive SLMs P31 and P32 to produce the final

output F4= ).

Figure 13. Optical Quadruple XNOR gate using New Quadruple Universal Gate




The light output from the laser source after being polarized at an angle 45 degrees with respect to



another beam splitter BS10. BS2 again splits the ray into two directions: one is incident on the next beam

splitter BS3 and the other part of the beam is incident on the mirror M18 to provide light for the operation

of the third universal gate. BS3 again splits the ray into two directions: one of which is incident on the

next beam splitter BS4 to provide light for the operation of the universal gate and other part of the beam

is incident on the mirror M9 to provide light for the second universal gate. The input X (X1, X2) is fed

through the positive SLMs P1 and P2 respectively. The other input of this first universal gate Y (Y1, Y2)

is fed through the positive SLMs P7 and P8 respectively. The output of this gate is fed to the savart plate

S11 along with O/E convertors C5 and C6 to provide one of the electrical inputs to the third universal gate

through the positive SLMs P17 and P18 respectively. The input Y is also given to the second universal

gate through the positive SLMs P9 and P10 respectively and X is also given to this gate through the

positive SLMs P15 and P16 respectively. The output of this gate is fed to the savart plate S22 along with

O/E convertors C11 and C12 to provide one of the electrical inputs to the fourth universal gate through the

positive SLMs P25 and P26 respectively. The other input of third universal gate is 3(1,1) that is fed

through the positive SLMs P23 and P24. . The output of this third universal gate is fed to the savart plate

S39 along with O/E convertors C17 and C18 to provide the other electrical input to the fourth universal

gate through the positive SLMs P31 and P32 respectively. The output from this 4th universal gate provides

the final output.

Let us consider a case, when the inputs are X= 1(X1 = 0, X2 = 1) and Y= 2 (Y1 = 1, Y2 = 0)

respectively. The positive SLMs P1 and P2 are controlled by the inputs X1 and X2. Thus P1 will block the

horizontally polarized light from S1 and P2 allow the vertically polarized light. Thus the vertically

polarized light from S2 is fed to the next savart plate S3 along with the O/E convertors C1 and C2. C1 will

produce zero output voltage and C2 will produce high voltage output that is fed to the negative SLMs P3

and P4 respectively. Thus P3 will allow the horizontal light component incident from the savart plate S4

and P4 will block the vertically polarized light. As a result the horizontally polarized light from S5 is fed

to S6 along with the O/E convertors C3 and C4. C3 will produce high voltage and C4 will produce zero

voltage which is fed to the positive SLMs P5 and P6 respectively. Thus P5 will allow the horizontally

polarized light incident from S7 and P6 will block the vertically polarized light. Thus only the

horizontally polarized light is fed to the savart plate S9 from S8. The positive SLMs P7 and P8 are

controlled by Y1 and Y2 respectively. Thus horizontally polarized light will be passed through the

positive SLM P7 and it is fed to the next savart plate S11 along with the O/E convertors C5 and C6. C5 -

produces high output voltage and C6 produces zero output voltage that is fed to positive SLMs P17 and

P18 respectively. Now, the positive SLMs P9 and P10 are controlled by the inputs Y1 and Y2. Thus P9 will

allow the horizontally polarized light incident from the savart plate S12 and P10 block the vertically

polarized light. Thus the output from the Savart plate S13 consists of only the horizontally polarized light

which is fed to the next savart plate S14 along with the O/E convertors C7 and C8. C1 will produce high

output voltage and C2 will produce zero voltage output that is fed to the negative SLMs P11 and P12

respectively. Thus P11 will block the horizontal light component incident from the savart plate S15 and

P12 will allow the vertically polarized light. Thus the output from the savart plate S16 consists of only the

vertically polarized light which is then fed to S17 along with the O/E convertors C9 and C10. Thus C9 will

produce zero voltage and C10 will produce high voltage that is fed to the positive SLMs P13 and P14

respectively. Thus P13 will block the horizontally polarized light incident from S18 and P14 will allow the

vertically polarized light. Thus only the vertically polarized light is fed to the savart plate S20 from S19.

The positive SLMs P7 and P8 are controlled by X1 and X2 respectively. Thus vertically polarized light

will be passed through the positive SLM P16. It is fed to the next savart plate S22 along with the O/E




convertors C11 and C12. C11 produces zero output voltage and C12 produces high output voltage that is

fed to positive SLMs P25 and P26 respectively. Since, P17 and P18 are controlled by the output from C5

and C6, P17 will allow the horizontally polarized light from S23 and P18 will block the vertically polarized

light. Thus only the horizontally polarized light is incident on S25 along with the O/E convertors C13 and

C14 from S24. C13 will produce high voltage output and C14 will produce zero voltage that is fed to the

negative SLMs P19 and P20. As a result P19 will block the horizontal light component from S26 and P20

will allow the vertical light component. Thus only this vertical light component is passed from the S27 to

S28 along with O/E convertors C15 and C16. Since C15 produces zero output voltage and C16 produces

high output voltage which is fed to the positive SLMs P21 and P22 respectively, P21 will block the

horizontally polarized light incident from the savart plate S29 and P22 will allow the vertically polarized

light. Thus only this vertically polarized light is passed to the savart plate S31 from S32. Since both the

positive SLMs P23 and P24 receive high voltage input, it will allow the incoming vertically polarized light

to pass through it. It is fed to the Savart plate S39 with O/E convertors C17 and C18 from S32. C17 produces

zero voltage and C18 produces high voltage output that are then fed to the positive SLMs P31 and P32.

Subsequently P25 will block the horizontally polarized light incident from the savart plate S33 and P26

will allow the vertically polarized light. This vertically polarized light is incident on the savart plateS35

along with the O/E convertors C19 and C20 from S34. C19 will produce zero output voltage and C20 will

produce high voltage output that is fed to the negative SLMs P27 and P28 respectively. Thus P27 will

allow the horizontal light component incident from the savart plate S36 and P28 will block the vertically

polarized light. It is fed to the savart plate S38 along with the O/E convertors C21 and C22 from S37. C21

will produce high voltage output and C22 will produce zero voltage output that is fed to the positive

SLMs P29 and P30 respectively. Thus P29 will allow the horizontally polarized light incident from the

savart plate S40 and P30 will block the vertically polarized light. Thus only this horizontally polarized

light is fed to the savart plate S42 from S41. Since positive SLMs P31 receives zero voltage input and P32

receives high voltage input, P31 blocks the only incoming horizontal light component. No light

component is incident on the savart plate S43. Thus no light is present at the final output i.e.F4= 0 (F41 = 0

and F42 = 0). Hence the output from the Table 4 for the inputs X=1 and Y=2 is verified.

For the inputs X=0 (X1= 0, X2= 0) and Y=1(Y1=0, Y2=1), the final output consists of only horizontally

polarized light, leading to F4= 2 (F41= 1 and F42= 0).

For the inputs X=1 (X1= 0, X2= 1) and Y=3 (Y1=1, Y2=1), the final output consists of only vertically

polarized light i.e. F4= 1(F41= 0, F42= 1).

For the inputs X=2 (X1= 1, X2= 0) and Y=3 (Y1=1, Y2=1), the final output consists of only horizontally

polarized light i.e. F4= 2 (F41= 1 and F42= 0).

In the similar way, for the other different combinations of inputs of X and Y, the results can be

explained according to the Table 4.

3.7 Implementation of Quadruple XOR Gate

Quadruple XOR gate using the new quadruple universal gate is shown in the Figure 14. It is the

combination of XNOR gate followed by XOR gate. Here, fifth new quadruple universal gates are used

to design the Quadruple XOR gate where „1‟ represents the first block corresponding to the 1st new

quadruple universal gate, „2‟ represents the second block corresponding to the 2nd

new quadruple

universal gate, „3‟ represents the third block corresponding to the 3rd

new quadruple universal gate, „4‟

represents the fourth block corresponding to the 4th

new quadruple universal gate and „5‟ represents the

fifth block corresponding to the 5th


We are considering that X (X1,X2) is fed as the first input and Y(Y1,Y2) as the second input to

the first block which produces the output F1 = . Again in the second block Y is fed as the first input

and X is fed as the second input that produces the output F2 = The output of the first block is fed as




the first input of the third block whose second input is 3(1,1) and it produces a output of F3. The output

of the second block is fed as the first input of the fourth block. The output F3 is again fed to the second

input of the fourth block that produces the output F4. This output is fed as the first input to the fifth

block. The other input of this block is 3 and it produces the output F5 = ( + ). Similarly, XOR

gate can be implemented optically using SLM and savart plate.

Figure 14. Block diagram of Quadruple XOR gate using New Quadruple Universal Gate

The truth table for the Quadruple XOR gate for all the possible combinations of the input X and

Y is shown in the Table 5.

Table 5. Truth table of Quadruple XOR gate using New Quadruple Universal Gate INPUTS OUTPUT

X X1 X2 Y Y1 Y2 F51 F52 F5

0 0 0 0 0 0 0 0 0

0 0 0 1 0 1 0 1 1

0 0 0 2 1 0 1 0 2

0 0 0 3 1 1 1 1 3

1 0 1 0 0 0 0 1 1

1 0 1 1 0 1 0 0 0

1 0 1 2 1 0 1 1 3

1 0 1 3 1 1 1 0 2

2 1 0 0 0 0 1 0 2

2 1 0 1 0 1 1 1 3

2 1 0 2 1 0 0 0 0

2 1 0 3 1 1 0 1 1

3 1 1 0 0 0 1 1 3

3 1 1 1 0 1 1 0 2

3 1 1 2 1 0 0 1 1

3 1 1 3 1 1 0 0 0

IV. SIMULATION RESULTS OF THE DESIGNED GATES

The vertical axis in Figure 15(a) to 15(i) indicates power in dB, while horizontal axis represents

time scale in ps. The timing instant for the occurrence of bit pattern is at 1,3,5,7 ps. Upper first two set

waveforms indicate the input bit sequences, 0011 and 0101 for the input variables X and Y respectively.

The other waveforms indicate the outputs of all basic logic gates.




V. CONCLUSION

In this paper, we have proposed and implemented optical new quadruple universal gate (QUG)

along with the realization of the other optical basic logic gates such as NOT, AND, OR, NAND, NOR,

XNOR and XOR gates using this QUG. The functionality of those designed gates is verified using

simulation result. The available two universal gates NAND and NOR are highly effective in binary

domain. This new optical quadruple universal gate provides increased efficiency, less noise and

utilization of high space bandwidth along with faster and improved operation. It also facilitates high

parallel computing capability and helps in the designing of the dynamically reconfigurable and scalable

larger topologies. It also has wide range of applications in complex combinational, sequential circuits as

well as in communication fields and optical computational circuitry.




REFERENCES

[1] A. W. Lohmann, “Polarization and optical logic”, Appl. Opt. vol. 25,pp. 1594-1597, 1986.

[2] A. Avizienis, “Signed-Digit Number Representation for Fast Parallel Arithmetic”, IRE Trans. Electron. & Comp, vol.

10, pp. 389-400, 1961.

[3] B. L. Drake, R. P. Bocker, M. E. Lasher, R. H. Patterson, W. J.Miceli, “ Photonic computing using the modified-

signed-digit number representation”, Opt. Eng., vol. 25, pp. 38-43, 1986.

[4] B. L. Drake, R. P. Bocker, M. E.Lasher, T. B. Henderson, “Modified signed-digit addition and subtraction using

optical symbolic substitution”, Appl. Opt., vol. 25(15), pp. 2456-2457, 1986.

[5] A. K.Cherri, , M. A. Karim, “Modified signed digit arithmetic using an efficient symbolic substitution”, Appl. Opt.,

vol.27(18), pp. 3824-3827, 1988.

[6] A. K. Datta, A. Basuray, S. Mukhopadhyay, “Arithmetic operations in optical computations using a modified trinary

number system”, Optics Letters, vol.14, pp. 426-428, 1989.

[7] A. K. Ghosh, P. Pal. Choudhury, A. Basuray, “Modified Trinary Optical Logic Gates and their Applications in

Optical Computation”, Third International Conference on CISSE 2007, IEEE, University of Bridgeport, 3-12 December

2007 (2007) and published in the proceeding on Innovations and Advanced Techniques in Systems, Computing

Sciences and Software, Springer, pp. 87-92, 2008.

[8] A. K. Ghosh, A. Basuray, “Binary to Modified Trinary Number System Conversion and Vice-Versa for Optical Super

Computing. Natural Computing”, Vol. 9(4), pp.917-934, 2009.

[9] J. Lukasiewicz, “O logice trojwartosciowej”, Ruch Filozoficny, vol. 5, pp. 169-171, 1920.

[10] A. K. Ghosh, A. Bhattacharya, M. Raul, A. Basuray, “ Trinary Arithmetic and Logic unit (TALU) using savart plate

and spatial light modulator (SLM) suitable for optical computation in multivalued logic”, Optics & Laser

Technology, vol. 44(5), pp. 1583-1592, 2012.

[11] A. K. Ghosh, A. Bhattacharya, A. Basuray, “Quadruple Valued Logic System Using Savart Plate and Spatial

Light Modulator (SLM) and It's Applications”, Journal of Computational Electronics, vol. 11(4), pp. 405- 413, 2012.

[12] A. Bhattacharya, A. K. Ghosh, “Encoder, Decoder, Multiplexer and Demultiplexer in Quadruple-Valued Logic System

Using Savart Plate and Spatial Light Modulator (SLM)”, International Journal of Modern Trends in Engineering and

Research (IJMTER), vol. 02(08), pp. 31-43, 2015.

[13] X. Ye, P. Ye, M. Zhang, “All‐optical NAND gate using integrated SOA‐based Mach–Zehnder interferometer”, Optical

Fiber Technology, vol.12(4), pp.312–16, 2006.

[14] A. K. Mandal, G.K. Maity, “The all‐optical reversible new universal gate using Mach‐ Zehnder interferometer”,

International Journal of Science, Engineering and Technology, vol. 2(4), pp. 207-232, 2014.

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OPTICAL NEW QUADRUPLE UNIVERSAL GATE (QUG) USING SLM …