Opportunities for Gigascale Integration in Three Dimensional Architectures James Joyner, Payman Zarkesh-Ha, Jeffrey Davis, and James Meindl Microelectronics

Opportunities for Gigascale Integration in Three Dimensional Architectures

James Joyner, Payman Zarkesh-Ha, Jeffrey Davis, and James Meindl

Microelectronics Research CenterGeorgia Institute of Technology

SLIP Workshop 20009 April 2000

Supported by DARPA and SRC

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Outline

• Motivation• 3D Architecture Concepts• Derivation of 3D Model• Results of Model• Optimization of Interconnects• Wiring Density Limitations• Conclusions

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Motivation

• 10% of Interconnects = 80% of Wire Length.• KEEP INTERCONNECTS SHORT!!

0

0.2

0.4

0.6

0.8

1

1.2

1 10 100 1000 10000

Length in Gate Pitches

Per

cen

tag

e o

f C

um

ula

tive

Total Interconnects

Total Length

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Motivation

• Each gate has more neighboring gates.

2D 3D

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Motivation

• Reduction of gate pitch due to smaller wire-limited area.

2D 3D

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Outline


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3D Architecture Concepts

• Stratum - A layer of transistors with its tiers of interconnects.

• Tier - A pair of orthogonal metal levels with equal pitch.

Stratum 1

Stratum 2

Tier 2

Tier 1

Tier 2

Tier 1

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• Stratal- to gate- pitch ratio r.

Stratum 1

Stratum 2g

s

p

pr sp

gp

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Importance of r• Height of metal stack is at least as

great as the gate pitch (r > 1).• Substrate thickness for mechanical

stability.• Thermal/electrical insulation of strata.• r affects the probability of running an

interconnect vertically.

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• Gate pair – two gates separated by a given manhattan length.

• Length in manhattan geometry.

4121

zyx llll

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Outline


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Derivation of 3D Model

• Need two values.– Number of expected interconnects

between a gate pair (probability of occupation).• Use Rent’s Rule.

– Number of gate pairs (density of states).• Use discrete convolution.

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Number of Expected Interconnects• Expression from Rent’s Rule.

A B C

B B

B

B

B

C

C

C

C

C

A B B C

2D

1D

pkNNNfi CBA ,,,,exp

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• Manhattan sphere instead of circles.

1 2

2

2

2

3

3

3

3

3

33

3

4

4

4

4

4

4

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• Edge effects.Horizontal

1 2

2

2

2

3

3

3

3

3

33

3

4

4

4

4

4

4

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• Edge effects.Vertical

3

3

3

3

3

33

3

4

4

4

4

4

4

1 2

2

2

2

3 3

3

3

3

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• Use of averaging to avoid both horizontal and vertical edge effects.

• A function for the number of starting gates must be defined.

lm

lmlN

s

tB

1

1

l

kBC kNlN

Number ofGate Pairs

Number ofStarting Gates

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• Starting gate – a gate that can serve as the NA of a gate pair for a given length.

X

X

X

X X

X

X

X

X

1D

2D X

X

X

X

X

Length = 5

X

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Outline


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Comparison with 2D

1.0E-02

1.0E-01

1.0E+00

1.0E+01

1.0E+02

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04


Inte

rco

nn

ec

t D

en

sit

y F

un

cti

on

3D Model

Davis Model

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Variable r

1.0E-02

1.0E-01

1.0E+00

1.0E+01

1.0E+02

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04


Inte

rco

nn

ect

Den

sity

Fu

nct

ion

r = 1

r = 50

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Variable Strata

1.0E-02

1.0E-01

1.0E+00

1.0E+01

1.0E+02

1.0E+03

1.0E+04

1.0E+05

1.0E+06

1.0E+07

1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04


Inte

rco

nn

ect

Den

sity

Fu

nct

ion

16 Strata4 Strata1 Stratum

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Wire Demand

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.0E+00 1.0E+01 1.0E+02 1.0E+03 1.0E+04


Per

cen

tag

e o

f C

um

ula

tive

Total InterconnectsTotal Length S=1Total Length S=4Total Length S=16

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Outline


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Optimization

Ln-1

Interconnect Distribution

1,2 nnt

mnmw LLDN

ApAe

2

2int1.14

nt

m

n

or

c

LN

A

p

c

f

Area Required

Delay Equation

•Solve equations simultaneously.•pn is pitch required such that wire length Ln meets delay.•Ln is limited by the available area for a tier and the pitch.

Ln

Dn

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Optimization

2

4

6

8

10

12

14

16

0 0.5 1 1.5

Area (cm^2)

Nu

mb

er

of

Meta

l L

evel 1 Stratum

2 Strata

4 Strata

2

4

6

8

10

12

14

16

0 0.5 1 1.5

Area (cm^2)

Nu

mb

er o

f M

etal

Lev

el

1 Stratum

2 Strata

4 Strata

Metal Levels Wire-Limited Area

•50% reduction in metal levels•39% reduction in area

•92% reduction in area

950 MHz

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Optimization

6

7

8

9

10

11

12

13

14

15

16

0 0.5 1 1.5 2

Area (cm^2)

Nu

mb

er

of

Meta

l L

evels

1 Stratum - 325 MHz

2 Strata - 1.25 GHz

4 Strata - 4.75 GHz

•14x increase in clock frequency•63% reduction in area

Wire-Limited Clock Frequency

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Outline


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Limitations

Pad - Stratum 1

Pad - Stratum 2

AlignmentTolerance

Cross-section

Vertical Wiring Density

• Vertical interconnect pitch must be greater than alignment tolerance.

• Demonstrated alignment tolerance : 3 microns.

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Limitations

•Restrictions placed by density of vertical interconnects may require increased area.

•For frequency optimization, required alignment tolerance is 0.34 microns.

•Via aspect ratio may also add limitations on vertical wiring density.

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Outline


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Conclusions

• A new model has been derived for interconnect distributions in 2D and 3D architectures.

• 14x increase in wire-limited clock frequency,• 92% reduction in wire-limited area,• or 50 % reduction in metal levels for 3D system.• Restrictions on vertical interconnect density may

compromise the advantages of 3D architectures.

Documents

Opportunities for Gigascale Integration in Three Dimensional Architectures James Joyner, Payman Zarkesh-Ha, Jeffrey Davis, and James Meindl Microelectronics