OPERATION MANUAL

for the

NCAR PIRAC

P/C INTEGRATED RADAR ACQUISITION

BOARD

Note: This manual is currently under revision by Charlie Martin. The changes are not complete and have not been proofed. Read this document with a healthy dose of skepticism.

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2

Table of Contents Introduction....................................................................................................................................5

PCI Interface ................................................................................................................................11

PCI Memory Map ....................................................................................................................11

PCI Bus Bandwidth..................................................................................................................12

Interrupts ..................................................................................................................................13

Digital IF Section.........................................................................................................................13

Phase Locked Loop settings ....................................................................................................13

Timer/Trigger Section..................................................................................................................13

Timer Programming.................................................................................................................15

Waveform Generator ...................................................................................................................18

BYTE 0 ....................................................................................................................................18

BYTE 1 ....................................................................................................................................18

BYTE 2 ....................................................................................................................................18

BYTE 3 ....................................................................................................................................18

Status/Control Register ................................................................................................................20

LOW BYTE .............................................................................................................................20

HIGH BYTE ............................................................................................................................20

DSP Section .................................................................................................................................22

Reset.........................................................................................................................................22

COM Ports ...............................................................................................................................22

DSP Memory Map ...................................................................................................................22

DSP Interrupts..........................................................................................................................24

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DSP Register Map ...................................................................................................................24

Initialization .............................................................................................................................25

IIF Output Table ......................................................................................................................26

Programming the FIFOS..........................................................................................................27

Connectors ...................................................................................................................................28

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Introduction

The PIRAQ (P/C INTEGRATED RADAR AQUISITION) is a multi-function PCI bus board that can serve as a major component in a radar or lidar receiver/signal processor. The PIRAQ contains:

• An IF digitizer and downconvertor

• A programmable digital matched filter

• A dual DSP section

• A multi-function timer and trigger generator

• A programmable waveform and sample control lookup table capable of generating a complex waveform, sample clock, and an arbitrary modulation or test pulse.

Figure 1 provides an overview of the main functions on PIRAQ. The Timing section produces a trigger that causes the waveform generator to run. The generator is a clocked memory, with various bits used to generate specific timing signals.

The IF section implements quadrature down conversion, sampling and accumulation of the IF input. The Waveform MAC OE signal controls the accumulation period of the IF A/D. The WREN signals are used to control the transfer of the I and Q sums to the DSP FIFOs.

Once data have been written to the FIFOS, the processing of the samples proceeds asynchronously, as the DSPs process the data from the FIFOs. Each DSP has 2 MB of RAM in which to hold intermediate results. Final results from the DSPs are transferred to the PC host through the dual ported RAM areas on the PCI interface.

The PCI interface provides memory mapped registers for communication and control between the host PC and PIRAQ. The Wwaveform memory is accessed directly via dual ported ram, as are the counter registers in the Timing section. A small dual ported ram is provided for each DSP to use for communication with the host. A status/control register provides functions for configuring PIRAQ and running the DSPs.

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Digital IF, A/D,

Accumulators

Waveform generator,

DAC

DSP 0

Timing/ Trigger

PCI Interface

DSP 1

FIFOS FIFOS

MAC OE

WREN1

WREN0

RA

M T

P

TRIG

GE

R

TTL / 8

48MHz 0 - 5 V

60 MHz IF In

Trigger In

TP Out

2MB RAM 2MB RAM

64KB DPRAM

64KB DPRAM

Status/Control Register

Timer Counters

REF In

LO Out

Wave Table DPRAM

Figure 1. PIRAQ Functional Sections

6

8

PCI

Buffers

~~~~ ~~~~ ~~~~

PLL

PCI Bus

RAM Controller

RAM

Quad Conv.

Timer 2

Timer 1

I MAC

Q MAC

DSP 0

DSP 1

I FIFO

DPRAM

Status/ Control

Register

Trigger/ Timer/

TP Machine

DRV

Trigger Det.

Q FIFO

I FIFO

Q FIFO

DPRAM

~~~~ ~~~~ ~~~~

stop rewind

fi fo0 wren

fi fo1 wren

RAM RAM COM COM

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14 40/48 MHz

40/48 MHz

DC DAC OUT

AC DAC OUT

TRIG IN

TP/MOD

REF IN

LO OUT

IF B

IF A 12 MHz

SLOW DAC

RF Switch Gain ACC OE

Sampled at 48 MHz

A/D

D/A

D/A

COM COM

Figure 2. PIRAQ Block Diagram

TMODE

Gate01

Pulses

or

Trigger In

Even (02) Odd (01)

Trigger

TP Width (12)

TP Delay (11) TP Delay (11)

Sync (00)

Delay (10)Delay (10) Delay (10)

TP Width (12)

TP Out

Gate02

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PCI Interface The PCI specification allows a card to define up to six regions on the interface that are mapped into the host bus memory or I/O space. The mapping is performed by the boot firmware, and is completed before the operating system is running. Applications will then query the PCI interface to determine where the regions have been mapped. In the same manner, interrupt request lines are dynamically assigned, and then read from the interface by later code.

The Piraq PCI interface is implemented with the AMCC S5930 PCI chip. This interface provides a “slave” or “target” PCI interface only, and so Piraq is not capable of bus mastering.

PCI Memory Map1

Description Address Offset From PCI Base

PCI Addressing Modes

Memory Size

(bytes)

PCI memory region

8 16 32

DSP 1 Dual Port RAM 0x80000 - 0x8FFFF Y Y Y 64K 1

DSP 2 Dual Port RAM 0x90000 - 0x9FFFF Y Y Y 64K 1

Counter 0 0xA0000 - 0xA0006 (even)

Y 2

Counter 1 0xA0008 - 0xA000E (even)

Y 2

Addon Interrupt Clear 2

Waveform Table 0x00000 - 0x3FFFF ? ? Y 512K 3

Status/Control Register 0xA0010 Y Y 4

1 Check out these PCI region assignments

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Description Address Offset From PCI Base

PCI Addressing Modes

Memory Size

(bytes)

PCI memory region

8 16 32

Aliased Memory2 ?????? - ??????

PCI Bus Bandwidth In the PCI environment, a “bus mastering” device can gain control of the PCI bus, and write data into other memory regions on the bus. Bus mastering is therefore used to provide a device controlled DMA function, relieving the host processor of the need to spend it’s cycles reading data from a device. Conversely, as in the Piraq case, a slave device is not capable of bus mastering. The host processor must issue reads across the PCI bus to fetch data from the device memory which is mapped in the PCI address space. The net result is that the host CPU can only execute data reads within a loop as fast as the PCI bus can transfer data from the device.

It turns out that the effective transfer rate can be surprisingly slow. In tests made with Piraq, the maximum sustainable rate varied between 4 and 11 MB/s. The tests were made on half a dozen different systems, each of which had 33 MHz PCI busses. Significantly, the two multiprocessor systems tested were also the ones that had the slow transfer rates. Oscilloscope observations of control signals on the Piraq cards verified that the PCI burst mode is operational. It is not clear why the slave mode of operation should show such poor performance.

At first blush, this does not seem like an overly restrictive limitation. However, if significant amounts of data are being transferred from multiple Piraq cards on the same PCI bus, a significant system slowdown can be observed. For instance, if each card is supply 256KB/s, then the aggregate bandwidth is 1MB/s. The data transfers will be driven by tight read loops in the interrupt service routine. During the data reads, the CPU cannot be doing anything else, and thus on the slower systems the CPU will be tied up for 25% of the time just reading data from the PCI bus. Interrupts are disabled while the reads are taking place, and system response can become noticeably sluggish3.

The next generation of Piraq will use a PCI interface chip that supports bus mastering. In this case, the CPU need not issue data reads at all, and this situation will not occur.

2 What is he talking about here?

3 Perhaps it would be possible to queue the data reads to take place outside of the interrupt context. In initial attempts to do this under Linux, I was not able to get this to work.

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Interrupts The IIOF1 general purpose I/O lines from each Piraq DSP are OR’ed together; this in turn is provided as input to the 5930 Addon interrupt signal. The logic that implements the OR also latches these signals. Either DSP can thus signal a PCI interrupt by pulsing high the IIOF1 line.

The PCI interrupt request line will remain high until the Addon is cleared by the host software. Addon is cleared by a write to the PCI memory location allocated for this purpose.

Implementing an interrupt that remains high allows for level triggered interrupts, which in turn permits interrupts to be shared in PCI systems. When an interrupt is triggered, every service routine that shares the interrupt is called in succession. The first thing the routine does is to poll its associated device to determine if it requested an interrupt. If one was requested, the routine services the device.

The PCI interface must be specifically enabled to generate interrupts. The 5930 has multiple facilities for generating PCI interrupts, and the manual should be consulted for details on how to enable the Addon interrupt.

Since either DSP can generate an interrupt, some sort of scheme must be implemented to allow which DSP, or perhaps both of them, are asserting the PCI interrupt.

Digital IF Section

Phase Locked Loop settings The phase locked loop is set by sending three wire serial data to the PLL chip, through

the status/control register (one bit at a time). (See National Semiconductor LMX2301 data sheet for programming details). For 60 MHz IF input, the onboard oscillator is locked to 48 MHz. For 30 MHz IF input, the onboard oscillator is locked to 40 MHz. The PLL programmable dividers should be set to produce a 1 MHz reference signal.

Timer/Trigger Section The counters and associated PAL generate the two timing signals: TRIGGER and TPOUT. TRIGGER causes the waveform generator to run. TPOUT is an arbitrary signal brought to connector J1.

Three modes of operation are defined for the timer section. The TMODE and TRESET bits of the status/control register are used to configure the modes.

Mode Behavior Initialization

Single cycle, external The timing cycle is executed once Initialize TMODE=1, TRESET=0.

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Mode Behavior Initialization

trigger in response to an external trigger. After TRESET is raised, the timing cycle will run once after each external trigger.

Continuous, external trigger

The timing cycle is started by an external trigger, and then run continuously.

Initialize TMODE=0, TRESET=0. After TRESET is raised, the timing cycle will run repeatedly after the first external trigger.

Continuous, software trigger

The timing cycle is started under software control, and then run continuously.

Initialize TMODE=0, TRESET=0. Raise TRESET, and then raise TMODE to start a repeating timing cycle.

Table 1

Figure 3 shows the basic timing relationships. The external trigger pulse will start the sync timer. The sync timer then starts the even PRT timer. Alternatively, a rising TMODE can start the even PRT timer. Note that the sync timer has no effect for software (i.e. TMODE rising) initiated control.

After the even timer completes, an "even" pulse is generated and the odd PRT timer begins. After the odd PRT timer completes, an "odd" pulse is generated. If the continuous running mode is selected, the odd pulse will restart the even timer.

The even and odd pulses are combined, and the "delay" timer is added to them. Following this delay, the waveform generator trigger is produced. Note that either the even or odd pulses, or both, may be used to generate TRIGGER. Selection is made via the EVEN TRIG and ODD TRIG bits of the status control register.

The test pulse output can be generated from either or both of the odd and even pulses. A delay can be applied with the test pulse timer, and the test pulse width is set via the test pulse width timer. Selection of the odd, even or both pulses for input to the test pulse is made using the ODD TP and EVEN TP bits of the status/control register.

The timer section contains logic that allows selection between the timer and the waveform generated test pulse. The TPSOURCE bit in the status/control register will choose which signal is sent to the BTPOUT pin on J1. Coincidently, this can be used to disable the output of the waveform test pulse while the waveform table is being programmed. Note also that that the waveform test pulse is brought directly to another pin on J1, so that the timer and waveform test pulses can be used concurrently.

Below is a description of the values that must be programmed into the counters to give proper

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operation.

Timer #

Counter #

Parameter Timer Mode

Value

0 0 Sync 5

0 1 Even prt 5 P1 = (EVENPRT * 8E6) - 1

0 2

PRF and

Sync Delay Odd prt 5 P2 = (ODDPRT * 8E6) - 3

1 0 Trigger delay

5 A = | DELAY * 8E6 |

1 1 Test pulse delay

5 TPD = TPDELAY * 8E6

1 2

Waveform Trigger and Test

Pulse Test pulse width

1 TPWIDTH * 8E6

Timer Programming The timers are implemented with 82C54 programmable timer chips. Each chip contains three independent timers.

Each timer has independent clock and trigger inputs, and may be configured for a particular mode of operation. Only two modes are used in Piraq:

• Mode 1: Hardware retriggerable one-shot: The trigger generates a pulse of the specified length.

• Mode 5: Hardware retriggerable strobe. The trigger initiates a time countdown, followed by a single cycle pulse.

The TPWIDTH counter in Piraq is programmed for mode 1; all other counters are programmed for mode 5.

Each timer chip responds to four successive addresses, starting at the chip’s base address. The base address + 3 accesses the control register for the chip, and the previous three addresses correspond to each timer. Each value written to the control register will specify one of the timers, and will set the timer mode and the counter load mode.

The counter load mode specifies which of the MSB or LSB bytes will be loaded, or if both are to

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be loaded in successive writes to the timer address. The simplest programming technique would appear to be the following, which specifies that both bytes of the timer counters will be programmed with successive writes:

Write the control word to the timer address + 3: (timer number << 6) + (3 << 4) + (mode << 1)

Write the LSB to (timer address + timer number)

Write the MSB to (timer address + timer number).

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SYNC00

G Q

Q

QS E T

CLR

D

L

Q

QS E T

CLR

S

R

Q

QS E T

CL R

D

Q

Q S E T

CLR

D

ODD02

G Q

TPDELAY11

G QW IDTH

12G Q

DELAY10

G Q

EVEN01

G Q

Q

QS E T

CLR

D

Q

QSE T

CLR

D PULSES

PULSES

PULSES

ODDEVEN

ODDEVEN

ODD

ODD EVEN

EVEN

ODD EVEN

PULSES

ODDEVEN

APULSEDPULSE

DDPULSE

EOPULSE

1/324 M Hz CLOCK

CLK_SEL

TRESET

TRESET

TRESET

TRESET

TRESET

TRESET

TM ODE

TRIGIN

RFTRIGEN

RFTRIG

TRIGGER

TPOUT

TP_SEL

RAM _TP

CLOCK

CLOCK

CLOCK

CLOCK

CLOCK

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Waveform Generator

BYTE 0 7 6 5 4 3 2 1 0

DAC D7

DAC D6

DAC D5

DAC D4

DAC D3

DAC D2

DAC D1

DAC D0

BYTE 1 15 14 13 12 11 10 9 8

MAC OE MAC ACC

DAC D13

DAC D12

DAC D11

DAC D10

DAC D9

DAC D8

BYTE 2 23 22 21 20 19 18 17 16

RAM TP RF SWITCH

FIFO2 WREN

FIFO1 WREN

REWIND STOP GAIN1 GAIN0

BYTE 3 31 30 29 28 27 26 25 24

DO 7 DO 6 DO 5 DO 4 DO 3 DO 2 DO 1 DO 0

• BITS 0 - 13: These bits form the arbitrary waveform data word for the output DAC. The DAC output is AC coupled. A binary value of 2000h is mid scale (0V). A binary value of 3FFFh is plus full scale (1V) and a value of 0000h is minus full scale (-1V). The output data rate is either 48 MHz or 40 MHz depending on the operation mode (LO frequency controlled by the PLL). 40 MHz is selected for use with a 30 MHz IF while 48 MHz is selected for use with a 60 MHz IF.

• BIT 14: This bit controls the multiplier-accumulator (MAC) accumulate signal. When this bit is high, the MAC accumulates the raw I or Q into the overall sum. When this bit is low, the MAC load the next I or Q into the accumulator essentially starting a new sum. This sets the gate spacing by allowing the accumulator to sum a defined number of raw samples.

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The MAC samples this bit only on odd addresses with a latency of 3 counts.

• BIT 15: This bit controls the output enable of the MAC. When this bit is low, the MAC data will appear on the FIFO inputs. When this bit is high, the EOF word (set by pull up resistors on the FIFO bus) will appear on the FIFO inputs. There will be a delay between when this bit goes high to when the pull up resistors set the EOF value. This feature allows the insertion of an EOF word at the end of a group of samples. Another alternative EOF character can be set using the gain bits described below. This has the advantage that there is no delay. The MAC samples this bit only on odd addresses with a latency of 2 counts.

• BIT 16 - 17: These bits form a multiplier with the raw I - Q samples, effectively controlling the MAC gain. The GAIN0 bit has a weight of 0.5 and the GAIN1 bit has a weight of 1. These bits allow the normalization of range gates when the spacing (number of points in the accumulator sum) varies with range. In addition, a gain of zero can be set to force the output to zero for testing or for inserting an EOF. The MAC samples these bits only on odd addresses with a latency of 2 counts.

• BIT 18: The stop bit stops the address counter. The address counter will not restart until the next input trigger (even and/or odd depending on the trigger setting). The address counter resumes at the last address or address zero depending on the state of the rewind bit. There is a letency of 2 counts on this bit.

• BIT 19: The rewind bit causes the next lookup table address to start over again at zero. There is a latency of 2 counts on this bit.

• BIT 20 - 21: These bits control the write enable line of the FIFO. When this bit is low I and Q data in the MAC accumulator will be written to the FIFOs. The MAC accumulator output always contains the most recent accumulation. Therefore, the FIFO WREN bits should only be asserted on the last accumulation of a given gate. These bits are sampled by the FIFO only on odd addresses, with a latency of 2 counts.

• BIT 22: The RF SWITCH bit controls the state of the input RF switch. A low on this line selects the input from channel A. A high selects channel B.

• BIT 23: The RAM TP bit is an arbitrary digital output which can be made available on a front panel connector. The status word contains a control bit which allows this output to be at the test pulse connector. This bit can be arbitrarily programmed and has an output sample rate of 40 or 48 Mhz depending on the operation mode.

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• BITS 24 - 31 Digital output to connector J11.

Status/Control Register

HIGH BYTE

15 14 13 12 11 10 9 8

PLL DATA

PLL LE PLL CLOCK

PHASE LOCK/

RFTRIGEN

PC LED RAM BUS

TP SOURCE

DELAY SIGN

LOW BYTE 7 6 5 4 3 2 1 0

ODD TP EVEN TP

ODD TRIG EVEN TRIG

TMODE TRESET FIFO INT SEL

DSP RESET

• BIT 0: DSP RESET This bit, when low, sets both DSP's into hardware reset. When high, the DSP's begin executing code at the bottom of dual port ram.

• BIT 1: FIFO INTERRUPT SELECT This bit determines which of two sources will interrupt the corresponding DSP's. When this bit is low, the DSP's will be interrupted when the associated FIFO reaches half full (4096 words). When this bit is set, the DSP's will be interrupted when the associated FIFO reaches the programmed depth (see programming procedure below).

• BIT 2: TRESET This bit is the reset line to the sample timer. A zero will put the timer in reset.

• BIT 3: TMODE This bit controls which mode the timer state machine is in. The timing state machine samples the bit, when the TRESET line goes high (comes out of reset). A one puts the timer into external trigger mode. After TMODE is sampled as a one when TRESET goes high, further changes in TMODE do nothing. When TMODE is sampled as zero when TRESET goes high, the timer state machine is set to continuous running mode with hardware or software start. After TMODE is sampled when the TRESET line bit high, the timer waits for an event. If an external source is connected to the TRIGGER input line on the front panel, a delay followed by continuous pulses will begin following a

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rising edge. In addition, the delay and subsequent pulses can also be initiated by raising the TMODE bit..

• BIT 4:EVEN TRIGGER If set, the even4 PRT pulse will generate a trigger for the waveform generator. The trigger will be delayed by the trigger delay counter.

• BIT 5: ODD TRIGGER If set, the odd PRT pulse will generate a trigger for the waveform generator. The trigger will be delayed by the trigger delay counter.

• BIT 6: EVEN PULSE ENABLE If set, the even PRT pulse will be used in the test pulse generation. The test pulse will be delayed by the test pulse delay count.

• BIT 7: ODD PULSE ENABLE If set, a test pulse will be generated for each odd PRT pulse. The test pulse will be delayed by the test pulse delay count.

• BIT 8: DELAY SIGN The delay sign bit essentially adjusts the sign of the delay between the PRT generator and the test pulse generator. When this bit is set the test pulse precedes the first gate. When this bit is clear, the first gate precedes the test pulse. In either case, timer 0 sets the delay.

• BIT 9: TP SOURCE This bit determines whether the timer generated test pulse, or the arbitrary RAM test pulse will appear at the test pulse connector. A high selects the RAM test pulse; a low selects the timer test pulse.

• BIT 10: RAM BUS This bit arbitrates the RAM's address and data bus. When this signal is low, the PCI host has access to the waveform RAM. When this bit is high, the RAM is inaccessible to the PCI host and is ready to clock it's data out to the DAC.

• BIT 11: PC LED The PC LED bit controls the state of LED 7 on the LED array. This is used for convenience to the programmer only.

• BIT 12: PHASE LOCK / RFTRIGEN When read, the phase lock bit indicates the status of the phase locked loop. Low indicates the loop is not locked. High indicates phase lock.

4 The first PRT is defined as the even PRT.

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When written, the bit enables (hi) the rf trigger control of the timing section. The signal on input B (J5) is sampled by the rf detector/trigger generator circuit, generating the RFTRIG signal. If RFTRIGEN is high, the timer section will use RFTRIG to start the IPP timers.

• BIT 13 - 15: PLL CONTROL SIGNALS These three bits are connected to the National Semiconductor LMX2301 phase locked loop chip three wire interface. The PCI host configures the PLL by creating a serial data stream using these lines.

DSP Section

Reset After the DSP is reset, via the DSP RESET bit of the status/control register, the DSP begins executing code from the beginning of the dual ported RAM.

COM Ports COM1 and COM4 are connected to COM4 and COM1 respectively of the other DSP. COM2 and COM5 are brought to headers on the PIRAQ card.

DSP Memory Map All data types in the DSP use 4 bytes, and all DSP addressing is based on 4-byte access, i.e. successive addresses refer to succeeding 4 byte words. The 'C44 has two memory buses, referred to as local and global. The busses function identically, but are separated so that the executable code may be accessed concurrently with data manipulations. This allows for substantial improvements in processing throughput. Given this design, it is advisable to run the DSP code directly out of the dual ported ram, rather than relocating it to the larger memory segment on the PIRAQ local bus. This means that the executable DSP code and the data transfer region (for transfers between the DSP and host) must be squeezed into the 64KB dual ported RAM region. (I guess that steps should be taken to locate the program stack on the local bus as well?).

In addition to the large local memory and the dual ported memory are several other functions that are accessed through the local or global memory maps. These functions are:

DESCRIPTION MEMORY BUS ADDRESS (Long Word)

Size (4-byte words)

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DESCRIPTION MEMORY BUS ADDRESS (Long Word)

Size (4-byte words)

LED 0 LOCAL 0x20000 1 bit

LED 1 LOCAL 0x20001 1 bit

FIFO SERIAL PORT LOCAL (DSP 1 only) 0x20002

12 bit DAC LOCAL (DSP 2 only) 0x20003

I FIFO READ GLOBAL 0x80040000 1

Q FIFO READ GLOBAL 0x80040001 1

FIFO RESET GLOBAL 0x80040002

64KB DUAL PORT RAM

GLOBAL 0x80000000 - 0x80003FFF

16K

2MB LOCAL SRAM LOCAL 0x00020000 - 0x0003FFFF

512K

23

DSP Interrupts The DSPs have four general purpose I/O-External Interrupt lines, two of which are used by PIRAQ as interrupt inputs. The other two are used as outputs to generate interrupts in other parts of the system. These are used as follows:

I/O line Name Direction Purpose

IIOF0 FIFO interrupt Input Generate an interrupt when the FIFOs are filled to a preset level.

IIOF1 PCI interrupt Output Trigger an interrupt on the PCI interface.

IIOF2 DSP21 interrupt Input Receive an interrupt from the other DSP.

IIOF3 DSP12 interrupt Output Trigger an interrupt on the other DSP.

Table 2

DSP Register Map

REGISTER HEX ADDRESS VALUE DESCRIPTION

GLOBAL CONTROL 100000 0x0F8B4000 Sets up strobes and wait states for global bus

LOCAL CONTROL 100004 0x103C0880

Sets up strobes and wait states for local bus

IIOF FLAG IIF 022B

IIOF0 <= FIFO INT

IIOF1 => VME INT

IIOF2 =>NEXTDSP

Enables/dissables interrupts and allows I/O on IIOF bits

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REGISTER HEX ADDRESS VALUE DESCRIPTION

IIOF3 <= PREVDSP

INTERNAL RAM0 2FF800 - 2FFBFF NA General purpose memory

INTERNAL RAM1 2FFC00 - 2FFFFF NA General purpose memory

TIMER0 CONTROL 100020 6 = TCLK0 HIGH

0 = TCLK0 LOW

FIFO serial data bit line

TIMER1 CONTROL 100030 6 = TCLK1 HIGH

2 = TCLK2 LOW

FIFO serial clock line

DMA INTERRUPT ENABLE REGISTER

DIE 0

INTERNAL INT. ENABLE REGISTER

IIE 0

Initialization

The software should initialize the processor as follows:

25

main()

{

*LOCALCTRL = 0x103C0880; /* set up local bus memory map and wait states */

*GLOBALCTRL = 0x0F8B4000; /* set up global bus memory map and wait states */

asm(" LDHI 8000H,AR1"); /* point both the interrupt vector table */

asm(" LDPE AR1, IVTP"); /* pointer and the trap vector table pointer */

asm(" LDPE AR1, TVTP"); /* to the begining of the global memory */

asm(" LDI 800H,ST"); /* enable the cache */

asm(" LDI 0,DIE"); /* no DMA interrupts */

asm(" LDI 0,IIE"); /* no internal interrupts */

asm(" LDI 0220H,IIF"); /* set IIOF outputs but do not enable interrupts */

/* body of program contains */

/* whatever else that requires initialization before the interrupts are enabled */

asm(" LDI 022BH,IIF"); /* IIOF0 is level triggered */

asm(" IDLE"); /* wait forever but process interrupts */

}

IIF Output Table

"VME_INT1" "DSPXX_INT" IIF WRITE VALUE

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"VME_INT1" "DSPXX_INT" IIF WRITE VALUE

0 0 0x022B

1 0 0x026B

0 1 0x062B

1 1 0x066B

Programming the FIFOS The accumulations from the IF section are written to the I and Q FIFOS. Each DSP has a pair of these FIFOS, and values are obtained from each FIFO by issuing reads to the DSP global bus. Each FIFO has a depth of 8192 18-bit words.

The FIFOS are capable of generating DSP interrupts (to IIOF0) under certain conditions. The FIFO INT SEL bit in the status/control register chooses the condition; they can be configured to interrupt either when the FIFO is half full, or when the FIFO depth reaches a programmed level. The FIFO INT SEL bit selects the mode for all four FIFOs.

Programming of the FIFO depth is performed by the DSP, which uses its on-chip timer outputs to drive the FIFO LD, SI and SEN lines. These lines are used to serially load two 13-bit integer threshold values into the FIFOs. The first is the Empty Offset, which defines the "Programmable Almost Empty" threshold, and has no effect in the PIRAQ application. The second is the Full Offset, which defines the "Programmable Almost Full" threshold (PAF). In this mode, the DSP interrupt is triggered when the FIFO reaches this depth.

To perform the FIFO programming, place the data bit on the TCLK0 output, and then latch it into the FIFO by raising and lowering the TCLK1 output. To set TCLK0, shift the data bit left by two bits, OR it with 0x2, and write to 0x100020. The toggle TCLK1, write 0x6 followed by 0x2 to 0x100030. This is repeated for the 26 data bits which make up the Empty Offset and Full Offset values. Note that after programming, TCLK0 must be left in a low state for the FIFO to operate correctly. (This is not done in PAF.C)

The FIFO depth can be programmed serially by the DSP by writing to the register at address 20021, TCLK0 (100020), and TCLK1 (100030). Note: SD0 (TCLK0 on DSP 1) must be left low (a 2 in timer control register 100020) before triggers begin to cause the lowest bit of the FIFO data to be correct.

27

Connectors

Name and Location Signal Pin Function

BTPOUT 9

Buffered TPOUT from the timer/trigger section. This will either have the RAMTP from the waveform generator, or the TPOUT from the timer/trigger section. The source is selected via the TP SOURCE bit in the status/control register. The selection capability provides a convenient way of disconnecting the waveform RAMTP from TPOUT while the waveform table is being programmed.

SYNCIN 10 Not used.

TRIGIN 11 Input that can be used as an external trigger to the timer/trigger section.

BRAMTPOUT 12

Buffered RAMTP from the waveform generator. It will follow RAMTP even the waveform table is being programmed. BTPOUT can be used if this behavior is not desired.

AFC_DAC 13

BSYNCOUT 14 Not used.

J1 DB15F on guide

PHASEALARM 15

J3 SMC on card LO OUT

TCK 1 Bit Blaster

TDO 3 Bit Blaster

TMS 5 Bit Blaster

J4 header

TDI 9 Bit Blaster

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Name and Location Signal Pin Function

J5 SMC on guide

XMIT SAMPLE(B)

IF Input B, also sampled for RFTRIG. Selected for IF input via waveform table RFSWITCH.

J6 SMC on guide IF IN (A) IF Input A. Selected for IF input via

waveform table RFSWITCH.

J8 SMC on card AC_ADCOUT Analog output of the DAC values from the

waveform table.

J9 SMC on guide REF IN Reference oscillator input.

DO0 2

DO1 3

DO2 5

DO3 7

DO4 9

DO5 11

DO6 13

J11 header

DO7 14

Waveform TTL out

+5 V

MEM_POWER J12 header

+3.3V

J13 header JTAG 1-14

J14 header DSP2 COM5

J15 DSP2 COM2

29

Name and Location Signal Pin Function

header

J16 header DSP1 COM5

J17 header DSP1 COM2

Table 3. PIRAQ Connectors

30