3 Differential Amplifiers

3.1 Differential Amplifiers

[ref: Art of Electronics, by Horowitz & Hill]

Figure 3.1:

Differential amplifiers are amplifiers which are designed to amplify thedifference between two input signals i.e.

Vout = Ad (V1 − V2)

where Ad is the differential voltage gain. Ad is a positive number, and thus

if V1 is greater than V2 then the output with be a positive with respect tothe circuit ground.

Applications of differential amplifiers include:

• Amplifying a weak signal carried by a pair of wires, where both wiresare not at ground potential (being the ground of the amplifier). Signals

common to both wires (e.g. pickup of 50 Hz) cancel in the subtraction,

3-1

i.e. if

V1 = Vx + Vpickup

V2 = Vy + Vpickup

where Vpickup is a signal common to both, then

V0 = Ad (V1 − V2) = Ad (Vx − Vy)

Figure 3.2:

• DC amplifiers (one can ground one input e.g. V2 = 0) then

Vout = Ad (V1 − V2) = Ad (V1 − 0) = AdV1

• Balanced transmission lines (used sometimes for audio applications andfor RF applications).

• The type of amplifier known as the operational amplifier or “opamp” isa specially designed differential amplifier with very high gain (>105).

Opamps can be used to implement a variety of analogue signal pro-cessing and conditioning circuits including: addition, subtraction, in-version, active filters, integration, differentiation, logarithms, peak de-

tectors, gyrators (an ‘inductor’ built using opamp and a capacitor),active rectifiers, etc.

In linear signal processing applications (filtering, amplification), opampcircuits usually employ negative feedback which reduces the gain, but

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provides some very desirable properties such as improved linearity, in-dependence of fluctuations in Ad as a result of temperature).

Opamp circuits usually operate in the kHz frequency range, but someof the faster opamps can be used in the MHz region.

3.1.1 Terminology

The input terminal labelled V1 or ‘+’ is known as the non-inverting input(if V2 = 0 then V0 = AdV1).

The input terminal labelled V2 or ‘-’ is known as the inverting input (ifV1 = 0 then V0 = −AdV2).

A differential change1 at the inputs refers to a change in Vd = (V1 − V2).

A common-mode change refers to a change in voltage which is common toboth inputs.

Ideally a differential amplifier should respond only to differential changes atthe inputs. In practical circuit implementations the output is also sensitive

to common-mode changes. For example if we tie both inputs together andconnect the inputs to a signal generator, the output will responds to some

degree.To characterise the behaviour, it is useful to define two voltage gains:

Differential gain

Ad =∆Vout

∆Vd

where ∆Vd is an incremental change in the difference voltage, i.e.

Vd = (V1 − V2) → V1 − V2 + ∆Vd

Common-mode gain

Ac =∆Vout

∆Vc

1A differential change is also sometimes called a “normal mode” change.

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where ∆Vc is a change common to both inputs. i.e. V1 and V2 change

V1 → V1 + ∆Vc

V2 → V2 + ∆Vc

A good differential amplifier will have a differential gain which is high com-pared to its common-mode gain, i.e

Ad ≫ Ac

Common-mode Rejection Ratio (CMRR)

Another parameter which characterises an amplifier is the ratio,

CMRR =Ad

Ac

which is sometimes expressed in dB, being

20 log

∣

∣

∣

∣

Ad

Ac

∣

∣

∣

∣

Example

The commercially available OP-77 opamp has a CMRR of 120 dB (stated

in the data sheets). From this we can conclude that

|CMRR| =

∣

∣

∣

∣

Ad

Ac

∣

∣

∣

∣

= 10120

20 = 106

as a ratio. Although the quantity Ad is positive, the common mode gain Ac

may be positive or negative depending on the circuit implementation. Allwe can say from the dB CMRR alone is that |Ac| = 106 × Ad.

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3.2 Transistor implementation of a differential amplifier

A differential amplifier can be constructed using a pair of matched transis-

tors. The configuration shown in Figure 3.3 is known as the“emitter coupledpair” (because the emitters are coupled together (via the RE’s) at the node

marked A). This configuration is also known as the “long tail pair”, becauseof transistors attached to a “tail” resistor R. It may be implemented using

BJT transistors (NPN or PNP) or FETs.

Figure 3.3: Differential amplifier implemented using a “long tail pair”.

• In order for the emitter coupled pair to function well as a differential

amplifier, the transistors should be accurately matched (near identicalcharacteristics), ideally manufactured on the same piece of silicon.

• The inputs are at the bases of the transistors, marked V1 (non-invertinginput) and V2 (inverting input).

• The supply rails are marked VCC and VEE. Typical values could be

VCC = 15 V and VEE = −15 V.

• The transistors carry currents I1 and I2 which sum together at the

coupling point marked“A” in the sketch. A current IEE ≈ I1 + I2 flows

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in the tail resistor R. In our analysis we shall assume a large β, sayβ > 100, such that IC ≈ IE holds.

• Because of the symmetry, if the two inputs are tied together (i.e. V1 =V2), then I1 = I2, assuming identical transistors.

• The output is taken at the collector of transistor Q2.

3.2.1 Differential Gain Analysis

Consider, initially, the sitation where both inputs are grounded, i.e. V1 =V2 = 0.The voltage at node A will be a volt or two below zero (depending on the

value of RE and the operating current).The collector currents I1 and I2 both flow through the same tail resistor

R, and since we are ignoring base currents, IEE = I1 + I2. Thus, from thesymmetry, we have

I1 = I2 =IEE

2The output voltage is taken from the collector of Q2, being

Vout = VCC − I2RC

The output voltage is typically arranged to sit at half the supply (VC =12VCC) for the case when both inputs are grounded.

Now consider what happens if a small differential voltage ∆V = V1−V2 (say

less than 100 mV) is created between the input terminals, by increasing V1

by ∆V2 and decreasing V2 by ∆V

2 such that V1 − V2 = ∆V . The differential

voltage is created in such a way to avoid introducing a common-mode com-ponent at the input (i.e. the average voltage is still zero).

The emitter voltages will follow with approximately the same increments,and so by symmetry, the voltage at node A will not change significantly

(∆VA ≪ ∆V ). Thus we consider ∆VA = 0.

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Since the voltage at A is fixed, the collector current I1 will increase byan amount

∆I1 =∆V1

re + RE=

∆V/2

re + RE

where re = 25 mV/I1.I2 will decrease by the same amount:

∆I2 =−∆V/2

re + RE= −∆I1

This causes the output voltage to rise by

∆Vout = −∆I2RC = −−∆V/2

re + RERC =

RC

2 (re + RE)∆V

Thus the differential voltage gain is

Ad =∆Vout

∆V=

RC

2 (re + RE)

(being half of the gain derived for a single ended common emitter AC am-

plifier).

Figure 3.4 shows a plot of the currents I1 and I2 as a function of the differ-ential input voltage ∆V . As ∆V increases from zero, the currents I1 andI2 are initially fairly linear functions of ∆V but eventually flatten as |∆V |

increases. For larger values of ∆V (a few volts), Q2 will switch off com-pletely, and IEE = I1 ≈ (V1 − 0.6)/(RE + R), rising beyond the operating

value as V1 continues to increase (this plot does not extend that far).

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0100mV50mV−50mV−100mV

IEE

∆V

I1

I2

IC ≈ IE

IEE

2

Figure 3.4: Plot of the collector currents I1 and I2 as a function of the differential inputvoltage ∆V .

Alternative explanation of the differential voltage gain

From our previous analysis of a single transistor AC amplifier, it should beobvious that if V2 decreases by ∆V/2 and the voltage at node A is fixed,

then∆Vout

∆V2=

∆Vout

−∆V/2=

−Rc

re + RE

Thus

Ad =∆Vout

∆V=

Rc

2 (re + RE)

3.2.2 Common Mode Gain Analysis

The common-mode gain is determined by tying both inputs and injectinga voltage common to both. The analysis may be simplified by splitting the

circuit into two parts as illustrated in Figure 3.5. The tail resistor is splitinto two resistors each of value 2R carrying currents I1 = I2 = IEE/2.

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Figure 3.5:

If both inputs are tied together and change by an amount ∆V = ∆V1 =

∆V2, then (as in the standard analysis of a single transistor AC amplifier)

∆Vout = −∆I2RC = −∆V2

re + RE + 2RRC =

−RC

re + RE + 2R∆V2

and∆Vout

∆V2=

−RC

re + RE + 2R

Thus the common mode gain is

Ac =∆Vout

∆V=

−RC

re + RE + 2R

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3.2.3 The CMRR

• Substituting the expression for Ad and Ac into the definition of common

mode rejection ratio, we get

CMRR ≡Ad

Ac=

RC

2(re + RE)/

−RC

re + RE + 2R

CMRR = −re + RE + 2R

2 (re + RE)

• Note To achieve a high CMRR, one should choose R ≫ re + RE forwhich the following approximation can be made:

CMRR ≈−R

re + RE

3.2.4 Practical Circuit

Figure 3.6:

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• The components are chosen such that Vout ≈12VCC when V1 = V2 = 0.

• One can omit the resistor RC from Q1, saving one resistor. This will

have no influence on the circuit as I1 is not a function of the collectorresistance of Q1.

• Quiescent current at Vout = 12VCC is designed to be 100µA.

The voltage at node A is

VA = V1 − VBE1− I1RE ≈ 0 − 0.6 − 0.1 = −0.7 V

The intrinsic emitter resistance is

re ≈25

0.1= 250 Ω

The differential gain is

Ad =RC

2 (re + RE)

=75000

2 (250 + 1000)≈ 30

The common mode gain

Ac =−RC

(re + RE + 2R)≈ −

RC

2R= −

75

2 × 72≈ −0.5

Thus

CMRR =30

(−0.5)= −60

3.2.5 Improved CMRR Performance using current source

The common mode gain and the common mode rejection ratio are functionsof the tail resistance R, i.e.

Ac =−RC

re + RE + 2R

CMRR ≈−R

re + RE

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To improve the CMRR, one can replace the tail resistor R by a currentsource which has very high impedance. Observe that as R → ∞, Ac → 0

and |CMRR| → ∞. A practical circuit can achieve a CMRR of 106, with awell designed current source.

Figure 3.7:

If one ties V1 and V2 together, then I1 = I2 = IEE/2 (always), independent

of the base voltage. Thus the use of a current source in the tail eliminatescommon-mode gain, and the CMRR is theoretically infinite.

A practical circuit is shown in Figure 3.8. The emitter current

IEE = IC3 ≈ IE3 =VE3 − VEE

RX=

VB − 0.6

RX

The emitter voltage is biased to a couple of volts above the negative rail.This ensures that small changes in VBE2 do not significantly affect the cur-

rent IE3.The output impedance2 of the current source is about 4 MΩ, which implies

2The output impedance of this BJT current source implementation (with the base at a fixed voltage)can be shown to be R0 = r0(1 + (βre ‖ RE)/(re ‖ r0)) ≈ r0(1 + βRE/(βre + RE)) where RE is theemitter resistor, r0 is the collector emitter resistor in the small signal model. For a collector currentIC , r0 = VA/IC where VA is the so called Early voltage, specified in data sheets. For a discrete BJTtransistor like the 2N2222A, 100 < VA < 500, and so for a collector current of 2 mA, this would predict50 kΩ < r0 < 250 kΩ. For r0 = 100 kΩ, RE = 1000 Ω, β = 100, re = 25/2 = 12.5 Ω, ⇒ R0 ≈ 4.5 MΩ.

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a CMRR of 4E6/(25 + 100) = 32400 or 90 dB.

Figure 3.8: Current source in the tail.

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3.3 DC Amplifier

Figure 3.9:

• A non-inverting DC amplifier can be created from a differential am-plifier by grounding one input V2 = 0, and feeding the input signal at

V1.

• The output can not swing below the base voltage of Q2, which is zero.Thus for the case of Vin = V1 = 0, the output is typically designed to

sit at Vout = 12VCC (by the choice of RC). A subsequent level shift stage

may be used to remove the 12VCC offset at the output.

• The use of a differential amplifier (with one input grounded) for DCamplification essentially removes the problem of the ‘0.6 volt VBE off-

set’ present in a single transistor amplifier shown in Figure 3.10, andcompensates for dependence on temperature.

For a fixed collector current, VBE decreases by 2.1 mV/C increasein temperature. If the temperature increases, the reduction in VBE

forces the collector current (Figure 3.10) to increase, and hence theoutput voltage decreases.

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• The differential amplifier inherently compensates for temperature driftsbecause the VBE voltages of well matched transistors change by same

amount. The identical changes in VBE will not be amplified by Ad, butby the common-mode gain Ac, which is small (usually <1) comparedto Ad.

• If V2 = 0, Vin = V1, then the common-mode change is Vc = (V1 +V2)/2 = Vin/2, and so the output is

Vout = AdVin + AcVin

2+

VCC

2

≈ AdVin +VCC

2

since Ad ≫ Ac.

Figure 3.10: Use of a single stage transistor as a DC amplifier suffers from the input offsetas well as temperature dependence.

3.3.1 Gain Analysis of the DC Amplifier

Consider the DC amplifier configuration below.

Note that I1 + I2 ≈ I and

I1 ≈I

2+ ∆I

I2 ≈I

2− ∆I

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Figure 3.11:

First, we examine how VA changes if V1 is increased by ∆V1.

For incremental changes about the bias point, from nodal analysis, consid-ering incremental changes in current into node A

∆V1 − ∆VA

re + RE+

∆V2 − ∆VA

re + RE+

∆VEE − ∆VA

R= 0

Since V2 = 0 (constant), ∆V2 = 0. Since VEE is a fixed voltage, ∆VEE = 0.

Substituting and grouping terms, we get

∆V1

re + RE−

2∆VA

re + RE−

∆VA

R= 0

and solving for ∆VA

∆VA

[

2

re + RE+

1

R

]

=∆V1

re + RE

∆VA =∆V1

2 + re+RE

R

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Since R ≫ re + RE (by design)

∆VA ≈∆V1

2

Take note that an increase in V1 of ∆V1 will cause VA to rise by ∆VA ≈ ∆V1

2 .

Next, we try to express ∆Vout in terms of ∆V1.

The incremental output voltage

∆Vout = −∆I2RC

but

∆I2 =∆VBE2

re + RE=

−∆VA

re + RE

Substituting our expression for ∆VA,

∆I2 =−∆V1

(

2 + re+RE

R

)

(re + RE)

Thus

∆Vout = ∆V1RC

(

2 + re+RE

R

)

(re + RE)

The gain is thus∆Vout

∆V1=

RC(

2 + re+RE

R

)

(re + RE)

If R ≫ re + RE (by design of a good high impedance current source) then

gain of the DC amplifier is

Gain =∆Vout

∆V1=

RC

2 (re + RE)

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3.3.2 Input Impedance of DC Amplifier

Figure 3.12:

If V2 = 0, the input impedance is β times the effective impedance “looking

into the base of Q1” considering the impedance paths to ground, i.e.

Zin = β [(re1+ RE1

) + R|| (re2+ RE2

)]

Figure 3.13: Inpedance paths to ground seen looking into the base.

For matched components RE1= RE2

= RE and re1= re21

= re, so

Zin = β [(re + RE) + R|| (re + RE)]

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If R ≫ (re + RE), which is usually true in practice, then

Zin ≈ 2β (re + RE)

Example: For I = 200 µA, β = 100, in Figure 3.12,

re =25

0.1= 250 Ω

RE = 1000Ω

⇒ Zin = 250 kΩ

Note Very much higher input impedance can be achieved using FET tran-sistors. FET input stages are often used in opamps (although FET inputstages have higher voltage noise than BJT input stages).

Input impedance of DC amplifier (by derivation)

Zin =∆Vin

∆Iin=

∆Vin

∆I1/β= β

∆Vin

∆I1

Since

∆I1 = −∆I2 =∆V1

(

2 + re+RE

R

)

(re + RE)

and ∆Vin ≡ ∆V1, thus

Zin = β

(

2 +re + RE

R

)

(re + RE)

≈ β2 (re + RE)

since R ≫ re + RE for a high impedance current source.

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3.4 Audio Pre-Amplifier with Load

Figure 3.14:

Voltage Gain

∆Vo

Vin=

RC||RL(

2 + re+RE

R

)

(re + RE)

≈Rc||RL

2 (re + RE)

Input Impedance

Rin = R1||β [(re + RE) + R|| (re + RE)]

Rin ≈ R1||2β (re + RE)

Input HPF breakpoint

ω1 =1

R1C1

Output HPF breakpoint

ω2 =1

(RC + RL)C0

(Can you see why? Hint, think of the Thevening equivalent of the output

stage)

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3.5 “Single Ended”Differential Amplifier

• A single ended differential amplifier is one which has one output.

Figure 3.15:

• One can ground either the ‘+’ or the ‘-’ input of a differential amplifier

to create either an inverting or a non-inverting DC amplifier.

Figure 3.16:

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3.6 “Double Ended”Differential Amplifier

• A double ended differential amplifier has two anti-phase outputs

• Used for transmitting signals over a “balanced pair” (audio & telecomapplications)

Figure 3.17:

• Double Ended Gain

(double ended) A =Vout1 − Vout2

V1 − V2

Note The double ended gain is twice the single ended gain. i.e.

(double ended) A = 2×RC

2 (re + RE)=

RC

re + RE

If we ground one input (say V2 = 0) then drive V1 with a small wiggle,

then we observe the following waveforms at the outputs:

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Figure 3.18:

3.6.1 Application of double ended amplifier

Figure 3.19:

• A twisted pair transmission line is much less sensitive to “pickup” fromchanging magnetic fields, compared to a parallel wire transmission line

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Figure 3.20:

• Recall Faraday’s law, which states that the induced voltage equals (mi-

nus) the rate of change of flux cutting a loop, i.e. Vind = −dΨm

dt adds inseries with the driving source.

• With a twisted pair, the net flux≈zero. (flux contributions to adjacent“twists” will cancel)

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