Op-Amp Design Overview

8/10/2019 Op-Amp Design Overview

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Op-Amp Design Overview

Operational Amplifier

Stability Compensation

Miller Effect

Phase Margin

Unity Gain Frequency

Slew Rate Limiting

Reading:

Solomon, The Monolithic IC Op Amp: ATutorial Study


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Analysis Strategy

Recognize sub-blocks

Represent as cascade of simple stages


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Total op-amp model

Input differential pair Common source stage


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DC operating point

MOSFET ID[A] Veff

M1 25 0.235

M2 25 0.235

M3 25 0.247

M4 25 0.247M5 50 0.350

M6 50 0.332

M7 50 0.332

M8 50 0.332


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Small signal parameters

MOSFET ID[A] Veff gm[A/V] rds

M1 25 0.235 208

M2 25 0.235 800k!

M3 25 0.247

M4 25 0.247 1.43M!M5 50 0.350 285 715k!

M6 50 0.332

M7 50 0.332

M8 50 0.332 400k!

Note: Channel length modulation parameters

n= 0.050 V-1; p= 0.028 V

-1


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Total op-amp model: Low frequency gain

Input differential pair Common source stage

av1 = g

m1 r

ds2 r

ds4

av1 = 208A V( ) 800k!1.43M!( )

av1 =106

av2 =g

m2 r

ds5 r

ds8

( )av2 = 285A V( ) 400k! 715k!( )

av2 = 73


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Total op-amp model with capacitances

Gate of M5 Load: scope probe "10pF

Cg = (900m)(10m) 4.17E! 4

F

m2

"

#$

%

Cg = 3.74pF


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Total op-amp model with capacitances

First stage pole Second stage pole

fp1 =1

2! rds2 rds4( )Cg5

fp1 =1

2! 800k"1.43M"( ) 3.74pF( )

fp1 = 82kHz

fp1 =1

2! rds5 rds8( )CL

fp1 =1

2! 400k" 715k"( ) 10pF( )

fp1 = 61kHz


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Open loop transfer function

Product of individual stage transfer functions

A(j!) =gm1 rds2 rds4 gm5 rds5 rds8( )

1+j!2" rds2 rds4( )Cg5[ ] 1+j!2" rds5 rds8( )CL[ ]


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Two-stage op-amp: Simulation Schematic


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DC Operating Point Simulation


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Bode plot (single-pole term)

Magnitude, phase on log scales

Pole: Root of denominator polynomial


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Open loop Bode plot

Product of terms : Sum on log-log plot


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Stability example: Closed loop follower

Negative feedback:

Output connected to inverting input


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Unity gain: Why bother?

With buffer:

No current required

from source

vout =RL

RL + RS

!

"# $

%&vin vout = vin

No buffer:

Voltage divider

Signal reduced due to

voltage drop across RS


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Problem: Instability

Oscillation superimposed on desired output

Output for zero input Why? Need...


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Controls: ES3011 in 20 minutes

General framework

A: Forward Gain: Feedback Factor

fraction of output

fed back to input


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Example: Op-amp, Noninverting Gain

A: Forward Gain

Op-amp open loop gainVout=A(V+-V-)

Transfer function A(j#)

: Feedback Factor

! =R1

R1 + R2


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Closed Loop Gain

Output

Solve for vout/vin

vout = A vin !"vout( )v+! v!

1 24 34

vout = Avin ! A"vout

1 + A"( )vout = Avinvout

vin

=A

1 + A"


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Op-amp with negative feedback

If A >> 1

Closed loop gain determined only by

Advantage of negative feedback:

Open loop gain A can be ugly (nonlinear,poorly controlled) as long as it's large!

voutvin

=

A

1+ A!" A

A!#

voutvin

" 1

!


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Example: Op-amp, Noninverting Gain

: Feedback Factor

Closed loop gain

! =R1

R1 + R2

vout

vin=

R1+ R2

R1=

1

!


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Reexamine closed loop transfer function

Output with no input:

infinite gain

Infinite when 1+A = 0

Condition for oscillation:

1+A = 0

In general A, functions of#

If there's a frequency #at which 1+A = 0:

Oscillation at that frequency!

vout

vin

=

A

1+ A!


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Example: follower

Use A(j#),

solve for 1+A = 0

No thanks!

! = 1 " vout

vin

=

A

1 + A

A(j!) =gm1 rds2 rds4 gm5 rds5 rds8( )

1 +j!2" rds2 rds4( )Cg5[ ] 1 +j!2" rds5 rds8( )CL[ ]


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Reexamine condition for oscillation

1+A = 0$A = -1

Magnitude and phase condition:|A| = 1 AND %A = -180

Easier to get from Bode plot


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Look at original A for 2 stage op-amp

Find #at which |A| = 1; Check %A -180 ?

Trouble!


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Simulation A for 2 stage op-amp


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Compensation: Dominant Pole

Move one pole to

lower frequency How?


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Compensation: Dominant Pole

Need to increase

capacitanceby "1000X:

BAD! Die area cost


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Miller Effect

Impedance across inverting gain stage G

Reduced by factor equal to (1+G)


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Math for Miller effect

Impedance across inverting gain stage G

Reduced by factor equal to (1+G)

ixvx (Gvx )

Z

ixvx 1 G

Z

vx

ix

ZinZ

1 G


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Example: Impedance is capacitive

Capacitance multiplied by (1+G)

Equivalent capacitance higher by factor 1+G

Problem for high bandwidth amplifiers

Opportunity for compensation ...

Zin =Z

1+G( )

Z=1

sC! Zin =

1

s 1 +G( )C

Ceq1 24 34


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Miller Compensation

Need effect of large capacitance

Use Miller effect to multiply small on-chipcapacitance to higher effective value

Effect of large capacitance

without die area cost of large capacitance


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New schematic

Add CCacross 2nd stage


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New transfer function


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New step response

No oscillation!


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"Phase margin"

How stable is new

transfer function?

Phase margin =

Phase lag at |A| = 1

minus (-180)


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Dominant pole op-amp model

Simpler model with dominant pole from CC


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Approximate dominant pole transfer function

A(j! ) "gm1 rds2 rds4( )A2

1+ j! rds2 rds4( )A2CC[ ]

A2 = gm5 rds5 rds8( )


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Unity gain frequency

Depends only on

Input stagetransconductance gm

Compensation

capacitor CC

A(j! ) "gm1 rds2 rds4( )A2! rds2 rds4( )A2CC[ ]

A(j! ) =1 at !T

!T "gm1

CC


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Slew rate

I= C dV/dt

Only limited current IBIASavailable to charge,discharge CC


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Slew rate

I= C dV/dt & =

CC

IBIASdV

dt


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Summary Op-amp:

Stability

Compensation Miller effect

Phase Margin

Unity gain frequency

Slew Rate Limiting

Documents

Op-Amp Design Overview