JOURNAL OF ELECTRONIC TESTING: Theory and Applications 23, 163–174, 2006

* 2007 Springer Science + Business Media, LLC. Manufactured in The United States.

DOI: 10.1007/s10836-006-0548-6

On the Tolerance to Manufacturing Defects in Molecular QCA Tiles

for Processing-by-wire*

JING HUANG, MARIAM MOMENZADEH AND FABRIZIO LOMBARDI

Department of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USAhjing@ece.neu.edu

mmomenza@ece.neu.edu

lombardi@ece.neu.edu

Received February 21, 2006; Revised July 6, 2006

Editor: M. Tehranipoor

Abstract. Among emerging technologies, Quantum-dot Cellular Automata (QCA) relies on innovative computational

paradigms. For nano-scale implementation, the so-called processing-by-wire (PBW) paradigm in QCA is very effective as

processing takes place, while signal communication is accomplished. This paper analyzes the defect tolerance properties

of PBW for manufacturing tiles by molecular QCA cells. Based on a 3�3 grid and various input/output arrangements in

QCA cells, different tiles are analyzed and simulated using a coherence vector engine. The functional characterization

and polarization level of these tiles for undeposited cell defects are reported and detailed profiles are provided. It is shown

that novel features of PBW are possible due to the spatial redundancy of the cells in the tiles that permits to retain at high

probability the fault free function in the presence of defects. Moreover, it is shown that QCA tiles are robust and

inherently tolerant to cell defects (by logic equivalence, also additional cell defects can be accommodated).

Keywords: QCA, defect tolerance, processing by wire, emerging technologies

1. Introduction

As CMOS is approaching its physical limits, new devices

for so-called emerging technologies (such as carbon tubes

and tunneling devices) have been proposed. These

technologies have the potential to achieve an extremely

high density (in the range of 1012 devices/cm2), fast

operating speed at Tera Hertz frequencies, together with

room temperature operation and low power dissipation.

Among these emerging technologies, Quantum dotCellular Automata (QCA) [7] is very promising. QCA

design involves diverse new paradigms, such as process-ing-by-wire (PBW) [10]. PBW refers to the ability of

QCA by which information manipulation can be accom-

plished, while transmission and communication of signals

take place. PBW capabilities can be observed in the

inverter chain as well as in the arrangement of cells in an

MV. An implicit PBW feature has also been analyzed in

[14] for testing of QCA devices and their unique logic

features. PBW is applicable to both combinational and

sequential circuits. Sequential circuits are not considered

in this paper as they have been analyzed in other manu-

scripts [17].

Recent research in QCA manufacturing involves

molecular implementations [3, 8]. It is expected that

homogeneous cell arrangements will be constructed by

either self-assembly, or large scale cell deposition on

insulated substrates [8]. Modular QCA design is well

suited to these manufacturing techniques [5, 6]. However,

very little work has been pursued on modular QCA

design to accomplish PBW. The SQUARES methodology

(based on a 5� 5 grid) has been proposed as initial effort

for modularizing QCA design [1]. However, SQUARES

is very limited, because it does not consider cell

interactions extending over the single grid. A tile-based

approach (using a 3� 3 grid) has been proposed in our

earlier work of [5]. It has been shown that tiles are not

only area efficient, but they also offer versatile logic and

interconnection functions. In previous works [1, 5], logic

and interconnect circuits are assumed to be defect free. In

this paper, the defect tolerance of tiles for QCA design is*This manuscript is an extended version of the paper by the same

authors that appeared in [4].

investigated. Five tiles (originally proposed in [5]) are

analyzed. The main focus of this work is defect tolerance

of tiles as basic devices. Design using the 3� 3 tiles has

been presented in [5, 6]. Various tile-based design issues

have been addressed in [6]. Sample circuits built with the

3� 3 tiles have been demonstrated and compared to the

SQUARES methodology and a gate-based design [6]. In

this paper, defect tolerance of 3� 3 tiles is investigated in

detail. The PBW offered by these tiles is extended by

investigating spatial redundancy in the arrangement of the

cells. The logic behavior of the defective tiles are

compared with the defect-free behavior to relate whether

the PBW capability of a tile is changed by the defects.

The polarization characteristics of the functions for all

analyzed tiles are also found by simulation. It is shown

that due to spatial redundancy, the correct functions of the

tiles are tolerant to defects. This further validates the

premises that tile-based design can be used to efficiently

assemble QCA circuits [5].

The rest of the paper is organized as follows. Preliminar-

ies, including review on QCA, PBW by tiling, the assumed

defect model and the simulation environment, are intro-

duced in Section 2. Section 3 presents detailed results for

defect tolerance of tiles. These results are analyzed in

Section 4. Finally, Section 5 concludes the paper.

2. Preliminaries

2.1. QCA Review

A QCA cell can be viewed as a set of four charge

containers or Bdots,^ positioned at the corners of a square

[15]. The cell contains two extra mobile electrons which

can quantum mechanically tunnel between dots, but not

cells. The electrons are forced to the corner positions by

Coulombic repulsion. The two possible polarization states

represent logic B0^ and logic B1,^ as shown in Fig. 1a.

Logic elements are based on two gate primitives

(inverter, or INV, and majority voter, or MV, as shown

in Fig. 1b and c) to implement combinational circuits.

Two arrangements referred to as the binary wire and the

inverter chain can be utilized as interconnects [15], and

are shown in Fig. 1d and e. Sequential as well as

combinational designs can be realized in QCA [9, 11,

18]. Clocking is also required for QCA [2]; clocking

implements timing over a planar layout in four periodic

zones for quasi-adiabatic switching.

Currently, micro-sized QCA devices have been fabricat-

ed with metal cells which operates at 50 mK [12]. Recent

developments in QCA manufacturing have focused on

molecular implementations [3, 8], in which higher speed

and room-temperature operation are expected. Moreover,

homogeneous cell arrangements can be constructed by

self-assembly or large scale cell deposition.

2.2. PBW by Tiling

As in the early stages of VLSI, QCA requires building

blocks that are versatile for flexible manufacturing and

assembly of different circuits. An early proposal for

modular QCA is the so-called SQUARES methodology

[1]; SQUARES is based on a 5� 5 QCA grid. A novel

arrangement has been proposed recently [17] for con-

structing a tile-based serial memory in QCA. Our previous

work in [5] has demonstrated that tiles based on the 3� 3

grid provides universal and versatile logic functions; it has

been shown that both logic and interconnect circuits can be

accomplished by utilizing these QCA tiles [5]. In this

paper, the defect tolerance of these tiles is investigated; it

will be shown that the proposed tiles are not only versatile

in logic function generation, but they are also inherently

defect tolerant. A tile is constructed with nine QCA cells

arranged in a 3� 3 grid. Tiles can be arranged to generate

the desired logic operations within a Cartesian layout. This

scheme provides the following desirable features at

manufacturing [5, 6]: (1) The 3� 3 grid provides a better

cell utilization than the 5� 5 grid of SQUARES [5]; this

is due to the separation of the logic/interconnect imple-

mentations and the reduced size of the building block, i.e.,

9 versus 25 cells in a grid. (2) Tile-based design allows

compatibility with timing/clocking techniques, thus reduc-

ing the length of the longest line of QCA cells in a zone

(and avoiding kinks).

2.3. Defect Model

Defect tolerance is the main focus of this paper. Currently

during manufacturing using a self-assembly molecular

process, defects can occur in both the chemical synthesisphase (in which the QCA cells are manufactured) and the

deposition phase (when the QCA cells are attached to a

substrate) (Lieberman, personal communication). Defects

are more likely to occur in the deposition phase than in the

chemical synthesis phase, often resulting in perfectly

manufactured but imperfectly placed cells. In this paper,

only the defect resulting from an undeposited cell, is

considered (a defect due to additional and incorrectly

deposited cell will be shown later to be logically

logic "0"

celldot

logic "1"

quantum

C

F=Maj(A,B,C)=AB+AC+BCB

A

F=A'A

(b) Inverter(a) QCA cell

(c) Majority Voter (e) Inverter Chain

(d) Binary Wire

Fig. 1. Basic QCA devices.

164 Huang et al.

equivalent). This represents the case when the defective

cell fails to attach to the substrate. Other defects in the

deposition phase such as due to misplacement are unlikely

to be present in a molecular self-assembly process. In the

assumed model, multiple undeposited cell defects may

occur. It will be shown later that additional cell defects can

also be considered as part of the assumed model.

For defect tolerance, the relationship between a fault-

free tile and a tile with undeposited cells is very

important because it defines the paradigm of PBW for a

tile-based design. It is evident that a tile inherently offers

significant defect tolerance as its nine cells closely

interact in a spatial redundancy arrangement.

2.4. Simulation Setup

For evaluating the effects of PBW in QCA, the software

simulation tool QCADesigner1 v1.4.0 (Unix version) is

used [13]. QCADesigner v1.4.0 features different simu-

lation engines. Throughout this paper, the coherence

vector engine is used due to its accurate and detailed

evaluation of QCA. The coherence vector engine is based

on the density matrix approach [13] which models the

power dissipative effects of QCA. The basic functionality

of QCA is based on the Coulombic interaction among

neighboring cells; this depends on the distance as well as

the angle between the two cells. The radius of effect Rdefines the Coulombic interactions within an area

centered on cell i, i.e., all cells within this area interact

with cell i. In all simulations the cell size, is 10� 10 nm

and the cell-to-cell distance is 2:5 nm. The radius of

effect R is set to 40 nm. All other parameters are set to the

default values of QCADesigner.

Hereafter, the following assumptions are made: (1)

Only undeposited cell defects are considered as likely to

occur in molecular implementations. The set of undepos-

ited tiles is denoted by U. (2) A one-dimensional clocking

scheme is assumed for quasi-adiabatic switching: all cells

in a tile are assumed to be within a timing zone; input and

output cells are assumed to be in distinct timing zones.

So, a total of three timing zones per tiles are used in the

simulations. (3) The no logic state (referred to as the

undefined state and denoted by B-^) may occur for some

defective patterns due to lack of definitive polarization at

the output. This happens when the polarization level is

very low (less than �0:1) for at least some input signals,

or a spike or glitch can be observed at the output.

3. Defect Tolerance of Tiles

Five different tiles based on the 3� 3 grid, as shown in

Fig. 2, are investigated in this paper. The orthogonal tile

is used for implementing MV as well as MV-like (MV

with inversion at selected inputs) logic functions. The

baseline and fan-in tiles can be used for signal switching

in the interconnect. The double and triple fan-out tiles are

also used as part of the interconnect. The defect tolerant

properties of these tiles are detailed in this section.

(b) Double Fan-Out tile (c) Baseline tile

(e) Triple Fan-Out tile(d) Fan-In tile

(a) Orthogonal tile

C

F1 2 3

4 5 6

7 8 9

A

1 2 3

4 5 6

7 8 9

F2

F1B

A

B

F2

F11 2 3

4 5 6

7 8 9

F1

B

F3

F21 2 3

4 5 6

7 8 9

A

B

F11 2 3

4 5 6

7 8 9

B

Fig. 2. Tiles based on a 3� 3 grid.

Tolerance to Manufacturing Defects in Molecular QCA Tiles for PBW 165

For a specific tile, the probability of generating a func-

tion f in the presence of jUj undeposited cells is defined

as follows:

Pf ;U ¼Nð f ;UÞ

CjUj9

ð1Þ

where CjUj9 is the number of all possible pattern combina-

tions when jUj cells are undeposited, Nð f ;UÞ is the number

of occurrences of function f in the presence of jUj un-

deposited cells (determined by simulation). In this paper,

each tile is constructed from a fully populated 3� 3 grid

and therefore each tile consists of nine cells that can be

possibly undeposited. For example, assume two cells are

undeposited, i.e., jUj ¼ 2. Then the number of all possible

pattern combinations C29 ¼ 36. If nine of these patterns

generates the desired function f in a specific tile (i.e.,

Nð f ;UÞ=9), then the probability of generating f is

Pf ;U ¼ 936¼ 25%.

3.1. The Orthogonal Tile

Fig. 2a shows the so-called orthogonal tile. Three input

cells (A, B, C) are connected to the sides of the tile, while

an output cell (F) is provided at the remaining side. In the

defect-free case, the output of this tile is Maj(A,B,C)=

ABþ BCþ AC. Thus, this is the basic logic block in a

tile-based design for QCA and its defect-tolerant proper-

ties are very important to assess.

Table 1 shows the simulation results when at most one

cell is undeposited from the orthogonal tile. The probabil-

ity of generating different majority functions versus the

number of undeposited cells is shown in Fig. 3. An

exhaustive simulation has also been pursued for the

orthogonal tile, i.e., with i undeposited cells, i ¼ 1, ....,8

from the layout (note that for all tiles, the absence of all

cells results in all outputs to take an undefined value). For

the orthogonal tile, the numbers of patterns of every

output function when i cells are undeposited, are shown

in Table 2. Once undeposited cell defects are present, the

three input signals may also interact, such that different

functions can be generated at the output, i.e., the relation

between the inputs and placement of the cells for PBW

may be changed. In particular, variants of the majority

function (with complemented input variables) are

Table 1. Single undeposited defect in orthogonal tile.

Undeposited cell F Undeposited cell F

None Maj(A,B,C) 1 Maj(A,B,C)

2 Maj(A_,B,C) 3 Maj(A,B,C)

4 Maj(A,B,C) 5 Maj(A,B,C)

6 Maj(A_,B,C_) 7 Maj(A,B,C)

8 Maj(A,B,C_) 9 Maj(A,B,C)

Fig. 3. Probability of generating different majority functions

vs. number of undeposited cells in the orthogonal tile.

Table 2. Number of occurrences of output functions in the orthogonal

tile with jUj undeposited cell defects.

F

{jUj}

1 2 3 4 5 6 7 8

A 0 0 2 5 9 9 5 1

A0 0 3 13 28 28 15 3 0

B 0 6 12 13 11 6 1 0

C 0 0 2 5 7 10 5 1

C0 0 3 15 28 30 15 3 0

– 0 4 11 24 24 22 16 6

Maj(A;B;C) 6 10 11 7 5 2 0 0

Maj(A0;B;C) 1 3 3 1 0 0 0 0

Maj(A;B;C0) 1 3 3 2 0 0 0 0

Maj(A0;B;C0) 1 3 12 13 12 5 3 0

NXOR 0 1 0 0 0 0 0 0

Total 9 36 84 126 126 84 36 9

Table 3. Functional characterization of orthogonal tile with multiple

undeposited cell defects.

Observations Results

Number of undeposited cells 1 2 3 4

Number of defective patterns 9 36 84 126

Occurrences of wire func. 0 4 22 32

Wire func. percentage 0% 11.1% 26.1% 25.3%

Occurrences on INV func. 0 4 23 51

INV func. percentage 0% 11.1% 27.3% 40.48%

Occurrences of MV func. 6 13 14 8

MV func. percentage 66.7% 36.1% 16.6% 6.34%

Occurrences of MV-like func. 3 11 14 11

MV-like func. percentage 33.3% 30.5% 16.6% 8.73%

Occurrences of undefined 0 4 11 24

Undefined state percentage 0% 11.1% 13.1% 19.1%

166 Huang et al.

expected due to possible input inversion through the cells

of the tile. The variants of the majority function are

referred to as MV-like functions (the cardinality of the

MV-like function set can be at most 7).

The following observations can be made from the

simulation results: (1) In almost all cases, an orthogonal

tile with undeposited cells (as defects) behaves in the

following two ways: wire/inverting functions or MV/MV-

like functions. (2) Undeposited cell defects occurring on

corner cells (cells 1, 3, 7 and 9) do not change the logic

function of the tile, thus confirming the defect tolerant

design of a majority voter. (3) In the simulations using

the coherence vector engine, whenever cell 6 is undepos-

ited, the polarization level experiences a significant drop.

In all simulated occurrences when cell 6 is present, the

magnitude of the maximum polarization is above �0:9.

However, when cell 6 is undeposited, then the magnitude

of the maximum polarization level drops below �0:77.

When other additional cells are undeposited (besides cell

6), in many cases the polarization level for some input

patterns is so low that no definite logic function can be

observed at the output. The statistical results in the

presence of up to four undeposited cells (corresponding to

a defect level just lower than 50%) are summarized in

Table 3. Note that by definition, the MV-like function set

does not include the MV function.

The average magnitude of the maximum polarization

level of the output when a number of cells are undepos-

ited as defects, is shown in Fig. 4. As for previous tiles,

in some cases the output exhibits the no definite polar-

ization level. In some cases, the polarization level is quite

high; also, when increasing the number of undeposited

cells as defects, the decrease in polarization level is not

significant. The analysis presented in this paper is ap-

plicable to tiles as basic QCA blocks within a single timing

zone (excluding the input and output cells); if a tile is con-

nected to another tile using a long QCA wire an appropriate

mechanism must be employed to maintain the correct

polarization level across multiple clocking zones [2].

3.2. Double Fan-out Tile

The double fan-out tile tile, as shown in Fig. 2b, is

analyzed next. The double fan-out tile has one input

(provided by the horizontal cell B) and two outputs (i.e.,

the horizontal output cell F1 and the vertical output cell

F2). In the defect-free case, both outputs follow the value

of the input cell, i.e., F1 ¼ F2 ¼ B (wire function), hence

the tile behaves as a fan-out point in a CMOS interconnect.

The following observations can be made with respect to

the fan-out tile in the presence of undeposited cell defects:

(1) Inversion can be expected at the outputs if one of the

cells connected to the corresponding output cell (i.e., cell 6

or 8) is undeposited. (2) A straightforward QCA imple-

mentation of the fan-out circuit requires only 4 cells (i.e.,

to deposit cells 4, 5, 6 and 8), so redundancy as basis for

defect tolerance is inherently present in this tile. Table 4

shows the results for a single undeposited cell defect.

When multiple cells are undeposited, it can be

observed that in most cases this tile produces either a

wire, or an inverting function (the output is the

complement of the input). The probabilities of generating

different functions for the two outputs (F1 and F2) are

plotted in Fig. 5. Even with four undeposited cells due to

defects, in almost 90% of the cases the tile can still

function either as a wire, or an inverter. This is caused by

its spatial redundancy as discussed previously, therefore,

an excellent level of resilience in functionality is

accomplished. The following additional observations

can be drawn: (1) The probability of being in an

undefined state for an output signal increases with the

number of undeposited cells. (2) The probability of

having a wire function in the horizontal output F1 is

greater than for the vertical output F2, indicating that

signal propagation in the one-dimensional clocking

scheme is stronger along the direction of signal flow

(perpendicular to the direction of the underlying clock

signal, which is implemented as an E field). (3) The

probability of having an inverting function in the vertical

output F2 is greater than for the horizontal output F1.

This is expected due to the 90- orientation of the output

cell with respect to the input cell and the possible 45-misalignments in the defect-free cells. (4) The polariza-

tion plots for two extreme cases are shown in Fig. 6a

(fault-free case or no defect) and b (all nine cells

undeposited). In the defect-free case, both outputs exhibit

Fig. 4. Average magnitude of the maximum polarization level of an

orthogonal tile.

Table 4. Single undeposited defect in double fan-out tile.

Undeposited cell F1 F2 Undeposited cell F1 F2

None B B 1 B B

2 B B 3 B B

4 B_ B_ 5 B B

6 B_ B 7 B B

8 B B_ 9 B B

Tolerance to Manufacturing Defects in Molecular QCA Tiles for PBW 167

the wire function with high polarization levels. In the

extreme case when all cells in the grid are undeposited,

logically F1 still produces the wire function, while F2

performs the inverting function; however, both outputs

have a very low polarization level (below the 0.1 value),

thus an undefined state function is generated.

These results confirm that PBW takes place in its

simplest form, i.e., it performs inversion. Moreover, the

fan-out tile has excellent processing capabilities (wire and

inverting functions), i.e., 93:6% of the exhaustive number

of combinations for up to four undeposited cells. The

average values of the maximum polarization level

(magnitude) at the outputs (F1 and F2) are shown in

Fig. 7. The diagram shows the average magnitude of the

maximum output polarization level when undeposited

cells are incrementally present. The average magnitude of

the maximum polarization level is reported for the wire

function, the inverting function, the undefined state

function as well as the total. The polarization level of

the wire function is higher than the inverting function for

all cases, thus confirming that this tile provides excellent

defect-tolerant capabilities compared to other functional

defective behaviors.

3.3. Baseline Tile

The baseline tile is shown in Fig. 2c; it has two inputs

(one vertical input cell A and one horizontal input cell B)

Fig. 5. Probability of generating different functions vs. number of undeposited cells in the double fan-out tile.

Fig. 6. Polarization plot of fan-out tile.

168 Huang et al.

and two outputs (the horizontal output cell F1 and the

vertical output cell F2). Table 5 shows the simulation

results when at most one cell is undeposited from the

baseline tile. This tile accomplishes wire crossing by

selectively undepositing cells.

For the baseline tile, altogether 20 output functions

(such as F1F2 ¼ AB, AB0; :::) are observed using an

exhaustive simulation. For undeposited cells, no addi-

tional inversion on the input signals is generated (while

still retaining the crossing property), i.e., F1F2 ¼BA0;B0A;B0A0 are not observed in the simulation. For

the fully populated grid, this tile works as a switch (or

coplanar crossing) with F1F2 ¼ BA, i.e., the two input

signals cross each other. In the presence of undeposited

cells, three types of functions are observed. The first type

is the coplanar crossing, that is also the fault free logic

function. The second type is when the tile works as two

L-shape wires, with F1F2 ¼ AB. Also in this type it is the

L-shape wires with inversion, such as F1F2 ¼ A0B,

F1F2 ¼ A0B0. The third type is the fan-out (when the

two outputs follow the same input, such as F1F2 ¼ BB,

F1F2 ¼ AA) and the fan-out with inversion, such as

F1F2 ¼ B0B. The last type is the undefined function in

which at least one output exhibits the undefined state.

The probabilities of having these function types versus

the number of undeposited cells are plotted in Fig. 8.

In the presence of undeposited cells as defects, no

additional inversion on the input signals is generated

(while still retaining the crossing property).

The average value of the maximum polarization level

(magnitude) at the outputs is shown in Fig. 9. The results

also show a near-symmetry in the operation of the outputs

of this tile. For example, when a number of cells are

undeposited, the probability of generating F1 ¼ A is

nearly the same as F2 ¼ B. Moreover, the average

maximum polarization level of A (B) is stronger at

F2(F1).

3.4. Fan-in Tile

The fan-in tile is shown in Fig. 2d. This tile has two

inputs (one vertical input A and one horizontal input B)

and one horizontal output F. In the fault free case, this tile

acts as a wire, with F following the horizontal input B.

Hence, this tile is referred to as the fan-in tile, i.e., only

the horizontal signal flow is permitted and the vertical

input is isolated. The simulation results when at most one

cell is removed from the tile are shown in Table 6.

The exhaustive simulation shows that altogether five

output functions (A, B, A0, B0 and �) are possible in the

fan-in tile. It can be observed that the output follows

either A (with possible inversion) or B (with possible

inversion) or it exhibits no definite polarization. These

results are summarized in Fig. 10.

Fig. 7. Average magnitude of the maximum polarization level of the double fan-out tile.

Table 5. Generation of output function by undepositing at most one cell

in the baseline tile.

U F1 F2 U F1 F2

None B A 5 A0 B0

1 B A 6 A0 A

2 B B 7 A A

3 B B 8 B B0

4 A A 9 B A Fig. 8. Probability of generating different functions vs. number of

undeposited cells in the baseline tile.

Tolerance to Manufacturing Defects in Molecular QCA Tiles for PBW 169

The average maximum polarization level (magnitude)

of the output F is shown in Fig. 11 for different numbers

of undeposited cells.

3.5. Triple Fan-out Tile

The triple fan-out tile is shown in Fig. 2e; this tile has one

input (the horizontal input cell B) and three outputs (the

three cells F1,F2 and F3). The simulation results when at

most a single cell is undeposited from a triple fan-out tile,

are given in Table 7.

Various output functions can be observed for the triple

fan-out tile, such as F1F2F3 ¼ BBB;B0BB; :::. For this

tile, in most cases even when multiple cells are undepos-

ited, the tile produces either a wire or an inverting function.

The probabilities of generating these functions versus the

number of undeposited cells are plotted in Fig. 12. It can be

concluded that the probability of the output in the unde-

fined state increases with an increased number of unde-

posited cells. Additionally, the probability of having a wire

function at the horizontal input F2 is greater than for a

vertical input (F1 or F2), while the probability of having

an inverting function for a vertical input (F1 or F2) is

greater than for the horizontal input F2.

4. Discussion and Analysis of Results

For the polarization level in the presence of undeposited

cell defects, the simulation results have shown the follow-

ing features:

(1) In all tiles, the total average magnitude of the

maximum polarization level decreases by increasing

the number of undeposited cells, as expected.

(2) In all considered tiles, the probability of no polariza-

tion increases when increasing the number of

undeposited cells. This is expected, because no

polarization will be encountered due to the large

inter-cell spacing. Additionally, in all considered

tiles, the curves for the probability of having the

undefined state versus the number of undeposited

cells have similar shapes (as shown in Figs. 5, 8, 10

and 12). This suggests that the probability of having

an undefined state at the output is independent of the

type of the tile, but it is dependent on the number of

undeposited cells.

As for functional characterization, the tiles show the

following behavior:

(1) The double and triple fan-out tiles have similar defect

tolerant properties (as shown in Figs. 5 and 12). The

fault-free function in these tiles is the wire function.

Table 6. Generation of output function by undepositing at most one cell

in the fan-in tile.

U F U F

None B 5 B

1 B 6 A0

2 B 7 B

3 B 8 B

4 A 9 B

Fig. 9. Average maximum polarization magnitude of baseline tile.

Fig. 10. Probability of generating different functions vs. number of

undeposited cells in the fan-in tile.

170 Huang et al.

It can be observed that with one undeposited cell,

the probability of having the correct wire function

at the outputs is >75% for the double fan-out tile and

> 65% for the triple fan-out tile. In both these tiles,

the probability of obtaining the correct wire function

at the horizontal output is greater than the probability

of obtaining the correct wire function at the vertical

output(s). Even with multiple undeposited cells, in

most cases the tile still produces a stable logic func-

tion: either the wire function, or the inverter function

(as shown in Fig. 13). These functions are very useful

for logic design [6].

(2) The MV-like function in the orthogonal tile com-

bines the logic function of MV and INV and can be

used efficiently in tile-based logic design [6]. Design

using MV-like functions has been investigated in

detail in [6]. Additionally, Fig. 3 illustrates that the

MV and different MV-like functions have unequal

sensitivity to undeposited cell defects. For example,

the probability of having the MV function

(F ¼Maj(A,B,C)) declines sharply by increasing the

number of undeposited cells, while the probability of

having the MV-like function F ¼Maj(A_,B,C_) stays

roughly the same with an increased number of

undeposited cells.

(3) The baseline tile acts as a switch (coplanar crossing)

in fault-free conditions. However, this switching

function is not very fault tolerant. Even with only

one undeposited cell, the probability of having the

switching function is less than 25%. With multiple

undeposited cells, in most cases this tile acts as a fan-

out (with possible inversion) tile, i.e., the two outputs

follow the same input.

(4) The presence of new logic functions (such as the

inverting function in the fan-out tile, the MV-like

functions in the orthogonal tile [6], or the fan-out

function in the baseline tile) shows that defect

tolerance can be utilized in accomplishing PBW even

under a large number of defective cells and high

defect levels.

5. Conclusion

In this paper, the defect tolerance of QCA tiles has been

analyzed under undeposited cell defects, as applicable to

molecular QCA. QCA tiles can be used as basic modular

blocks by which defect-tolerance can be in the future

extended to circuit-level [16]. By logic equivalence, this

analysis also illustrates the tolerance to additional (extra)

cell defects as the results provide the output character-

istics of a 3� 3 tile with less than nine cells (hence, the

presence of additional cell defects can also be accounted).

Specifically, in the defect model each cell can be assumed

to be erroneously deposited or undeposited in a tile for

generating the desired output function. Circuit design

using QCA tiles has been investigated in a previous paper

[6]. If a specific tile with k cells is the desired (fault free)

tile, the simulation results of this paper can also be

utilized for additional cell defects, i.e., for defects in

which unwanted cells are deposited (such that more than

k cells are present in the tile). Hence, a tile with k QCA

cells and jUj undeposited cell defects has the same

characteristics (polarization and functional behavior) as a

tile with k � jUj QCA cells with jUj additional cell

defects (provided all undeposited and additional cell

defects occur at same locations). Therefore, a logic

equivalence exists between a model made of undeposited

cell defects and a model made of additional cell defects

and the results presented in this paper can also be

extended to this last scenario.

The simulation results have shown that PBW by tiling

in the presence of cell defects is still very versatile and

robust. Except for the baseline tile, the capability of

generating the defect-free function is preserved with very

high probability for at most one defective cell per tile.

Moreover in the presence of multiple undeposited cells,

QCA tiles can still be used in most cases to perform

useful logic functions. Throughout an exhaustive simula-

tion, the following logic functions consistently appear at

the output(s) of the tiles: (1) the wire function, (2) the

inverting function, (3) the majority function, and (4) the

majority-like functions (i.e., majority function with one or

two complemented variables at the inputs).

The MV function is only observed in the orthogonal tile,

indicating that this tile plays a significant role in tile-based

QCA design (as the wire and INV functions are observed

Table 7. Generation of output function by undepositing at most one cell

in the triple fan-out tile.

U F1 F2 F3 U F1 F2 F3

None B B B 5 B0 B0 B0

1 B B B 6 B B0 B

2 B0 B B 7 B B B

3 B B B 8 B B B0

4 B0 B0 B0 9 B B B

Fig. 11. Average maximum polarization magnitude of fan-in tile.

Tolerance to Manufacturing Defects in Molecular QCA Tiles for PBW 171

Fig. 13. Probability of generating wire and INV functions in the tiles.

Fig. 12. Probability of generating different functions vs. number of undeposited cells in the triple fan-out tile.

172 Huang et al.

for all simulated tiles). A comparison of the results of this

paper with those of [6] suggests that as tile-based design is

not restrictive as a design utilizing discrete gates (such as

MV and INV) when assembling QCA circuits, defect

tolerance can also be incorporated into PBW. This feature

of QCA tiles exploits design modularity and its ability of

generating the same functions using different tiles with

arrangements in the input/output cells.

Moreover, in the presence of multiple undeposited

cells, tiles have a high probability of performing some

deterministic logic functions, even though it might be a

different logic function. As this is deterministic, a post-

fabrication step can be employed to reprogram the circuit

for performing an useful logic function. A process similar

to healing as for assembly [19] is envisioned.

Current research is been pursued by designing defect-

tolerant QCA circuits using the proposed tiles within a

CAD framework [16].

Note

1. QCADesigner is developed by the ATIPS lab at the University of

Calgary in Canada.

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Jing Huang recieved her B.S. degree in electronics engineer-

ing from Fudan University, Shanghai, China in 2001 and M.S.

degree in electrical engineering from Northeastern University,

Boston. She is currently a Ph.D. student and research assistant in

ECE department, Northeastern University, Boston. Before that

she has worked in the Computer Aided Test Lab in EE

Department, Fudan University as research assistant from 1999

to 2001. She also worked for Huawei Technologies Inc. China as

hardware design engineer from 2001 to 2002. Her research

interests include testing, design for testability and fault tolerance

of VLSI, reconfigurable systems and nanotechnologies.

Mariam Momenzadeh was born in Tehran, Iran. She

received her B.Sc. degree in electrical engineering from Sharif

University of Technology, Tehran, Iran in 1999 and M.Sc.

degree in computer engineering and Science from University of

Connecticut, Storrs in 2003. In 2006, she recieved her Ph.D.

degree in electrical and computer engineering department at

Northeastern University, Boston. Her research interests lie in

testing, design for testability and fault tolerance issues in

digital systems, ATE systems and nano-technologies.

Fabrizio Lombardi graduated in 1977 from the University

of Essex (UK) with a B.Sc. (Hons.) in electronic engineering.

In 1977 he joined the Microwave Research Unit at University

College London, where he received the master_s degree in

microwaves and modern optics (1978), a diploma in microwave

engineering (1978) and a Ph.D. degree from the University of

London (1982).

Tolerance to Manufacturing Defects in Molecular QCA Tiles for PBW 173

He is currently the holder of the International Test

Conference (ITC) endowed professorship at Northeastern

University, Boston. At the same institution during the period

1998-2004 he served as Chair of the Department of Electrical

and Computer Engineering. Prior to Northeastern University

he was a faculty member at Texas Tech University, the

University of Colorado-Boulder and Texas A&M University.

Dr. Lombardi was an associate editor (1996-2000) of IEEE

Transactions on Computers and a distinguished visitor of the

IEEE-CS (1990-1993). Since 2000, he has been the associate

editor-in-chief of IEEE Transactions on Computers. Currently

he is also an associate editor of the IEEE Design and Test

Magazine and a distinguished visitor of the IEEE-CS; he is

also the chair of the committee on nanotechnology devices

and systems of the Test Technology Technical Council of the

IEEE.

His research interests are testing and design of digital

systems, quantum computing, ATE systems, configurable/

network computing, defect tolerance and CAD VLSI. He

has extensively published in these area and edited six books.

174 Huang et al.