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Design Information
report_design provides a summary on operating conditions, derating factors, wire load models, and design rules like maximum capacitance, transition and fanout.
report_clock provides a summary of all clocks in the design including generated clocks with their sources and their attributes (propagated or ideal clocks).
report_disable_timing provides a summary of all the timing arcs that are disabled in the design.
report_case_analysis reports all the nets or pins that are constrained to appropriate values for proper propagation.
Constraint Checking
check_timing -verbose is a powerful construct in Primetime and is recommended to run on all designs to check the constraints. Primetime can report unconstrained clocks in the design, combinational timing loops, inputs or outputs that are not constrained, multiple clocks clocking the same flop or flops that do not have a clock defined on them. This aids the designer to identify incorrect or undefined constraints earlier in the cycle.
report_constraint generates a summary of all the constraint violations including setup/hold and the amount by which the design violates the constraint. Usage and offers available in this construct are
report_constraint -all_violators -verbose
By default, report_constraint generates all the violations in the design and the reports can be segregated by using appropriate switches. For example, to report only max fanout violations, a -max_fanout switch can be added.
report_constraint -all_violators -verbose -max_fanoutreport_constraint -all_violators -verbose -max_delayreport_constraint -all_violators -verbose -min_delay
report_constraint -all_violators -verbose -max_capacitancereport_constraint -all_violators -verbose -recoveryreport_constraint -all_violators -verbose -removal
Timing Reports
report_timing reports design timing information for each path group (or clock group) and offers several switches to segregate the timing results based on max
delay, min delay, recovery, removal etc. The level of detail that can be viewed in the reports can also be customized. Simple syntax for this construct is
# To report timing from one clock group to another (max_delay, setup)report_timing -from [get_clocks clk1] -to [get_clocks clk2] -delay max
# To report flop to flop timing (min_delay timing, hold)report_timing -from [get_pins my_count_lden_reg/clk] -to [get_pins count_0_reg/lden] -delay min
# Detailed timing report that traces clocks at both launch and capture flops with all nets, input pins and a maximum of 1000 paths.report_timing -from [get_clocks clk] -to [get_clocks clk] -path full_clock_expanded -nets \-input_pins -capacitance -transition -max_paths 1000 -nworst 100 -delay max
Switches that are often used in report_timing include
report_timing # Report timing paths[-from from_list] (From pins, ports, nets, or clocks)[-rise_from rise_from_list] (Rising from pins, ports, nets, or clocks)[-fall_from fall_from_list] (Falling from pins, ports, nets, or clocks)[-through through_list] (Through pins, ports, or nets)[-to to_list] (To pins, ports, nets, or clocks)[-rise_to rise_to_list] (Rising to pins, ports, nets, or clocks)[-fall_to fall_to_list] (Falling to pins, ports, nets, or clocks)[-delay_type delay_type] (Type of path delay:Values: max, min, min_max, max_rise, max_fall, min_rise, min_fall)[-nworst paths_per_endpoint] (List N worst paths to endpoint:Value >= 1)[-max_paths count] (Maximum number of paths per path group to output: Value >= 1)[-path_type format] (Format for path report:Values: full, full_clock, short, end, summary, full_clock_expanded)[-input_pins] (Show input pins in path)[-nets] (List net names)[-transition_time] (Display transition time for each pin)[-capacitance] (Display total capacitance for each net)[-slack_lesser_than slack_limit] (Display paths with slack less than this)[-slack_greater_than slack_limit] (Display paths with slack greater than this)
pwd
/proj/verde_pd11/kutukuru/DRMDMA/NL1p0/main/pd/tiles/drmdma_t_TileBuilder_Aug06-1329_drmdma_t_exp1
zless rpts/PtTimScanShiftMultTyptyprc110ctt0p85v110cReRouteSiStp/clock_frequency.rpt.gz
=== TEST_SCLK ===
Period: 4.545 ns
Slack: 0.524 ns
Target: 220 MHz
Actual: 249 MHz
****************************************
Report : timing
-path_type full_clock_expanded
-delay_type max
-input_pins
-nets
-nworst 10
-max_paths 10000
-unique_pins
-group **clock_gating_default**
-transition_time
-capacitance
Design : drmdma_t
Version: D-2009.12-SP2
Date : Thu Aug 12 13:31:32 2010
zless rpts/PtTimFuncTT0p85vtyprc110ctt0p85v110cRouteSiStp/update_timing.log.gz
report_disable_timing
zless rpts/PtTimFuncTT0p85vtyprc110ctt0p85v110cRouteSiStp/tie_fanout.rpt.gz
Total number of violations: 0
zless rpts/PtTimFuncTT0p85vtyprc110ctt0p85v110cRouteSiStp/si_update_noise.rpt.gz
Information: Activating steady state resistance estimation mode for library
forceUnits_tsmc28hp_tt0p85v110c. (NOISE-001) ****************************************
Report : timing
-path_type full
-delay_type max
-input_pins
-nets
-nworst 10
-max_paths 10000
-unique_pins
-transition_time
-capacitance
-crosstalk_delta
Design : drmdma_t
Version: D-2009.12-SP2
Date : Wed Aug 11 12:11:09 2010
zless rpts/PtTimFuncTT0p85vtyprc110ctt0p85v110cRouteSiStp/si_qor.rpt.gz
****************************************
Report : qor
Design : drmdma_t
Version: D-2009.12-SP2
Date : Wed Aug 11 12:13:23 2010
****************************************
Timing Path Group 'async_default' (max_delay/setup)
---------------------------------------------
Levels of Logic: 15
Critical Path Length: 8.99793
Critical Path Slack: -0.50182
Total Negative Slack: -23.37672
No. of Violating Paths: 68
---------------------------------------------
Timing Path Group 'clock_gating_default' (max_delay/setup)
---------------------------------------------
Levels of Logic: 11
Critical Path Length: 45.21947
Critical Path Slack: -0.65381
Total Negative Slack: -1.25667
No. of Violating Paths: 15
---------------------------------------------
Timing Path Group 'JTAG_TCLK' (max_delay/setup)
---------------------------------------------
Levels of Logic: 14
Critical Path Length: 3.20883
Critical Path Slack: 5.23249
Total Negative Slack: 0.00000
No. of Violating Paths: 0
---------------------------------------------
Timing Path Group 'SCLK' (max_delay/setup)
---------------------------------------------
Levels of Logic: 34
Critical Path Length: 1.52422
Critical Path Slack: -0.16275
Total Negative Slack: -295.89784
No. of Violating Paths: 6397
---------------------------------------------
ESCOB
Timing Path Group 'TEMP_PCIE_REFCLK' (max_delay/setup)
---------------------------------------------
Levels of Logic: 9
Critical Path Length: 0.56201
Critical Path Slack: 7.76119
Total Negative Slack: 0.00000
No. of Violating Paths: 0
---------------------------------------------
ESCOB
Timing Path Group 'flop_to_io' (max_delay/setup)
---------------------------------------------
Levels of Logic: 20
Critical Path Length: 1.00056
Critical Path Slack: -0.22456
Total Negative Slack: -11.80751
No. of Violating Paths: 197
---------------------------------------------
ESCOB
Timing Path Group 'io_to_flop' (max_delay/setup)
---------------------------------------------
Levels of Logic: 4
Critical Path Length: 8.78495
Critical Path Slack: -0.34654
Total Negative Slack: -10.26075
No. of Violating Paths: 319
---------------------------------------------
ESCOB
Timing Path Group 'io_to_io' (max_delay/setup)
---------------------------------------------
Levels of Logic: 4
Critical Path Length: 33.55542
Critical Path Slack: 0.03358
Total Negative Slack: 0.00000
No. of Violating Paths: 0
---------------------------------------------
ESCOB
ESCOB
Timing Path Group 'async_default' (min_delay/hold)
---------------------------------------------
Levels of Logic: 3
Critical Path Length: 0.51743
Critical Path Slack: 0.07972
Total Negative Slack: 0.00000
No. of Violating Paths: 0
---------------------------------------------
ESCOB
Timing Path Group 'clock_gating_default' (min_delay/hold)
---------------------------------------------
Levels of Logic: 1
Critical Path Length: 0.48892
Critical Path Slack: 0.08293
Total Negative Slack: 0.00000
No. of Violating Paths: 0
---------------------------------------------
ESCOB
Timing Path Group 'JTAG_TCLK' (min_delay/hold)
---------------------------------------------
Levels of Logic: 2
Critical Path Length: 0.46976
Critical Path Slack: 0.05226
Total Negative Slack: 0.00000
No. of Violating Paths: 0
---------------------------------------------
ESCOB
Timing Path Group 'SCLK' (min_delay/hold)
---------------------------------------------
Levels of Logic: 3
Critical Path Length: 0.62047
Critical Path Slack: 0.01707
Total Negative Slack: 0.00000
No. of Violating Paths: 0
---------------------------------------------
ESCOB
Timing Path Group 'TEMP_PCIE_REFCLK' (min_delay/hold)
---------------------------------------------
Levels of Logic: 2
Critical Path Length: 0.06282
Critical Path Slack: 0.05309
Total Negative Slack: 0.00000
No. of Violating Paths: 0
---------------------------------------------
ESCOB
ESCOB
Cell Count
---------------------------------------------
Hierarchical Cell Count: 3893
Hierarchical Port Count: 208384
Leaf Cell Count: 351585
---------------------------------------------
ESCOB
ESCOB
Area
---------------------------------------------
Design Area: 550031.250000
---------------------------------------------
ESCOB
ESCOB
Design Rule Violations
---------------------------------------------
Total No. of Pins in Design: 1371192
clock_gating_setup Count: 15
max_capacitance Count: 17
min_capacitance Count: 85
max_transition Count: 8724
max_fanout Count: 23
clock_gating_setup Cost: -1.25667
max_capacitance Cost: -0.03828
min_capacitance Cost: -0.01212
max_transition Cost: -281.95796
max_fanout Cost: -23.00000
Total DRC Cost: -306.26503
---------------------------------------------
set_option route_with_si_driven true
set_option route_with_si_post_route_fix true
set_attribute -net {BOUNDBUF_N_1491} -si_post_route_fix true
hey CRPR is Clock Re-convergence Pessimism removal, its computing delay adjustments on the clk network ,as the name says its the removal of pessimism for the clock path .
when you set the timing analysis for BC- WC mode , the same clock path is subjected to both fast op-cond and the slow op-cond,which introduces pessimism .
A setup check at a flip-flop in a circuit ensures that the latest arriving signal at the data pin arrives before the earliest arriving signal on the clock pin. Similarly, a hold check ensures that the earliest arriving data signal arrives after the latest arriving clock signal. The earliest or latest arriving signal on the data pin of a flip-flop is usually triggered by another flip-flop.
If both the clock and the data signals share a portion of the clock network , then for common clock network , a pessimism ( maximum delay - minimum delay ) will be introduced , we need to remove the same ,also if clk source insertion delays are
defined they do count.
On chip variation and CRPR
Posted in Static Timing Analysis by Nigam on the September 27th, 2007
Static timing analysis in a chip is largely dependent on Process, Temperature and Voltage variations (PVT), the cell delays and interconnect delays vary largely with these factors. Hence it is necessary to run timing analysis in both worst and best case operating conditions and ensure we meet setup/hold requirements for the chip.
For worst case corners, we specify the chip running at high temperature, low voltage and a slow process (high cap). For best case corner, the voltage is high, temperature is low and a fast process (low cap). Setup is more problematic in slow corner because of larger cell/interconnect delays and hold is more problematic in the fast corner.
Another factor that needs to be considered during timing analysis is on-chip variation (OCV). On a single chip, there can be variations for two exactly similar gates due to other variables during manufacturing process. This variation can be anywhere between 8-12% and needs to be included in timing analysis for a more accurate and foolproof picture.
To add OCV analysis in Synopsys Primetime, we use timing derate factor for min/max cases (8-12%) as shown below. This specifies that the min paths can be faster than the max paths by 40% !
set_timing_derate –min 0.8 –max 1.2
Next, we use the “on_chip_variation” switch as shown below to enable OCV
set_operating_conditions -analysis_type on_chip_variation
However, if you look at the reports carefully, you will notice that Primetime is overtly pessimistic i.e. if there is a common branch of clock tree between launch and capture flops, Primetime varies this clock tree delay depending on OCV (for example, for setup analysis, it will slow down the common clock tree branch delay for launch flop and will fasten the same branch to capture flop!)
To counter this, Clock Reconvergence Pessimism Removal (CRPR) feature is added in Primetime. CRPR is enabled by using the command below
set timing_remove_clock_reconvergence_pessimism true
By enabling this feature, Primetime looks at the common logic in clock and data path, removes the difference between their max and min delays thus projecting a more realistic picture.
For more details on OCV and CRPR, please refer to the paper at the link below.