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OMAP5912OSKTarget Module
Hardware Reference Guide
Literature Number SPRU715October 2004
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,enhancements, improvements, and other changes to its products and services at any time and to discontinueany product or service without notice. Customers should obtain the latest relevant information before placingorders and should verify that such information is current and complete. All products are sold subject to TI’s termsand conditions of sale supplied at the time of order acknowledgment.
TI warrants performance of its hardware products to the specifications applicable at the time of sale inaccordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TIdeems necessary to support this warranty. Except where mandated by government requirements, testing of allparameters of each product is not necessarily performed.
TI assumes no liability for applications assistance or customer product design. Customers are responsible fortheir products and applications using TI components. To minimize the risks associated with customer productsand applications, customers should provide adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or processin which TI products or services are used. Information published by TI regarding third-party products or servicesdoes not constitute a license from TI to use such products or services or a warranty or endorsement thereof.Use of such information may require a license from a third party under the patents or other intellectual propertyof the third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of information in TI data books or data sheets is permissible only if reproduction is withoutalteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproductionof this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable forsuch altered documentation.
Resale of TI products or services with statements different from or beyond the parameters stated by TI for thatproduct or service voids all express and any implied warranties for the associated TI product or service andis an unfair and deceptive business practice. TI is not responsible or liable for any such statements.
Following are URLs where you can obtain information on other Texas Instruments products and applicationsolutions:
Products Applications
Amplifiers amplifier.ti.com Audio www.ti.com/audio
Data Converters dataconverter.ti.com Automotive www.ti.com/automotive
DSP dsp.ti.com Broadband www.ti.com/broadband
Interface interface.ti.com Digital Control www.ti.com/digitalcontrol
Logic logic.ti.com Military www.ti.com/military
Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork
Microcontrollers microcontroller.ti.com Security www.ti.com/security
Telephony www.ti.com/telephony
Video & Imaging www.ti.com/video
Wireless www.ti.com/wireless
Mailing Address: Texas Instruments
Post Office Box 655303 Dallas, Texas 75265
Copyright 2004, Texas Instruments Incorporated
vRead This First
Preface
Read This First
About This Manual
This document discusses the design of the OMAP5912 target module used inthe OMAP5912 Starter Kit (OSK). It details the design of each aspect of thetarget module. Sufficient detail is provided to show how each componentinteracts and what functions they perform. Additional information is found inthe individual component datasheets.
The OMAP5912 target module is the processor module for theOMAP5912OSK. It provides a means to evaluate the OMAP5912 processorby allowing you to work with the ARM, DAP, and peripherals of the OMAP5912.
How to Use This Manual
The sections that make up this design specification include:
Target module requirements Detailed design Expansion connectors I/O connectors Mechanical specifications
Notational Conventions
This document uses the following acronyms:
Acronym Definition
CFC Compact Flash Controller
DDR Dual Data Rate
Flash Nonvolatile memory
JTAG Joint Test Access Group
OTC OMAP Technology Center
SDR Single Data Rate
SDRAM Synchronous Dynamic Random Access Memory
USB Universal Serial Bus
Information About Warnings
vi
Information About Warnings
This is an example of a warning statement.
A warning statement describes a situation that could potentiallycause harm to you.
The information in a warning is provided for your protection. Please readeach warning carefully.
Related Documentation From Texas Instruments
The following books describe the OMAP devices and related support tools. Toobtain a copy of any of these TI documents, call the Texas InstrumentsLiterature Response Center at (800) 477−8924. When ordering, pleaseidentify the book by its title and literature number.
OMAP5912 Applications Processor (literature number SPRS231) datasheet contains the electrical and timing specifications for theOMAP5912™ device, as well as signal descriptions for all of the availablepackages.
TPS65010: Power and Battery Management IC for Li-Ion Powered Sys-tems (literature number SLVS149) data sheet contains the electrical andtiming specifications for the TPS65010™ device.
Documentation that describes the OMAP5912 device, related peripherals,and other technical collateral, is available in the OMAP5912 Product Folderon TI’s website: www.ti.com/omap5912.
Information About Warnings / Related Documentation From Texas Instruments
Related Documentation
viiRead This First
Related Documentation
256M bits DDR Mobile RAM EDK2516CBBH(16M words x 16 bits) (Docu-ment No. E0300E70) data sheet, Elpida Memory, Inc., published Octo-ber 2003 (K) Japan Ver 7.0
8Mx16 Mobile SDRAM 54CSP (K4M28163PD-R(B)G/S) data sheet, Sam-sung Electronics, published December 2002 Revision 1.3
Universal Serial Bus Specification Revision 2.0 Compaq Computer Corpo-ration, Hewlett−Packard Development Company, Intel Corporation,Lucent Technologies, Microsoft Corporation, NEC Corporation, PhilipsElectronics, Revision 2.0 April 27, 2000
Open HCI—Open Host Controller Interface Specification for USB, Com-paq Computer Corporation, Release 1.0a October 1996
FCC Warning
This equipment is intended for use in a laboratory test environment only. Itgenerates, uses, and can radiate radio frequency energy and has notbeen tested for compliance with the limits of computing devices pursuantto subpart J of part 15 of FCC rules, which are designed to providereasonable protection against radio frequency interference. Operation ofthis equipment in other environments may cause interference with radiocommunications, in which case the user at his own expense will berequired to take whatever measures may be required to correct thisinterference.
Trademarks
74LVC139 is a trademark of Phillips Electronics.
AT93C46 is a trademark of Atmel Corporation.
EDK2516CBBH is a trademark of Elpida Memory, Inc.
FDC6331L is a trademark of Fairchild.
K4M28163PD-R(B)G/S) is a trademark of Samsung Electronics.
LAN91C96 is a trademark of SMSC.
OMAP, OMAP5912, SN74LVC139, SN74LVC244AGQN, TLV320AIC23,TPS65010, TPS71501 are trademarks of Texas Instruments Incorporated.
QFlash and MT28F128J3 are trademarks of Micron Technologies, Inc.
RC28F320J3 and Stata Flash are trademarks of Intel Corporation.
Related Documentation / FCC Warning / Trademarks
viii
Contents
ix
Contents
1 OMAP5912 Target Module Major Components 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the design of the major components included on the OMAP5912 target module.
1.1 OMAP5912 Target Module Summary 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Memory Map 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2.1 Flash Memory Bus Memory Map 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2.2 SDRAM Memory Map 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 OMAP5912 Processor 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.1 OMAP5912 Processor 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.2 Clock Interface 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.3 Reset Interface 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.4 Power Connections 1-13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3.5 Configuration Pins 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Power Management 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.1 Block Diagram 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.2 Power Budget 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.3 TPS65010 1-20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.4 Digital Current Input 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.5 SDRAM Voltage 1-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.6 3.3 V Supply 1-25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.7 3 V Supply 1-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.8 Control Interface 1-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.9 Real Time Clock Power 1-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.10 DSP Voltage Control 1-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.11 DLL Voltage 1-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.12 Core Voltage 1-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4.13 Battery Mode 1-39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Flash Memory 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.1 Supported Configurations 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.2 Supported FLASH Devices 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.3 FLASH Circuit Design 1-42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.4 Address Bus 1-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.5 Data Bus 1-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.6 Control Signals 1-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.7 Address Decode Logic 1-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5.8 General-Purpose Mode Support 1-46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
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1.6 DDR SDRAM 1-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.1 DDR SDRAM Circuit Design 1-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6.2 Elpida EDK2516CBBH DDR Device 1-49. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Audio Codec 1-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.1 Audio CODEC Design 1-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.2 Audio Inputs 1-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.3 Audio Outputs 1-52. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.4 Clocking 1-53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.5 Power 1-55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.7.6 OMAP5912 Interface 1-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Compact Flash 1-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.1 Integrated Interface 1-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.2 Compact Flash Interface Signals 1-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.3 CFLASH.IREQ 1-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.4 Address Decode Logic 1-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.5 Data Bus Interface 1-61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8.6 Power interface 1-61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 JTAG/Multi-ICE Interface 1-62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.1 JTAG/Multi-ICE Features 1-62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.9.2 Design Description 1-62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 USB Port 1-64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.1 USB Features 1-64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.10.2 Design Description 1-64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11 Serial Port 1-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11.1 Features 1-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.11.2 Design Description 1-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.12 Ethernet 1-69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.12.1 Ethernet Circuit Design 1-69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.12.2 Interrupt 1-70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.12.3 Memory Address Decode 1-70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.12.4 LAN91C96 1-71. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.12.5 Crystal 1-72. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.12.6 Output Section 1-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.12.7 EEPROM 1-74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.12.8 Status LEDS 1-75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Expansion Connectors 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the type and pinout of the expansion connectors. Describes the multiple functionsof the connector pins.
2.1 Connector A 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Connector B 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Connector C 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.4 Connector D 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5 Connector Specification 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
xiContents
3 I/O Connectors 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Defines the pin outs of each of the I/O connectors on the OMAP5912 target module.
3.1 Serial 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Ethernet 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.3 JTAG 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.4 Multi-ICE 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.5 DC Power 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 Compact Flash 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.7 Headphones 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.8 Line In 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.9 Microphone In 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.10 USB Host 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.11 USB Client Adapter 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 Mechanical Specifications 4-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes the physical requirements for each of the card types.
4.1 OMAP5912 Target Module Card 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Component Locations 5-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides component locations on the OMAP5912 target module.
5.1 Key Components 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Connectors and Jumpers 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 Indicators 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A Component Locations A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Illustrates the location of components on the target module board.
A.1 Top Side Component Locations A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A.2 Bottom Side Component Locations A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B OMAP5912 Target Module Dimensions B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides the board dimensions of the OMAP5912 target module.
C OMAP5912 Target Module Schematics C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Provides the schematics for the OMAP5912 target module.
D Current Measurement Procedures D-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Describes how to use the test points on the target module to take current measurements.
D.1 Basic Principle D-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.2 Basic Measuring Techniques D-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D.3 Connection Methods D-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.3.1 Connecting a Voltmeter to Measure Voltage Drop D-3. . . . . . . . . . . . . . . . . . . . . . . . D.3.2 Connecting an Oscilloscope to Measure Voltage Drop D-4. . . . . . . . . . . . . . . . . . . . D.3.3 Connecting an Oscilloscope to Trigger Data Collection D-5. . . . . . . . . . . . . . . . . . .
Figures
xii
Figures
1−1 OMAP5912 Target Module Block Diagram 1-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2 OMAP5912 Clock Inputs 1-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3 OMAP5912 Clock Inputs 1-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4 OMAP5912 Reset Interface 1-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5 OMAP5912 Power Connections 1-14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−6 OMAP5912 Configuration Pins 1-16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−7 Power Management Block Diagram 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−8 Digital Current Input Design 1-22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−9 SDRAM Power Design 1-24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−10 3.3 V Power Design 1-26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−11 3 V Power Design 1-28. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−12 TPS65010 Control Interfaces 1-30. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−13 Real Time Clock Power Design 1-33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−14 Real Time Clock Voltage Adjustment 1-34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−15 DSP Voltage Control 1-35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−16 DLL Voltage Circuit 1-36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−17 DLL Voltage Adjustment 1-37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−18 Core Voltage Circuit 1-38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−19 Optional Battery Configuration 1-40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−20 FLASH Circuitry Design 1-43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−21 FLASH Decode Logic 1-44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−22 Mobile DDR SDRAM Design 1-48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−23 AIC23 Audio CODEC Design 1-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−24 AIC23 Audio Inputs 1-51. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−25 AIC23 Audio Outputs 1-53. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−26 AIC23 Clocking Options 1-54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−27 AIC23 Power Section 1-55. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−28 AIC23 OMAP5912 Interface 1-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−29 Compact Flash Socket Design 1-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−30 CFLASH_EN Signal Decode Logic 1-60. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−31 JTAG Interface Design 1-63. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−32 USB Host Design 1-64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−33 Serial Port Interface 1-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−34 10 Mb Ethernet Design 1-69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−35 Ethernet Address Decode Logic 1-70. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−36 Ethernet Output Section 1-73. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−37 Ethernet EEPROM 1-74. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
xiiiContents
2−1 Expansion Connector 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1 JTAG Pinout 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2 Multi-ICE Connector Pin Out 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3 DC Power Jack Pin Out 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4 Compact Flash Connector 3-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5 Headphone Pin out 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6 Line In Pin Out 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7 Microphone Jack Pin Out 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−8 USB Client Adapter 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−1 OMAP5912 Target Module Top Side 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4−2 OMAP5912 Target Module Back Side 4-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−1 OMAP5912 Target Module Key Top Side Components 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−2 OMAP5912 Target Module Connectors 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5−3 OMAP5912 Target Module Indicators 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D−1 Connecting Voltmeter to Measure Voltage D-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D−2 Connecting Oscilloscope to Measure Voltage D-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D−3 Connecting Oscilloscope for Data Collection D-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
xiv
Tables
1−1 OMAP5912 Target Module Components 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−2 Flash Bus Memory Map 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−3 Flash Memory Map Configurations 1-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−4 SDRAM Memory MAP 1-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−5 OMAP5912 Target Module Power Budgets 1-19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−6 FLASH Configurations 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−7 Supported FLASH Devices 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−8 Flash Address Decode Resistor Options 1-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−9 Flash Chip Select Resistor Options 1-45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−10 AIC23 I2C Address Definition 1-56. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−11 OMAP5912 Compact Flash Interface 1-59. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−12 Compact Flash Memory Mapping 1-61. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−13 Ethernet Status LEDs 1-75. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1 Expansion Connector A Pinout 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 Expansion Connector B Pin Out 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3 Expansion Connector C Pin Out 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4 Expansion Connector D Pin Out 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1 Serial Connector Pin out 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2 Ethernet Pin out 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−3 Compact Flash Connector Pin Out 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−4 Headphone Pin out 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−5 Line In Pin Out 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−6 Microphone Input Pin Out 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−7 USB Host Pinout 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
OMAP5912 Target Module Major Components
The following sections provide a detailed description of the design of the majorcomponents of the OMAP5912™ target module.
Topic Page
1.1 OMAP5912 Target Module Summary 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Memory Map 1-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.3 OMAP5912 Processor 1-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.4 Power Management 1-18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 Flash Memory 1-41. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.6 DDR SDRAM 1-47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.7 Audio Codec 1-50. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.8 Compact Flash 1-58. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.9 JTAG/Multi-ICE Interface 1-62. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.10 USB Port 1-64. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.11 Serial Port 1-67. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.12 Ethernet 1-69. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1
OMAP5912 Target Module Summary
1-2
1.1 OMAP5912 Target Module Summary
Table 1−1 lists the major components for the OMAP5912 target module.
Table 1−1. OMAP5912 Target Module Components
Component Description Comments
Processor
OMAP5912 GDY Package 1.0mm pitch
SDRAM
32MB Mobile DDR 1.8V Only
FLASH
NOR Strata 32MB Expandable to 64MB
Power Management
DC Input DC Jack Wall supply, 5V,3W, Regulated
Status LEDs Power good User defined
Low Power Option
Power on reset
MPU Reset Via switch
Audio CODEC
Audio CODEC AIC23
Line-In 3.5mm Jack
Headphone Out 3.5mm Jack
MIC In 3.5mm Jack
Serial Ports
RS232 DB9 Male Tx, Rx
USB Host 250ma power USB Type B
Ethernet 10Mb RJ45, status LEDs
Expansion
Compact Flash Type I and Type II Use integrated controller
Expansion Connectors All signals except SDRAM Support Expansion Cards
OMAP5912 Target Module Summary
1-3OMAP5912 Target Module Major Components
Table 1−1. OMAP5912 Target Module Components (Continued)
Component CommentsDescription
Debugging
JTAG 14 Pin
Multi-ICE 20 Pin TRST polarity jumper
Form Factor
Small as practical Stackable
Figure 1−1 is the high level block diagram of the OMAP5912 target moduledesign.
OMAP5912 Target Module Summary
1-4
Figure 1−1. OMAP5912 Target Module Block Diagram
DEC
Ethernet RJ45
EXP
A
3.3 V
NORflash
Compactflash
E
B
PX
LVL DB9
H
L
M
AIC23USB
P
PWR
SWCore
3.3 V3VASDRAM
LDODC
C
P
EX
JTAG
I
EC
U
P
D
XE
MobileDDR
OMAP5912
SDRAMVLYNQ
LCD
JTAG
DSP
FLASH
TPS65010
RTC
SDRAM
Memory Map
1-5OMAP5912 Target Module Major Components
1.2 Memory Map
The memory map of the OMAP5912 target module contains Flash bus andSDRAM memory.
1.2.1 Flash Memory Bus Memory Map
Table 1−2 defines the Flash bus or EMIFS (Expansion Memory InterfaceSlow) memory map. The Compact Flash interface has an option in the designto move the address space to the chip select (CS) CS2 region. This is thedefault location. Refer to section 1.8, Compact Flash, for more detail.
Table 1−2. Flash Bus Memory Map
CS Type Start End Bytes
CS1A Not Used 0400 2000 047F FFFF 8M Can be used on an expansion board.
Ethernet 0480 0000 04FF FFFF 8M
Not Used 0500 0000 057F FFFF 8M Can be used on an expansion board.
Not Used 0580 0000 05FF FFFF 8M Can be used on an expansion board.
CS1B Not Used 0600 0000 07FF FFFF 32M Can be used on an expansion board.
CS2 Compact FlashMemory
0800 0000 0800 07FF 2K When Compact Flash space is used,CS2 cannot be used for any othermemory.
Compact FlashAttrib
0800 0800 0800 0FFF 2K When Compact Flash space is used,CS2 cannot be used for any othermemory.
CF I/O 0800 1000 0800 17FF 2K When Compact Flash space is used,CS2 cannot be used for any othermemory.
CS3 Flash Memory 0C00 0000 0FFF FFFF 64M Can be used on an expansion board.
The flash memory in the CS3 region has four possible configurations as shownin Table 1−3.
Memory Map
1-6
Table 1−3. Flash Memory Map Configurations
(a) 4 MB Mode, Supports 2 4 MB Memory Parts, 8 MB Total
CS Type Start End Bytes
CS3 FLASH Slot 1 0C00 0000 0C3F FFFF 4M Can be used on an expansion boardvia FLASH.DIS pin.
FLASH Slot 2 0C40 0000 0C7F FFFF 4M Can be used on an expansion boardvia FLASH.DIS pin.
Not Used 0C80 0000 0FFF FFFF 56M Can be used on an expansion board.
(b) 8 MB Mode, Supports 2 8 MB Memory Parts, 16 MB Total
CS Type Start End Bytes
CS3 FLASH Slot 1 0C00 0000 0C7F FFFF 8M Can be used on an expansion boardvia FLASH.DIS pin.
FLASH Slot 2 0C80 0000 0CF8F FFFF 8M Can be used on an expansion boardvia FLASH.DIS pin.
Not Used 0CD0 0000 0FFF FFFF 48M Can be used on an expansion board.
(c) 16 MB Mode, Supports 2 16 MB Memory Parts, 32 MB Total Default Mode
CS Type Start End Bytes
CS3 FLASH Slot 1 0C000 0000 0CFF FFFF 16M Can be used on an expansion boardvia FLASH.DIS pin.
FLASH Slot 2 0D00 0000 0DFF FFFF 16M Can be used on an expansion boardvia FLASH.DIS pin.
Not Used 0E00 0000 0FFF FFFF 32M Can be used on an expansion board.
(d) 32 MB Mode, Supports 2 32 MB Memory Parts, 64 MB Total
CS Type Start End Bytes
CS3 FLASH Slot 1 0C000 0000 0DFF FFFF 32M Can be used on an expansion boardvia FLASH.DIS pin.
FLASH Slot 2 0E00 0000 0FFF FFFF 32M Can be used on an expansion boardvia FLASH.DIS pin.
The OMAP5912 target module supports multiple configurations of NORFLASH that can be loaded with various devices to create the differentconfigurations. For more information on the different configurations refer tosection 1.5, Flash Memory.
Memory Map
1-7OMAP5912 Target Module Major Components
1.2.2 SDRAM Memory Map
A single mobile DDR (Double Data Rate) SDRAM (Synchromous DynamicRandom Access Memory) device is provided on the OMAP5912 targetmodule. Table 1−4 defines the memory map for the DDR SDRAM. The 32MBconfiguration is the default mode.
Table 1−4. SDRAM Memory MAP
Mode Start End Bytes
32MB 1000 0000 11FF FFFF 32M Default configuration
64MB 1000 0000 13FF FFFF 64M To change the DDR configuration, thepart on the OMAP5912 target modulemust be replaced.
Reserved 1800 0000 18FF FFFF
OMAP5912 Processor
1-8
1.3 OMAP5912 Processor
This section covers the part of the design that is specific to the OMAP5912processor. The following components are discussed in this section:
OMAP™ processor Clock interface Reset circuitry Power connections Configuration pins
1.3.1 OMAP5912 Processor
There are two different packages available for the OMAP5912:
ZDY Plastic BGA ZZG Plastic BGA
The ZDY and ZZG packages are 289-pin devices. The ZZG package is a muchsmaller package and has a finer pitch. The OMAP5912 target module uses theZDY package. Figure 1−2 shows the pinout of the ZDY package.
OMAP5912 Processor
1-9OMAP5912 Target Module Major Components
Figure 1−2. OMAP5912 Clock Inputs
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
A
B
C
D
E
F
G
H
J
K
LM
N
P
R
T
U
Bottom view
OMAP5912 Processor
1-10
1.3.2 Clock Interface
Figure 1−3 shows the design of the crystals for the OMAP5912 target module.
Figure 1−3. OMAP5912 Clock Inputs
N8N14N12
R9
P10
R14T15R13
U17M10
N11U16T14P13
U10U11P2
T11
T17R2
BFAILOSC1_IN
CLK32K_INOSC1_OUTOSC32K_INOSC32K_OUTRTC_ON_OFFPWRON_RESETMPU_RSTRST_OUTRESET_MODECONFTDOTRSTTMSTDITCKRTCKEMU0EMU1
U3MCLK
MCLKREQT7
BCLKREQBCLK
R12L10
U3F
OMAP5912−289
R3020
VDD 3V3
R3030
3
2 5C13
10 pF
10 V
10 V10 pF
C11
Y2 SSP−T6
32.768 MHz
R301NO
POP
R46
10 pF 10 V
C102
10 pF 10 V
C5
BFAIL
VDD_SDRAM
VCC
GND
OUT
EN
4
2C1010.1 µF10 V
3
10.1 µF10 V
C19
VDD_3V3L9
Ferrite bead M2301_ND
R304 20K n.m.
Clockresetand
JTAGn.m 0603
(9)
Y1CS10_12
0000MABJ
U22DK/SG8002CAPCB−ND(32.76KMHz)
VSSVSSVSSVSSVSS
VSS
VSS
VSS
VSS
VSSVSSVSSVSS
VSS
VSS
VSS
VSS
VSS
VSS
E5E13
F12F6
H9H8G11G7
M6L11L7K10K9K8J9H10
N5N13
M12
RSVDE14
CVDDCVDDCVDDCVDDCVDD1CVDD2CVDD2CVDD2CVDD3CVDD3CVDD3CVDD3CVDD4CVDDACVDD5
CVDD9
CVDD8
CVDD7
CVDD6
CVDD5
CVDD5
CVDD5
CVDD1
CVDD4
CVDD4CVDD4
CVDD4
CVDD2CVDD3
CVDD1
CVDD10LDO.VDD
K5M7
C11T16
G9H7
G8T3
A9P17
C14
L9
H11G10
K11J10
G1
T13T10
R10M13J15
L3
D8D6
B1D7
T6D11
U2G12
H1
Powerand
ground
R45n.m., o603
The 32 KHZ clock has two options provided on the board, crystal or externaloscillator. The build of the OMAP5912 target module uses the externaloscillator.
OMAP5912 Processor
1-11OMAP5912 Target Module Major Components
1.3.2.1 Crystal Configuration
In the crystal configuration for the 32KHZ clock, an external crystal, Y2, is usedfor the clock source. The crystal is connected across pins U10 and U11.Because the crystal is used, pin T11 must be grounded. Capacitors C11 andC13 terminate the crystal to ground. These capacitors must be connecteddirectly to pin H8 of the OMAP5912, which is internally connected to ground.The length of this connection should be kept as short as possible. As an option,R45 can provide a direct connection to ground, if needed. It is not neededunder the current design.
In this configuration, the following components are not to be installed:
C101 L9 U22 R304 R302 R303
1.3.2.2 Oscillator Configuration
In the oscillator configuration, U22 provides the 32KHZ clock. L9 and C101provide filtering into the power rail of the oscillator. R304 provides a pull up tothe enable pin of the oscillator. R302 and R303 provide the termination of thecrystal pins on the OMAP5912 as required when using the external oscillator.
In this configuration, the following components are not installed:
C11 C13 Y2 R301
1.3.2.3 12 MHZ Clock
Crystal Y1 provides the 12MHZ function for the OMAP5912. Capacitors C5and C10 provide termination for Y1. An external oscillator can be used for the12MHZ clock. This option is not supported in the OMAP5912 target moduledesign.
In addition, you can use a 13MHZ crystal in place off the 12MHZ crystal. TheOMAP5912 target module is not supplied with a 13MHZ crystal. However, youcan replace the 12MHZ crystal if needed for your application.
OMAP5912 Processor
1-12
1.3.3 Reset Interface
Figure 1−4 defines the use of the three pins that make up the reset functionson the OMAP5912.
The nPWRON_RESET is an input to the OMAP5912 that, when taken low,resets the entire OMAP5912.
The MPU_RESET signal is an input to the OMAP5912 that when taken low,resets the ARM core on the OMAP5912.
Figure 1−4. OMAP5912 Reset Interface
R165R166
R168R167
0
0
N8
N14
N12
R51R50
R295 47K10K10K
(9) ON_OFF
(6) nPOWRON_RESET
(6) MPU_nRESET
(9) nRESET.OUT
VDD_3V3
R44
n.m..0603R9
R530
VDD_3V3
5912 RST_MODE
P10
R5210K
R14T15R13
U17M10
N11U16T14P13
U10U11P2
T11
T17R2
BFAILOSC1_INCLK32K_INOSC1_OUTOSC32K_INOSC32K_OUT
RTC_ON_OFF
PWRON_RESET
MPU_RST
RST_OUT
RESET_MODECONFTDOTRSTTMSTDITCKRTCKEMU0EMU1
U3MCLK
MCLKREQT7
BCLKREQBCLK
R12L10
U3F
OMAP5912−289
0
0
Clock,Reset,
and JTAG
There are four resistors on the module, which based on the way they areloaded, provide several options to configure the reset signals. The resetsignals for the nPWRON_RESET and the nMPU_Reset are generated by theTPS65010™ power management device. Both of these signals are open drainoutputs. For more information, refer to section 1.4.3, TPS65010.
OMAP5912 Processor
1-13OMAP5912 Target Module Major Components
Both the nPWRON_RESET and nMPU_RESET signals are needed togenerate an nPWRON_RESET signal into the OMAP5912. The reset switchon the TPS65010 only generates as nMPU_RST. Because only thenPWRON_RESET signal on the OMAP5912 is used, you need to make surethat both resets from the TPS65010 generate only the nPWRON_RESETsignal. This is done by loading the resistors as follows:
R165, connecting nPWRON_RESET to nPWRON_RESET of theOMAP5912
R166, connecting nMPU_RST to the nPWRON_RESET of theOMAP5912.
R167 and R168 are not installed.
This allows both reset signals from the TPS65010 to generate only annPWRON_RESET into the OMAP5912.
1.3.4 Power Connections
Figure 1−5 shows the power connections on the OMAP5912 processor. Eachof these is discussed in the following paragraphs.
OMAP5912 Processor
1-14
Figure 1−5. OMAP5912 Power Connections
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
E5E13
F12F6
H9H8G11G7
M6L11L7K10K9K8J9H10
N5N13
M12
RSVDE14
CVDD
CVDD
CVDD
CVDD
CVDD1
CVDD2
CVDD2
CVDD2
CVDD3
CVDD3
CVDD3
CVDD3
CVDDDLL
CVDDA
CVDDRTC
DVDD9
DVDD8
DVDD7
DVDD6
DVDD5
DVDD5
DVDD5
DVDD1
DVDD4
DVDD4
DVDD4
DVDD4
DVDD2
DVDD3
DVDD1
DVDDRTC
LDO.VDD
K5M7
C11T16
G9H7
G8T3
A9P17
C14
L9
H11G10
K11J10
G1
T13T10
R10M13J15
L3
D8D6
B1D7
T6D11
U2G12
H1
Powerand
ground
VDD_CORE
VDD_DSP
VDD_RTC
VDD_3V3
VDD_SDRAM
VDD_3V3
VDD_3V3
C151uF, 10 V, X5R, 0402
U3G
OMAP5912−289
C120.01 µF10 V
R47 10VDD_DLL
C8010 µF10 V
R48 10
10 V10 µFC80
C840.01 µF10 V
VDD_DSP
0.01 µFC17
10 V
VDD_3V3
C18
10 V0.01 µF
VDD_3V3
C16
10 V0.01 µF
VDD_3V3
The VDD_DLL power on the OMAP5912 can be sensitive to noise. Therefore,two RC circuits are used to provide enhanced noise immunity. R47 and C12provide a filter for the CVDDLL pin, which is the core voltage supply pin for theDLL. R48 and C14 perform the same function for the CVDDA pin, whichprovides the power to the DLL itself. Capacitor C80 provides low frequencyfiltering for the DLL supply. Power for the DLL is supplied by a separate LDO,U5. For information, refer to section 1.4, Power Management.
OMAP5912 Processor
1-15OMAP5912 Target Module Major Components
VDD_CORE is the main supply to the internal core voltages of the OMAP5912and is a nominal 1.6 V but can be set to 1.1 V−1.5 V under software controlthrough the TPS65010. Refer to section 1.4, Power Management, for moredetails. Filtering of the voltage is supplied by the bypass and filter capacitors.
VDD_DSP is the supply pin for the DSP in the OMAP5912. Power for the DSPis supplied through U11. U11 should be placed as close as possible to theOMAP5912 in the layout process. U11 can be disabled by taking GPIO4 of theTPS65010 low.
VDD_RTC supplies power to the Real Time Clock inside the OMAP5912. Poweris supplied by U9. Refer to section 1.4.9, Real Time Clock Power, for a moredetailed description.
VDD_3V3 is the 3.3 V supply for the OMAP5912. This supplies power to thevarious I/O function pins as well as the FLASH bus.
VDD_SDRAM supplies voltage to the output pins for the SDRAM interface.
Pin H1 on the OMAP5912 processor is the output of a regulated supply thatis delivered by an embedded LDO to the DPLL macros. The regulated supplyis available on the OMAP5912 at pad H1. A decoupling capacitor of 1 µF mustbe connected externally between LDO.FILTER and ground.
All power is connected to a common ground. All leads from the ground pinson the OMAP5912 to the actual ground plane are kept as short as practical.
OMAP5912 Processor
1-16
1.3.5 Configuration Pins
There are a group of pins that are used to configure the OMAP5912 processorbased on each individual application. Figure 1−6 shows these pins.
Figure 1−6. OMAP5912 Configuration Pins
N8
N14
N12
R9
P10
R14
T15
R13
U17
M10
N11
U16
T14
P13
U10
U11
P2
T11
T17
R2
BFAIL
OSC1_IN
CLK32K_IN
OSC1_OUT
OSC32K_IN
OSC32K_OUT
ON_OFF
PWRON_RESET
MPU_RST
RST_OUT
VSS
CONF
TDO
TRST
TMS
TDI
TCK
RTCK
EMU0
EMU1
U3MCLK
MCLKREQT7
BCLKREQ
BCLKR12
L10
U3F
OMAP5912−289
BFAIL
ON_OFF
n.m., 0603R44VDD_3V3
R5210K
Clock,reset,and
JTAG
BFAIL is the battery power failure and external FIQ interrupt input. BFAIL canbe used to gate certain input pins when battery power is low or failing. The pinsthat can be gated are configured via software. This pin can also optionally beused as an external FIQ interrupt source to the MPU. The function of this pinis configurable through software.
OMAP5912 Processor
1-17OMAP5912 Target Module Major Components
On the OMAP5912 target module, this pin connects to pin 54 of ExpansionConnector B. It is not used by any circuitry on the OMAP5912 target moduleand is free to be used by an expansion card.
ON_OFF controls the internal RTC. When pulled low, the RTC is disabled. Aresistor insures that the RTC is enabled by pulling the pin to VDD_RTC. This pinalso connects to pin 56 of Expansion Connector B for use by the expansioncards as needed either as a way to disable the internal RTC or to be used asone of its optional features. Refer to the OMAP5912 Application Processordata sheet (literature number SPRS231) for more detail on how the pin can beused.
CONF must be tied low through a 10K Ω resistor to put the OMP5912 in theoperational mode. Pulling this pin high puts the device in the test mode. Thetest mode is not used on the OMAP5912 target module design.
Power Management
1-18
1.4 Power Management
This section covers the design of the power management circuitry for theOMAP5912 target module. Covered in this section are these components:
Block diagram Power budgets TPS65010 DC input SDRAM voltage VDD_3V3 supply VDD_3V supply
1.4.1 Block Diagram
Figure 1−7 is the high level block diagram of the Power Management Circuitry.
Figure 1−7. Power Management Block Diagram
RTC
DLL
DSP
VDD_RTC
VDD_DLL
VDD_DSP
Core
3.3 V
3 V
SDRAM
DCinput
Control I/F
TPS65010
The TPS65010 is the power management device used.
The DC Input block is the interface to the external dc power supply.
The SDRAM rail provides power to the SDRAM device on the board.
The 3.3 V rail is the main power rail to the 3.3 V bus on the board including theFLASH memory devices.
The 3 V rail supplies power to the AIC23 audio CODEC.
Power Management
1-19OMAP5912 Target Module Major Components
The control interface contains the setting of the configuration pins and the I2Cinterface through which the OMAP51912 communicates to the TPS65010.
The RTC block provides power to the Real Time Clock voltage input of theOMAP5912.
The DLL block provides a separate power rail to the internal DLL power of theOMAP5912.
The DSP block provides the ability to control the power to the DSP block of theOMAP5912.
The Core voltage rail supplies power to the core components in theOAMP5912 processor.
Each of these blocks is discussed in more detail in the following sections.
1.4.2 Power Budget
Table 1−5 defines the estimated power budget for each section of theOMAP5912 target module. The design of the power circuitry is based on theseparameters. These are very rough worst case estimates with a lot of headroom allowed. Actual power consumption depends on the clock speed andapplications that are being run.
Table 1−5. OMAP5912 Target Module Power Budgets
Capacity (Ma)−−−−−−> 2500 400 1000 200 200
CORE 3V3 RTC DLL 3 V SDRAM
Device Voltage DC_IN 1.6 V 3.3 V 1.8 V 1.8 V 3.0 V 1.8 V Comments
TPS65010(Ma) VINMAIN 932.3
TPS65010(Ma) VINCORE 206
TPS65010(Ma) VIN1 23
TPS65010(Ma) VIN2 75
TPS65010(Ma) AC 500 Only when batteryconnected
OMAP5912(Ma) 206 5 5 Estimated
OMAP5912(Ma) 85 I/O Voltage
AIC23(Ma) 23
Flash (2) (Ma) 160 Worst case all Devices
Note: The 3.3 V expansion supply is limited to 125ma and is for running a single expansion card. If more power is needed, thedc input should be used.
Power Management
1-20
Table 1−5. OMAP5912 Target Module Power Budgets (Continued)
Capacity (Ma)−−−−−−>
Comments
20020010004002500
Device Comments
SDRAM3 VDLLRTC3V3CORE
DC_INVoltageDevice Comments1.8 V3.0 V1.8 V1.8 V3.3 V1.6 VDC_INVoltage
DDR SDRAM(Ma) 75 Estimated
SN74LVC139(Ma) 2 Conservative est.
SN74CBTLV3257(Ma) 0.3
LEDS (4) (Ma) 40
LAN91C96(Ma) 64
AT93C46(Ma) 2
MAX3221(Ma) 10 Estimated
SN74AHC1G04DCKR(Ma) 10
SN74LVC244AGQN(Ma) 24 Estimated
Compact Flash(Ma) 400 Limited to 500mA.Spec @ 400ma
Expansion Slot(Ma) 500 125(1)
USB Host(Ma) 250 Shuts down @ 440ma.Spec @ 250ma
(Ma) Totals 2486.3 206 922.3 5 5 23 75
(Ma) Remaining 13.7 194 67.7 177 125
Note: The 3.3 V expansion supply is limited to 125ma and is for running a single expansion card. If more power is needed, thedc input should be used.
1.4.3 TPS65010
The TPS65010 is a power management device specifically designed for usewith the OMAP family of processors. Its features are:
Linear charger management for single Li-Ion Li-Polymer cells
Dual input ports for charging from USB or from wall plug; handles100-mA/500-mA USB requirements
Charge current programmable through external resistor
1 A, 95% efficient step-down converter for I/O and peripheral components(VMAIN)
Power Management
1-21OMAP5912 Target Module Major Components
400 mA, 90% efficient step-down converter for processor core (VCORE)
2 × 200-mA LDOs for I/O and peripheral components, LDO enable via bus
Serial interface compatible with I2C; supports 100 kHz, 400-kHz operation
LOW_PWR pin to lower or disable processor core supply voltage in deepsleep mode
70-µA quiescent current
1% reference voltage
Thermal shutdown protection
HBM and CDM capabilities of 1 kV at VIB, PG, and LED2 pins
The TPS65010 is an integrated power and battery management integratedcircuit (IC) for applications powered by one Li-Ion or Li-Polymer cell, whichrequire multiple power rails. Both step-down converters enter a low powermode at light load for maximum efficiency across the widest possible range ofload currents.
The LOW_PWR pin allows the core converter to lower its output voltage whenthe application processor goes into deep sleep. The TPS65010 also integratestwo 200-mA LDO voltage regulators, which are enabled through the serialinterface. Each LDO operates with an input voltage range between 1.8 V and6.5 V, allowing them to be supplied from one of the step-down converters ordirectly from the battery.
The TPS65010 also has an integrated and flexible Li-Ion linear charger andsystem power management. It offers integrated ac-adapter supplymanagement with autonomous power-source selection, power FET andcurrent sensor, high accuracy current and voltage regulation, charge status,and charge termination. The USB mode is for the charger and is not used inthis particular design. In the ac-adapter configuration an external resistor setsthe maximum value of charge current.
The battery is charged in three phases: conditioning, constant current, andconstant voltage. Charge is normally terminated based on minimum current.An internal charge timer provides a safety backup for charge termination. TheTPS65010 automatically restarts the charge if the battery voltage falls belowan internal threshold. The charger automatically enters sleep mode when thedc supply is removed.
Note: Battery Not Supported with OMAP Starter Kit
While the battery can be added to the OSK, it is not supported with the OSK.You need to add a battery as needed. For more information, see section1.4.13, Battery Mode.
Power Management
1-22
The serial interface can be used for dynamic voltage scaling, for collectinginformation on and controlling the battery charger status, for optionallycontrolling two LED driver outputs, masking interrupts, or for disabling andsetting the LDO output voltages. The interface is compatible with thefast/standard mode I2C specification allowing transfers at up to 400 kHz.
1.4.4 Digital Current Input
Figure 1−8 shows the design of the dc input portion of the board.
Figure 1−8. Digital Current Input Design
DC 5V in,regulated
center positive123
P7DC8
F12.5A_QuickBlow
2DC_IN 1 DC_IN_FUSED
1
TP17R14
10, 0603
R68
ESDring
Delete D9use PG.
R6910, 0805
1
2
3
HDR3,n.m.
JP2
VINCORE
VINMAIN_A
VINMAIN_B
VCC
TPS65010
PG5
5
8
7
6
C7622 µF, 10V,X7R, 0402
12 R70
330, 0603DC
D9
LED,GRN
C77
X5R, 04021 µF, 10V,
R9510, 0603
D1
SMCJ6.0A
1
2
C26220 µF,6.3V,AE
DC
Power Management
1-23OMAP5912 Target Module Major Components
P7 is the main power jack for the external dc supply. The external supply isspecified to be a regulated 5 V. A regulated 5 V is required for the USBinterface. In series with the dc input is a 2.5A quick blow fuse in a 1206package. This fuse is a protection device in the case that the external + 5 Vsupply does not shut down properly. Diode D1 provides an additionalprotection function that insures that the input dc voltage cannot get over 6 V.C26 provides filtering of the dc input. C76 is required by the TPS65010 andshould be placed as close to the device as possible.
JP2 is an option jumper that is not normally installed. Its purpose is to allowfor the selection of either the dc input mode or the battery mode. In the batterymode the battery is used as the main dc input. For details, refer to section1.4.13, Battery Mode. The standard configuration is the loading of the R69, a1206 sized 0 Ω resistor. You can replace R69 with a .01 Ω or larger resistor toallow for the measurement of the total board current consumption by using anoscilloscope to measure the voltage drop across R69.
D4 is an LED that is connected to the PG (Power Good) output of theTPS65010. This is the main power LED for the OSK. The open-drain PGoutput indicates when a valid power supply is present for the charger on theac adapter input. The output turns on when a valid voltage is detected. A validvoltage is detected whenever the voltage rises above the voltage on VBATplus 100 mV. This output is turned off in the sleep mode. The PG output canalso be programmed through the LED1_ON and LED1_PER registers in theserial interface of the TPS65010. It can then be programmed to bepermanently on, off, or to blink with defined on and off period times. PG iscontrolled per default through the charger.
Due to the nature of the TPS65010 design, the main dc input can exhibit noise.For this reason, the VCC input of the TPS65010 must be filtered. This is donethrough an RC circuit comprised of R95 and C77. The supply current of theVCC rail for the TPS65010 is specified at 50 µA.
There is a single point ground connection. This is the point in which the Frame
ground and signal ground connect through R68. This connectionis not actually required but is intended to insure that the ground buses stayseparated and that the PCB layout software does not try to interconnect theground planes anywhere other than at this single point. This point should beas close to the dc input ground pin as possible. In addition, there is an ESDring that goes around the board that also connects to this single point throughR111, which is used to lower the current of the discharged voltage.
Power Management
1-24
1.4.5 SDRAM Voltage
The SDRAM voltage bus has a dedicated voltage supply that minimizes noiseon the bus. Figure 1−9 covers the portion of the design that comprises theSDRAM voltage supply.
Figure 1−9. SDRAM Power Design
TS
VBAT_B
VBAT_A
PG
VINCORE
VINMAIN_B
VINMAIN_A
VCC
L2
VCORE
PGND2
L1_A
L1_B
VMAIN
PGND1_A
PGND1_B
VIN2
VLDO2
VIN1
VLDO1
VFB_LDO1
GPIO4
GPIO3
GPIO2
GPIO1
AC
USB
ISET
Chargersection
40 38
41
42
11
43
37
1DEFCORE
DEFAMIN12
PS_SEQ14
SCLK
IFLSB30
28
SDAT29
PB_ONOFF47
BATT_COVER39
35
31HOT_RESET
INT
2
34PWRFAIL
LED2
LOW_POWER36
VIB3
NC27
32MPU_RESET
33RESPWRON A
GN
D1
AG
ND
2
AG
ND
3
TPS65010_1
DC_IN
8
6
4
7
10
9
46
48
16
15
13
5
C7622 µF, 10 V,X7R, 0402
19
20
VDD_SDRAM
TP12TP11
SH6
Vref 0.5 V
R82243K, 1%
93.1K, 1%R83
18
17
26
25
22
24
23
C322.2 µF10 V
C311 µF, 10 V,X5R, 0402
U10
1 1
.01.0603
Sw
itche
r
Power Management
1-25OMAP5912 Target Module Major Components
The SDRAM and the OMAP5912 voltage pins use LDO1 of the TPS65010.Resistors R82 and R83 are supplied to allow for the voltage to be offset backinto the sense input of the TPS65010. This allows for the voltage to be adjustedfor voltage drops experienced by the layout. The default configuration is to setthe voltage at 1.8 V, which is done by making R82 a 243K and R83 a 93.1Kinto the sense input.
LDO1 delivers up to 200 ma. The requirement for the SDRAM is 75 ma. Thevoltage on LDO1 can be adjusted through software. However, the defaultsetting is external adjust. The optional settings under software control are notused. Refer to the TPS65010: Power and Battery Management IC for Li-IonPowered Systems (literature number SLVS149) data sheet for more detail.
Capacitor C32 provides filtering for the voltage rail. Power for the VLDO1 issupplied by the main dc voltage input rail. Capacitor C31 is required tominimize ripple into the LDO, which can be generated by the TPS65010 backonto the main dc rail.
The current consumption of the VDD_SDRAM voltage rail can be measuredacross SH6 using test points TP11 and TP12 by using a scope to measure thevoltage drop across the .01 Ω resistor in SH6. Refer to Appendix D for adescription of the current measuring procedure.
1.4.6 3.3 V Supply
Figure 1−10 defines the design of the 3.3 V voltage rail on the OMAP5912target module. The 3.3 V supply is the main power supply for most of thecircuitry on the board including the Flash and Ethernet devices.
Power Management
1-26
Figure 1−10. 3.3 V Power Design
TSVBAT_BVBAT_A
PG
VINCOREVINMAIN_BVINMAIN_A
VCCL2
VCOREPGND2
L1_AL1_B
VMAINPGND1_APGND1_B
VIN2VLDO2
VIN1VLDO1
VFB_LDO1
GPIO4GPIO3GPIO2GPIO1
ACUSBISET
Chargersection
40 38414211
4337
1DEFCORE
DEFAMIN12
PS_SEQ14
SCLKIFLSB
3028
SDAT29
PB_ONOFF47
BATT_COVER393531
HOT_RESETINT
234
PWRFAILLED2
LOW_POWER36
VIB3
NC27
32MPU_RESET
33RESPWRON A
GN
D1
AG
ND
2A
GN
D3
TPS65010_1
DC_IN
8
64
7
1094648
161513
5
C7622 µF, 10 V,X7R, 0402
1920
VDD_3V3
TP6TP5
SH3
1817
2625
2224
23
C2822 µF10 V
U10
1 1
.01.0603
L2
6.8 µH
VDD_3V3_MAIN
Sw
itche
r
The 3.3 V power supply is supplied by the main switcher in the TPS65010,which incorporates synchronous step-down converters operating typically at1.25 MHz fixed frequency pulse width modulation (PWM) at moderate toheavy load currents. At light load currents the converters automatically enterpower save mode and operate with pulse frequency modulation (PFM). The3.3 V converter is capable of delivering 1A output current. The converteroutput voltages are programmed through the VDCDC1 and VDCDC2registers in the serial interface. The 3.3 V converter defaults to 3.3 V outputvoltage because the DEFMAIN configuration pin is tied to VCC. The 3.3 Voutput voltage can subsequently be reprogrammed after start-up through theserial interface.
Power Management
1-27OMAP5912 Target Module Major Components
Inductor L2 is required for the switcher in the TPS65010. Capacitor C28provides filtering for the voltage rail. The 3.3 V power is supplied by the maindc voltage input rail. Capacitor C76 is required to minimize ripple into theswitcher.
The current consumption of the VDD_3V3 voltage rail can be measured acrossSH3 using test points TP5 and TP6 by using a scope to measure the voltagedrop across the .01 Ω resistor in SH3. Refer to Appendix D for a descriptionof the current measuring procedure.
Power Management
1-28
1.4.7 3 V Supply
Figure 1−11 shows the design of the 3 V power supply, which is dedicated foruse by the AIC23 CODEC on the board.
Figure 1−11.3 V Power Design
TS
VBAT_B
VBAT_A
PG
VINCORE
VINMAIN_B
VINMAIN_A
VCC
L2
VCORE
PGND2
L1_A
L1_B
VMAIN
PGND1_A
PGND1_B
VIN2
VLDO2
VIN1
VLDO1
VFB_LDO1
GPIO4
GPIO3
GPIO2
GPIO1
AC
USB
ISET
Chargersection
40 38
41
42
11
43
37
1DEFCORE
DEFAMIN12
PS_SEQ14
SCLK
IFLSB30
28
SDAT29
PB_ONOFF47
BATT_COVER39
35
31HOT_RESET
INT
2
34PWRFAIL
LED2
LOW_POWER36
VIB3
NC27
32MPU_RESET
33RESPWRON A
GN
D1
AG
ND
2
AG
ND
3
TPS65010_1
DC_IN
8
6
4
7
10
9
46
48
16
15
13
5
C7622 µF, 10 V,X7R, 0402
19
20
VDD_3VA
TP8TP7
SH4
18
17
26
25
22
24
23C302.2 µF10 V
C291 µF, 10 V,X5R, 0402
U10
1 1
.01.0603
Sw
itche
r
Power Management
1-29OMAP5912 Target Module Major Components
The 3 V voltage supply uses LDO2 of the TPS65010. LDO2 delivers up to200 ma. The requirement for the AIC23 is 25 ma. The voltage on LDO2 canbe adjusted through software while there is no external adjustmentmechanism on VLDO2. The maximum voltage on VLDO2 is 3.0 V. Refer to theTPS65010: Power and Battery Management IC for Li-Ion Powered Systems(literature number SLVS149) data sheet for more detail.
Capacitor C30 provides filtering for the voltage rail. Power for the VLDO2 issupplied by the main dc voltage input rail. Capacitor C29 is required tominimize ripple into the LDO which can be generated by the TPS65010 backonto the main DC rail.
The current consumption of the VDD_3VA voltage rail can be measured acrossSH4 using test points TP7 and TP8 by using a scope to measure the voltagedrop across the .01 Ω resistor in SH4. Refer to Appendix D for a descriptionof the current measuring procedure.
Power Management
1-30
1.4.8 Control Interface
Figure 1−12 is the control interface portion of the TSP65010 device.
Figure 1−12. TPS65010 Control Interfaces
TSVBAT_BVBAT_A
PG
VINCOREVINMAIN_BVINMAIN_A
VCCL2
VCOREPGND2
L1_AL1_B
VMAINPGND1_APGND1_B
VIN2VLDO2
VIN1VLDO1
VFB_LDO1
GPIO4GPIO3GPIO2GPIO1
ACUSBISET
Chargersection
40 38414211
4337
1DEFCORE
DEFAMIN12
PS_SEQ14
SCLKIFLSB
3028
SDAT29
PB_ONOFF47
BATT_COVER393531
HOT_RESETINT
234
PWRFAILLED2
LOW_POWER36
VIB3
NC27
32MPU_RESET
33RESPWRON A
GN
D1
AG
ND
2A
GN
D3
TPS65010_1
8
64
7
1094648
161513
5
1920
1817
2625
2224
23
U10
Sw
itche
r
R3NO POP
DC_IN_FUSED
R40
R7510K
I2C.SCLI2C.SDA
R7610K
RESET_INPWR_INT
VDD_3V3
S1
12
34
SPNO_B3S
Reset
LOW_PWR
R8010K
250−500K
R861K
D2LED, GRN
1
2VDD_3V3
MPU_nRESETnPWRON_RESET
1.4.8.1 Default Core Voltage
Resistors R3 and R4 set the default core voltage on power up. With R4populated and R3 not populated, which is the default configuration, the corevoltage is 1.6 V at power up. With R3 populated and not R4, the default voltageis 1.6 V or as determined by the loading of R3 and R4.
Power Management
1-31OMAP5912 Target Module Major Components
1.4.8.2 SW1
SW1 connects to the HOT_RESET input and is used to generate anMPU_RESET signal for the ARM processor. HOT_RESET is de-bouncedinternally by the TPS65010 and has a typical de-bounce time of 56 ms. TheRESET_IN signal connects to the Expansion Connector B pin 59 to allow theexpansion cards to generate an MPU_RESET if needed. It can also be usedto exit Low Power Mode, in this case the TPS65010 waits until the VCOREvoltage has stabilized before generating the MPU_RESET pulse. TheMPU_RESET pulse is active low for 100 µsec. HOT_RESET has an internal1M pullup to VCC.
1.4.8.3 LED D2
The LED2 output is connected to D2 and can be programmed to blink or bepermanently on or off. The LED2_ON and LED2_PER registers are used tocontrol the blink rate. For LED2, the minimum blink on time is 10 ms and thiscan be increased in 127 10 ms-steps to 1280 ms. The minimum blink periodis 100 ms and this can be increased in 127 100-ms steps to 12800 ms.Software applications are free to use this as needed.
1.4.8.4 LOW_POWER Input
The low_power state is entered by the processor setting the ENABLE_LP bitin the serial interface and then raising the LOW_PWR pin. The TPS65010actually uses the rising edge of the internal signal formed by a logical AND ofthe LOW_PWR and ENABLE LP signals to enter low power mode.
The VMAIN switching converter remains active, but the VCORE converter canbe disabled in low power mode through the serial interface by setting theLP_COREOFF bit in the VDCDC2 register. If left enabled, the VCORE voltageis set to the value predefined by the CORELP0/1 bits in the VDCDC2 register.The LDO1OFF/nSLP and LDO2OFF/nSLP bits in the VREGS1 registerdetermine whether the LDOs are turned off or put in a reduced power mode(transient speed-up circuitry disabled in order to minimize quiescent current)in low power mode.
All TPS65010 features remain addressable through the serial interface.TPS65010 can exit this state through the following events:
Due to an under-voltage condition at VCC Due to an OVERTEMP condition By the processor deasserting the LOW_POWER pin By your activating the HOT_RESET pin or the PB_ONOFF pin
Power Management
1-32
1.4.8.5 Interrupt Output
The open drain INT pin is used to combine and report all possible conditionsthrough a single pin to the OMAP5912. INT can also be activated if any of theregulators are below the regulation threshold. The PWR_INT signal connectsto MPUIO1 on the OMAP5912.
1.4.8.6 I2C
The SDA and SCL pins form the I2C interface that connects to the OMAP5912processor to allow applications on the OMAP5912 to control the functions ofthe TPS65010 device.
The I2C serial interface is compatible with the standard and fast mode I2Cspecifications, allowing transfers at up to 400 kHz. The interface enables mostfunctions to be programmed to new register contents that remain intact as longas VCC remains above 2 V.
The TPS65010 has a 7-bit address with the LSB set by the IFLSB pin whichis tied to ground. The 6 MSBs are 100100. Attempting to read data fromregister addresses not listed in this section results in FFh being read out.
For normal data transfer, DATA is allowed to change only when CLK is low.Changes when CLK is high are reserved for indicating the start and stopconditions. During data transfer, the data line must remain stable wheneverthe clock line is high. There is one clock pulse per bit of data. Each data transferis initiated with a start condition and terminated with a stop condition. Whenaddressed, the TPS65010 device generates an acknowledge bit after thereception of each byte.
The OMAP5912 must generate an extra clock pulse that is associated with theacknowledge bit. The TPS65010 device must pull down the DATA line duringthe acknowledge clock pulse so that the DATA line is a stable low during thehigh period of the acknowledge clock pulse. The DATA line is a stable lowduring the high period of the acknowledge-related clock pulse. Setup and holdtimes must be taken into account.
During read operations, a master must signal the end of data to the slave bynot generating an acknowledge bit on the last byte that was clocked out of theslave. In this case, the slave TPS65010 device must leave the data line highto enable the master to generate the stop condition.
Power Management
1-33OMAP5912 Target Module Major Components
1.4.9 Real Time Clock Power
The Real-Time Clock section provides power to the separate Real-Time Clockinput of the OAMP5912 processor. Figure 1−13 provides the design of thecircuit.
Figure 1−13. Real Time Clock Power Design
OUT
FB
VIN
NCG
U9TPS71501DCK
3
DC IN
C750.47 µF
10 V
4
2
5
1
R72270K, 1%0603
R731M, 1%0603
C240.47 µF10 V
SH1
.01.0603
TP1 TP2
VDD_RTC
1 1
The real-time clock power regulator is separate from the TSP6510 and is feddirectly by the main dc supply. This insures that power can be fed continuouslyfrom the external supply or the battery, when installed. Even though theTPS6510 can power down, the voltage to the RTC is always supplied.
U9 is a TPS71501 LDO regulator. The features of this regulator include:
50-mA low-dropout regulator Available in 2.5 V, 3.0 V, 3.3 V, 5.0 V, and adjustable 24-V maximum input voltage Low 3.2-µA quiescent current at 50 mA 5-Pin SC70/SOT-323 (DCK) package Stable with any capacitor (>0.47 ìF) Over current limitation –40°C to 125°C operating junction temperature range
The OMAP5912 target module design uses the adjustable version of theregulator, which allows the voltage to be set by changing R72 and R73. Thisinsures that no matter how the layout is done, exactly 1.8 V is on theOMAP5912 processor pins.
Power Management
1-34
In the Figure 1−13 resistors R1 and R2 should be chosen for approximately1.5-µA divider current. Lower value resistors can be used for improved noiseperformance, but the solution consumes more power. Higher resistor valuesshould be avoided as leakage current into/out of FB across R1/R2 creates anoffset voltage that artificially increases/decreases the feedback voltage and,therefore, erroneously decreases/increases VO. The recommended designprocedure is to choose R2 = 1 MΩ to set the divider current at 1.5 µA, and thencalculate R1 using the information in Figure 1−14.
Figure 1−14. Real Time Clock Voltage Adjustment
Output Voltage Programming Guide
OutputVoltage R1 R2
1.8 V 0.499 MΩ 1 MΩ
2.8 V 1.33 MΩ 1 MΩ
5.0 V 3.16 MΩ 1 MΩ
The current consumption of the VDD_RTC voltage rail can be measured acrossSH1 using test points TP1 and TP2 by using a scope to measure the voltagedrop across the .01 Ω resistor in SH1. Refer to Appendix D for a descriptionof the current measuring procedure.
There is no separate external battery backup on the real-time clock. Thisrequires that the battery be installed and the OMAP5912 processor be put intodeep sleep mode.
IN OUT
FBGND
V1
0.1 µF
TPS71501
R1
R2
0.47 µF
V0
R1 V0
Vref 1 R2
Power Management
1-35OMAP5912 Target Module Major Components
1.4.10 DSP Voltage Control
You can remove the DSP voltage to conserve power on the OMAP5192.Figure 1−15 shows the control circuitry for this function.
Figure 1−15. DSP Voltage Control
VIN
ON/OFF
R1/C1
4
5
6
VOUT
VOUT
R2
3
2
1
U11
FDC6331LC334.7 µF/10 V
SH5
.01.0603
TP9 TP10
VDD_DSP
1 1
R84150, 0603
R8115K
VDD_CORE
R8115K
TPS65010
GPIO4
VDD_3V3
+17
U11 is a FDC6331L™ integrated power switch from Fairchild. This device is anFET switch that allows the voltage on the DSP to be completely removed bytaking pin 16 of the TPS6501 low. This load switch integrates a smallN-Channel power MOSFET that drives a large P-Channel power MOSFET(Q2) in one tiny 6 package. Access to the GPIO pin is through the I2C busbetween the TPS6501 and the OMAP5912.
The current consumption of the VDD_DSP voltage rail can be measured acrossSH5 using test points TP9 and TP10 by using a scope to measure the voltagedrop across the .01 Ω resistor in SH5. Refer to Appendix D for a descriptionof the current measuring procedure.
Power Management
1-36
1.4.11 DLL Voltage
Figure 1−16 shows the dedicated LDO regulator for DLL power supply.
Figure 1−16. DLL Voltage Circuit
OUT
FB
VIN
NCG
U5TPS71501DCK
3
VDD_3V3_MAIN
C470.47 µF
10 V
4
2
5
1
R90243K, 1%0603
R911M, 1%0603
SH7
.01.0603
TP18 TP19
VDD_DLL
1 1 1.5 V
The DLL power regulator is separate from the TSP6510 and is fed directly bythe 3.3 V supply from the TPS65010.
U5 is a TPS71501 LDO regulator. The features of this regulator include:
50-mA low-dropout regulator Available in 2.5 V, 3.0 V, 3.3 V, 5.0 V, and adjustable 24-V maximum input voltage Low 3.2-ìA quiescent current at 50 mA 5-Pin SC70/SOT-323 (DCK) package Stable with any capacitor (>0.47 ìF) Over current limitation –40°C to 125°C operating junction temperature range
The OMAP5912 target module design uses the adjustable version whichallows the voltage to be set by changing R90 and R91. This insures that nomatter how the layout is done, exactly 1.5 V is on the DLL power pins. Thecorrect value has been set on the OMAP5912 target module as required bythe layout.
Note: Proximity to OMAP5912
During the layout process, all of the components from C74 forward need tobe placed as close to the OMAP5912 as possible.
Power Management
1-37OMAP5912 Target Module Major Components
Figure 1−17 shows that resistors R1 and R2 should be chosen forapproximately 1.5-ìA divider current. Lower value resistors can be used forimproved noise performance, but the solution consumes more power. Higherresistor values should be avoided as leakage current into/out of FB acrossR1/R2 creates an offset voltage that artificially increases/decreases thefeedback voltage and thus erroneously decreases/increases VO. Therecommended design procedure is to choose R2 = 1 M? to set the dividercurrent at 1.5 ìA, and then calculate R1 using the equation illustrated inFigure 1−17.
Figure 1−17. DLL Voltage Adjustment
Output VoltageProgramming Guide
OutputVoltage R1 R2
1.8 V 0.499 MΩ 1 MΩ
2.8 V 1.33 MΩ 1 MΩ
5.0 V 3.16 MΩ 1 MΩ
The current consumption of the VDD_DLL voltage rail can be measured acrossSH7 using test points TP18 and TP19 by using a scope to measure the voltagedrop across the .01 Ω resistor in SH7. Refer to Appendix D for a descriptionof the current measuring procedure.
IN OUT
FBGND
V1
0.1 µF
TPS71501
R1
R2
0.47 µF
V0
R1 V0
Vref 1 R2
Power Management
1-38
1.4.12 Core Voltage
The Core voltage output of the TPS6510 provides power for the core circuitryinside the OMAP5912. Figure 1−18 shows the external components on theTPS6510.
Figure 1−18. Core Voltage Circuit
L2
VCORE
PGND2
4
48
48
TPS65010
L1, 10 µH
R77, 0,0603
R78
n.m. 0603
C2710 µF10 V
TP3 YP4
SH2
VDD_CORE
.01.0603
1 1
The VCORE converter is always enabled in a typical application. The VCOREoutput voltage can be disabled or reduced from 1.6 V to a lower, preset voltageunder processor control. When the processor enters the sleep mode, a highsignal on the LOW_PWR pin initiates the change. When the processor is insleep or low power mode, the VCORE voltage can be programmed to lowervoltages without a problem.
In order to insure that the voltage is exactly at the correct value on theOMAP5912 pins, R77 and R78 have been added to allow the VCORE to beset as needed. In the default configuration R78 is not installed and R77 is a0 Ω resistor.
The exact core voltage for the OMAP5912 is set at 1.6 V. This may change ata later date as testing progresses. This design allows the voltage level to bechanged as needed.
The current consumption of the VDD_CORE voltage rail can be measuredacross SH2 using test points TP3 and TP4 by using a scope to measure thevoltage drop across the .01 Ω resistor in SH2. Refer to Appendix D for adescription of the current measuring procedure.
Power Management
1-39OMAP5912 Target Module Major Components
1.4.13 Battery Mode
An optional Li-ION battery can be connected by using header J4. The selectionof this battery is your responsibility; the battery is not supplied with theOMAP5912 target module or the OSK. Refer to the TPS65010: Power andBattery Management IC for Li-Ion Powered Systems (literature numberSLVS149) data sheet for information on selecting the appropriate battery. Inorder for the circuit to operate properly, the temperature sense lead must beconnected on the battery.
In order for the TPS65010 to operate correctly in the Non-Battery mode,resistor R79 must be installed to insure that the temperature detection circuitryin the TPS65010 is kept happy. When in the battery mode of operation, R79MUST is removed.
JP2 can be used to attach the battery to the circuitry by placing it so that pins2 and 3 are shorted. For this to work, R69 and R71 must be removed.Optionally, R69 can be removed and R71 installed.
This places the battery as the main voltage source and uses the dc input onlyas a supply to the charger circuit of the TPS65010. C25 is a filter for the inputof the battery charger circuit in the TPS65010. R74 sets the default chargecurrent for the battery.
Figure 1−19 illustrates the design of the battery mode of operation.
Power Management
1-40
Figure 1−19. Optional Battery Configuration
TSVBAT_BVBAT_A
PG
VINCOREVINMAIN_BVINMAIN_A
VCC
L2VCOREPGND2
L1_AL1_B
VMAINPGND1_APGND1_B
VIN2VLDO2
VIN1VLDO1
VFB_LDO1
GPIO4GPIO3GPIO2GPIO1
ACUSBISET
Chargersection
40 38414211
4337
1DEFCORE
DEFAMIN12
PS_SEQ14
SCLKIFLSB
3028
SDAT29
PB_ONOFF47
BATT_COVER393531
HOT_RESETINT
234
PWRFAILLED2
LOW_POWER36
VIB3
NC27
32MPU_RESET
33RESPWRON A
GN
D1
AG
ND
2A
GN
D3
TPS65010_1
8
64
7
1094648
161513
5
1920
1817
2625
2224
23
U10
Sw
itche
r
C76
22 µF, 10 V,X7R, 0402
1234
nPG
BATT_TEMP
C251 µF, 10 VX5R, 0402
R741.6K0603
R79 10K, 0603VBAT
2 1 R70
330, 0603DC
4 HEADER,n.m.
D9
LED, GRN
123
HDR3,n.m.
JP2
R71
n.m. 0805DC
R690,0805
F1
1A_Quick Blow
1 2 DC_IN_FUSED123
P7DC8
DC_IN
Flash Memory
1-41OMAP5912 Target Module Major Components
1.5 Flash Memory
The OMAP5912 target module supports two NOR FLASH devices and can beconfigured in several ways to obtain a range of Flash densities. It also providesfor a mechanism whereby the FLASH can be disabled by an expansion boardand that expansion board is then the provider of the FLASH devices.
The following sections provide a description of the FLASH circuitry on theOMAP5912 target module.
1.5.1 Supported Configurations
Table 1−6 defines the supported FLASH memory configuration on theOMAP5912 target module. The standard configuration is the dual 16 MBdevices for a total of 32 MB.
Table 1−6. FLASH Configurations
Size Slot 1 Slot 2
4Mb 4Mb −
8Mb 4Mb 4MB
8Mb 8Mb −
16Mb 8Mb 8Mb
16Mb 16Mb −
32Mb 16Mb 16Mb
32Mb 32Mb
64Mb 32Mb 32Mb
Flash Memory
1-42
1.5.2 Supported FLASH Devices
The Flash design supports the devices specified in Table 1−7.
Table 1−7. Supported FLASH Devices
Manufacturer Part Number Size
Micron MT28F320J3 32Mb
Intel RC28F320J3A110 32Mb
MIcron MT28F640J3 64Mb
Intel RC28F640J3A120 64Mb
Micron MT28F128J3FS-12 128Mb
Intel RC28F128J3C150 128Mb
Only the NOR flash devices are supported on the OMAP5912 target module.The base configuration is two Micron MT28F128J3 devices. The MicronQFlash™ devices are software compatible with the Intel Strata Flash™devices. They are offered in a version with a Micron ID or an Intel ID. TheMicron ID version is used on the OMAP5912 target module.
1.5.3 FLASH Circuit Design
Figure 1−20 is the interconnection between the OMAP5912 and the FLASHdevices. Only one FLASH device is shown. The differences in connectionsrequired for the second FLASH device is contained in the text.
Flash Memory
1-43OMAP5912 Target Module Major Components
Figure 1−20. FLASH Circuitry Design
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
C8
A8
G1
H8
G4
D5
D6
A6
H3
A4
B6
0 0 0 0 0
F0 0 0
22 22 22 22 22 222222 2222222222 222222 22 2222 222222222222 22 22 2222 22 22 22 22 22 2222 222222
D3
R16
1R
162
C2
R16
3E
4E
3R
165
R16
7D
2
D1
E2
C1
R17
3R
171
R16
9
G5
G2
G4
G3
R18
9R
187
R18
5R
183
R17
5E
1
F5
F1
F2
R18
1R
179
R17
7
R19
7H
5
R20
1F
3
J2 J4H2
R19
9R
200
R19
8
F4
H4
H3
R19
6R
195
R19
3G
6R
191
FLA
SH
.RD
YF
LAS
H.C
LKF
LAS
H.D
[0]
FLA
SH
.D[1
]F
LAS
H.D
[2]
FLA
SH
.D[3
]F
LAS
H.D
[4]
FLA
SH
.D[6
]
FLA
SH
.D[9
]F
LAS
H.D
[8]
FLA
SH
.D[7
]
FLA
SH
.D[5
]
FLA
SH
.D[1
5]
FLA
SH
.D[1
1]
FLA
SH
.D[1
3]F
LAS
H.D
[14]
FLA
SH
.D[1
2]
FLA
SH
.D[1
0]
FLA
SH
Inte
rfac
e
J3R
202
T1
R20
3
J8R
205
J6R
204
M5
P3
R20
6R
207
R20
8J1 K
2R
209
R21
4N
3H
14R
215
H6
R3
K3
R21
2R
213
R21
1M
15R
210
nFLA
SH
.CS
1AnF
LAS
H.C
S1B
nFLA
SH
.CS
3nF
LAS
H.C
S2
nFLA
SH
.OE
n.F
LAS
H.W
E
nFLA
SH
.BE
0nF
LAS
H.B
E1
GP
IO1
nFLA
SH
.CS
2BnF
LAS
H.A
DV
nFLA
SH
.WP
nFLA
SH
.RP
MP
U_B
OO
T
Sh.
9, 1
0S
h.9
Sh.
9S
h.9
Sh.
8, 9
, 10
Sh.
8, 9
, 10
Sh.
8, 9
Sh.
8, 9
Sh.
9S
h.9
Sh.
9S
h.9
Sh.
9S
h.9
VD
D_3
V3
10K
10K
R16
422
FLA
SH
.D1
FLA
SH
.D15
FLA
SH
.D14
FLA
SH
.D13
FLA
SH
.D12
FLA
SH
.D11
FLA
SH
.D10
FLA
SH
.D9
FLA
SH
.D5
FLA
SH
.D8
FLA
SH
.D7
FLA
SH
.D6
FLA
SH
.D4
FLA
SH
.D3
FLA
SH
.D2
FLA
SH
.D0
R16
622
R17
0R
168
2222
R17
6R
178
22 22
R17
4R
172
2222
R19
4R
192
2222
R18
8R
190
R18
4R
186
22 2222 22
R18
2R
180
2222
R2
0
R1
10K
VD
D_3
V3
FLA
SH
.CLK
Sh.
9F
LAS
H.R
DY
Sh.
8, 9
, 10
R3
R4
R6R5
VD
D_3
V3
10K10K
10K10K
OM
AP
5912
−28
9 G
DY
U31
FLA
SH
.D2
FLA
SH
.D10
FLA
SH
.D11
FLA
SH
.D12
FLA
SH
.D13
FLA
SH
.D14
FLA
SH
.D15
FLA
SH
.D3
FLA
SH
.D4
FLA
SH
.D6
FLA
SH
.D7
FLA
SH
.D8
FLA
SH
.D5
FLA
SH
.D9
FLA
SH
.D0
FLA
SH
.D1
nFLA
SH
.OE
nFLA
SH
.WE
nFLA
SH
.RP
nFLA
SH
.WP
A B
FLA
SH
.RD
YC
nFLA
SH
.AD
VD
FLA
SH
.CLK
E G H
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
CE
OE
WE
RP
WP
[DN
U]
VS
SV
SS
VS
SQ
[DN
U]
VS
SQ
[VS
S]
WA
IT[D
NU
]A
DV
[DN
U]
CLK
[DN
U]
ST
S
RF
U[C
E2]
RF
U[A
0]R
FU
[CE
1]
I0
FLA
SH
.A24
VD
D_3
V3
J0
C1
0.01
uF10
V
F1
K0
nFLA
SH
.BE
0
K10
K
NO
R F
LAS
HS
LOT
1
U1 28F
xxxK
3 [J
3] (
4−32
MB
ytes
)
Flash Memory
1-44
1.5.4 Address Bus
The OMAP5912 has 24 address lines, A1−A25. Only address lines 1−24 areused for the largest device. Even though all of the address lines are connectedto the devices, not all of the pins can be used depending on which device isinstalled.
1.5.5 Data Bus
The data bus from the OMAP5912 is 16 bits wide. All of the data bits areconnected to each of the Flash devices.
1.5.6 Control Signals
All signals are the same for both slots except the chip select (CS) signal. Slot0 uses the CSXA while Slot 1 uses CSXB. Depending on the type of memoryused, some of the signals may not be connected. This is handled by thepopulating or unpopulating of certain resistors.
The signal GPIO1 is used to set the configuration of the Flash bus. To becompatible with the OMAP5912 target module design, this pin must be tied toground. The MPU_BOOT signal should be tied high for the OMAP5912 targetmodule application.
1.5.7 Address Decode Logic
Figure 1−21 illustrates the design of the decode logic for the FLASH devices.
Figure 1−21. FLASH Decode Logic
L
M
O
N
0
0
0
0
FLASH.A22 R35
R36FLASH.A23
R37FLASH.A24
R38FLASH.A25
Rx0
2
R
Q
P
nFLASH.CS3
nFLASH.CS2
nFLASH.CS1B
R34
R33
R32
0
0
0
10 KR29
FLASH.DIS
3
1
A
B
GGND
VSS Y0Y1Y2Y3
VDD_3V3
16
8
U4A
74LVC139
nFLASH.CSXAnFLASH.CSXB
4567
VDD_3V3
C690.01 µF10 V
FLASH.A[1.25]
Flash Memory
1-45OMAP5912 Target Module Major Components
Table 1−8 defines how the resistors are to be loaded for each of the supportedmemory size configurations. In order to support contiguous memory betweenthe two memory device slots, the address decoding for the second block mustbe moved. This is done by moving the A bit of the ‘139 decoder to theappropriate address line at the beginning of the Slot 2 address range. Thedefault value of the OMAP5912 target module design is highlighted inTable 1−8.
Table 1−8. Flash Address Decode Resistor Options
Devices Size L M N O Address line used
1 4MB x A22
2 8MB x A22
1 8MB x A23
2 16MB x A23
1 16MB x A24
2 32MB x A24
1 32MB x A25
2 64MB x A25
1 64MB None
In the event a single 64MB device is used, Rx in Figure 1−21 must be installedto insure that the full 64MB range is valid for the chip select.
The base address range can also be moved between chip selects. Table 1−9defines how this can be done. The moving of the chip select is not impactedby whether or not there is one or two memory devices used.
Table 1−9. Flash Chip Select Resistor Options
Chip Select Size P Q R
CS1B 32MB x
CS2 64MB x
CS3 64MB x
If CS1B is to be used, it is limited to 32MB of address space. Insure that thedesired memory configuration works with CS1B. CS3 is the defaultconfiguration.
Flash Memory
1-46
1.5.8 General-Purpose Mode Support
The OMAP5912 comes with an internal boot ROM that enables you to bootand flash the external flash memory on the board. There are two different waysof booting the OMAP5912 device:
Full Boot. The device boots from the internal ROM. When used with theexternal Boot loader software the internal ROM can then be used to bootthe Flash device on the board.
Fast Boot. The device boots from the external Flash that is on CS3.
In order to select between these modes, GPIO_13 is tested. If GPIO_13 is low,then the Fast Boot method is selected. If GPIO_13 is high, then the Full Bootmethod is selected. In order to allow the setting of GPIO_13 either high or low,JP3 is provided.
DDR SDRAM
1-47OMAP5912 Target Module Major Components
1.6 DDR SDRAM
This section covers the design of the SDRAM section of the OMAP5912 targetmodule. While the OMAP5912 supports SDR (Single Data Rate) SDRAM, thisdesign uses an DDR (Dual Data Rate) SDRAM device. The device is theElpida 246 Mb Mobile DDR EDK2516CBBH™.
Only Mobile DDR devices are supported by the OMAP5912. Mobile providesfor low current operation and supports only 1.8 V voltage rails and interfaces.The OMAP5912 supports up to 512 Mb of DDR SDRAM. Due to the limitationof the single device, the maximum memory is limited by the single devices thatare on the market.
Refer to the Elpida 256 bits DDR Mobile RAM EDK2516CBBH data sheet formore infomation.
1.6.1 DDR SDRAM Circuit Design
Figure 1−22 illustrates the design of the DDR SDRAM interface on theOMAP5912 target module.
DDR SDRAM
1-48
Figure 1−22. Mobile DDR SDRAM Design
0 0 00 0000 0 0000000
SD
RA
M.D
[15]
SD
RA
M.D
[14]
SD
RA
M.D
[12]
SD
RA
M.D
[13]
SD
RA
M.D
[9]
SD
RA
M.D
[8]
SD
RA
M.D
[10]
SD
RA
M.D
[11]
SD
RA
M.D
[2]
SD
RA
M.D
[0]
SD
RA
M.D
[1]
SD
RA
M.D
[3]
SD
RA
M.D
[5]
SD
RA
M.D
[4]
SD
RA
M.D
[6]
SD
RA
M.D
[7]
D10
E8
E9
F8
F9
C6
A10
E10
C8
D9
C3
F7
A1
B2
00 0 0 000 000000S
DR
AM
.A12
SD
RA
M.A
11S
DR
AM
.A10
SD
RA
M.A
9S
DR
AM
.A8
SD
RA
M.A
7S
DR
AM
.A6
SD
RA
M.A
5
SD
RA
M.A
0S
DR
AM
.A1
SD
RA
M.A
2S
DR
AM
.A3
SD
RA
M.A
4
A12
A11
A10
/Ap
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
SD
RA
MIN
TE
RFA
CE
U3A
OM
AP
5912
−28
9 G
DY
nSD
RA
M.D
QS
HA
120
UD
QS
nSD
RA
M.D
QS
LA
20
LDQ
S
nSD
RA
M.D
DR
.CLK
nSD
RA
M.C
SA
6E
7100
CK
CS
SD
RA
M.C
LKS
DR
AM
.CK
E
SD
RA
M.B
A1
SD
RA
M.B
A0
A7
B13
C4
C5
01000
CK
CK
E
BA
1B
A0
A8
C7
E6
D4
D5
nSD
RA
M.D
QM
UnS
DR
AM
.DQ
ML
nSD
RA
M.W
EnS
DR
AM
.RA
SnS
DR
AM
.CA
S
UD
MLD
MW
ER
AS
CA
SR3910KR4010K
10K R42R4110K
R4310K
VD
D_S
DR
AM
F3
F7
SD
RA
M.D
3S
TO
RM
ED
4S
TO
RM
ED
5S
TO
RM
ED
6S
DR
AM
.D7
SD
RA
M.D
8S
DR
AM
.D9
SD
RA
M.D
10S
DR
AM
.D11
SD
RA
M.D
12S
DR
AM
.D13
SD
RA
M.D
14S
DR
AM
.D15
C7
C2
E7
D7
C8
D8
D2
E3
D3
C3
B2
B3
A2
2222
A8
SD
RA
M.D
0
B8
B7
SD
RA
M.D
2S
DR
AM
.D1
2222 22222222 22 22 222222222222
VDD
VDD
VDD
F9A9K9
D1VDDQ
VDDQC9
E9VDDQB1
VDDQ
VDDQA7
VD
D_S
DR
AM
VSS
VSS
VSS
F1
K1A1
VSSQVSSQ
B9VSSQC1
VSSQVSSQ
E1D9
A3
Mob
ileD
DR
U7
Not
e: S
DR
AM
.DD
R.C
LK a
nd S
DR
AM
.CLK
rou
tes
mus
t be
the
sam
e le
ngth
and
rou
ted
next
to e
ach
othe
rat
4m
il sp
acin
g.
DDR SDRAM
1-49OMAP5912 Target Module Major Components
1.6.2 Elpida EDK2516CBBH DDR Device
The features of the Elpida EDK2516CBBH device include:
Low voltage power supply
VDD: 1.8 V ± 0.15 V
VDDQ: 1.8 V ± 0.15 V
Wide temperature range (.25°C to 85°C)
Programmable partial array self refresh
Programmable driver strength
Auto temperature compensated self-refresh by built-in temperaturesensor
Deep power down mode
Small package (60-ball FBGA)
FBGA package is lead free solder (Sn-Ag-Cu)
Data rate of 200 Mbps/IO(max)
Double Data Rate architecture with two data transfers per one clock cycle
Bi-directional, data strobe (DQS) is transmitted/received with data, to beused in capturing data at the receiver.
1.8 V LVCMOS interface
Command and address signals refer to a positive clock edge
Quad internal banks controlled by BA0 and BA1
Data mask (DM) for write data
Wrap sequence = sequential/ interleave
Programmable burst length (BL) = 2, 4, 8
Automatic precharge and controlled precharge
Auto refresh and self refresh
8,192 refresh cycles/64 ms (7.8ìs maximum average periodic refreshinterval)
Burst termination by Burst stop command and Precharge command
Audio Codec
1-50
1.7 Audio Codec
An AIC23 audio CODEC is included on the OMAP5912 target module toprovide audio input and output. The design of the audio circuit is described inthis section.
1.7.1 Audio CODEC Design
Figure 1−23 illustrates the design of the audio CODEC circuit on theOMAP5912 target module.
Figure 1−23. AIC23 Audio CODEC Design
C61
10 V
C60
Stereo in
Stereo in
3
421
124
3
R1355.6 K
C48220 pF
10 V 10 V.A1 µFC49
R134, 5.6 K
10 V220 pF
C52
R136, 5.6 K
5.6 KR139
10 V.A1 µFC53
L5FERRITE BEAD
M2301−ND
R143330
C560.1 µF
10 V
220 pFC55
10 V
R1421 K
R141330
220 pFR140C54
10 V4.7 K
(5,6,9) I2C.SDA
(5,6,9) I2C.SDL
(5,9) MCBSP1.DX
R144 22
R146 22(5,9) MCBSP1.FSX
(5,9) MCBSP1.DR
(5,9) MCBSP1.CLKXR145 20K
VDD_3VA
TP131
R147 22.0603(5,9) MCBSP1.FSX
VCC
GND
OUT
EN
U21DK/SG8002CAPCB−ND
(12,000MHz)VDD_3V3
C640.1 µF
10V n.m.
L8
FERRITEBEAD
M2301−MD
4
2
R150
20K n.m.
R14833 n.m.
R149n.m.0603
3
1
19
20
18
17
23
24
4
6
5
7
3
21
26
25
LLINEIN
RLINEIN
MICIN
MICBIAS
SDIN
SCLK
DIN
DOUT
LRCIN
LRCOUT
BCLK
CS
XTO
XTL_MCLK
U17TLV320AIC23PW
DG
ND
AG
ND
HP
GN
D
28 15 11
R49, 0,0805
Joining analog and digitalgrounds by the CODEC
LOUT
ROUT
LHPOUT
RHPOUT
CLKOUT
HPVDD
AVDD
BVDD
DVDD
VMID
MODE
3
21
4
12
13
1
1TP14
TP15
P5
Headphone outstereo inR138
20 K
R13720 K
C50100uF, 6.3 V
L3FERRITE
BEADM2301−ND
100uF, 6.3 VC50
FERRITE
M2301−NDBEAD
L4
2TP16
1
MCBSP1.CLKS (5,9)
C5810 µF10 V
0.1uF10 V
C59
L6
VDD_3VA
VDD_3VA
C570.1 µF
10 V
C620.1 µF
10 V
L7
0.1 µF10 V
10 µF10 V0.1 µFC63
9
10
8
14
1
27
16
22
M2301−ND
FERRITEBEAD
BEADM2301−ND
FERRITE
R298, 22
Mic in
P1
Line in
Audio Codec
1-51OMAP5912 Target Module Major Components
1.7.2 Audio Inputs
The audio circuit has two stereo audio inputs. Figure 1−24 shows the audioinputs.
Figure 1−24. AIC23 Audio Inputs
Stereo in
Stereo in
3
421
124
3
R1355.6 K
C48220 pF
10 V 10 V.A1 µFC49
R134, 5.6 K
10 V220 pF
C52
R136, 5.6 K
5.6 KR139
10 V.A1 µFC53
L5FERRITE BEAD
M2301−ND
R143330
C560.1 µF
10 V
220 pFC55
10 V
R1421 K
R141330
220 pFR140C54
10 V4.7 K
19
20
18
17
23
24
4
6
5
7
3
21
26
25
LLINEIN
RLINEIN
MICIN
MICBIAS
SDIN
SCLK
DIN
DOUT
LRCIN
LRCOUT
BCLK
CS
XTO
XTL_MCLK
U17TLV320AIC23PW
DG
ND
AG
ND
HP
GN
D
LOUT
ROUT
LHPOUT
RHPOUT
CLKOUT
HPVDD
AVDD
BVDD
DVDD
VMID
MODE
12
13
2
9
10
8
14
1
27
16
22
Mic in
P1
Line in
The TLV320AIC23 has line inputs for the left and the right audio channels(RLINEIN and LLINEIN). Access to these signals is gained through connectorP1, which is a 3.5mm audio jack. Both line inputs have independentlyprogrammable volume controls and mutes. The gain is independentlyprogrammable on both left and right line-inputs.
Audio Codec
1-52
R134 and C48 create a high pass filter for the audio input on the left channel.R136 and C52 create a high pass filter for the audio input on the right channel.Resistors R139 and R136 are used to insure the line inputs are terminatedwhen no signal is present at P1.
Connector P6 is a 3.5mm jack that is used to connect the microphone inputto the AIC23. MICIN is a high-impedance, low-capacitance input that iscompatible with a wide range of microphones. It has a programmable volumecontrol and a mute function. Active and passive filters prevent highfrequencies from folding back into the audio band.
The MICBIAS output provides a low-noise reference voltage suitable forbiasing electret-type microphones and the associated external resistor biasingnetwork. The maximum source current capability is 3 mA. This limits thesmallest value of external biasing resistors that can be used safely. TheMICBIAS output is not active in standby mode.
1.7.3 Audio Outputs
Access to the headphone outputs is through a single 3.5 mm stereo jack. Whilesuitable for driving a headphone, the output is not suitable for driving a set ofspeakers unless those speakers are powered. The audio is coupled to the leftand right channels through C30 and C31. Each channel has a ferrite bead andresistor circuit to help minimize transmissions out the audio jack.
Figure 1−25 illustrates the design of the stereo headphone output of the AIC23Audio CODEC.
Audio Codec
1-53OMAP5912 Target Module Major Components
Figure 1−25. AIC23 Audio Outputs
1920181723244
6573
21
2625
LLINEINRLINEINMICINMICBIASSDINSCLKDIN
DOUTLRCINLRCOUTBCLKCS
XTOXTL_MCLK
U17TLV320AIC23PW
DG
ND
AG
ND
HP
GN
D
LOUTROUT
LHPOUTRHPOUTCLKOUT
HPVDDAVDDBVDDDVDDVMID
MODE
3
21
4
1213
11
TP14TP15
P5
Headphone outR13820 K
R13720 K
C50100 µF, 6.3 VL3
L3FERRITE
BEADM2301−ND
100 µF, 6.3 VC51
FERRITE
M2301−NDBEAD
L4
2
910
8141271622
1.7.4 Clocking
The AIC23 requires an external 12 MHZ clock to drive the internalcomponents. Figure 1−26 shows that there are two ways of accomplishingthis.
Audio Codec
1-54
Figure 1−26. AIC23 Clocking Options
R147 22.0603MCLK
VCC
GND
OUT
EN
X2DK/SG8002CAPCB−ND
(12,000MHz)VDD_3V3
C640.1 µF
10 V n.m.
4
2
R150
20K n.m.
R14833 n.m.
R149n.m.0603
3
1
1920181723244
6573
21
2625
LLINEINRLINEINMICINMICBIASSDINSCLKDIN
DOUTLRCINLRCOUTBCLKCS
XTOXTL_MCLK
U17TLV320AIC23PW
DG
ND
AG
ND
HP
GN
D
LOUTROUT
LHPOUTRHPOUTCLKOUT
HPVDD
AVDD
BVDDDVDD
VMIDMODE
1213
2
910
8141271622
X2 is an external 12 MHZ crystal oscillator that can provide the 12 MHZ clockwhen installed. R3 must be mounted to make the connection. X2 is notinstalled on the OMAP5912 target module and the primary clock source optionfor providing the clock is used.
The primary clock source is the MCLK signal from the OMAP5912. MCLK canbe set to 12 MHZ and fed directly into the AIC23. This is the primary methoduse on the OMAP5912 target module. In this option X2, R150, R149, R148,and C64 are not installed.
Audio Codec
1-55OMAP5912 Target Module Major Components
1.7.5 Power
Figure 1−27 illustrates the power design for the AIC23.
Figure 1−27. AIC23 Power Section
1920181723244
6573
21
2625
LLINEINRLINEINMICINMICBIASSDINSCLKDIN
DOUTLRCINLRCOUTBCLKCS
XTOXTL_MCLK
U17TLV320AIC23PW
DG
ND
AG
ND
HP
GN
D
R49, 0,0805
Joining analog and digitalgrounds by the CODEC
LOUTROUT
LHPOUTRHPOUTCLKOUT
HPVDDAVDDBVDDDVDDVMID
MODE
1213
2
C5810 µF10 V
0.1 µF10 V
C59
L6
VDD_3VA
VDD_3VA
C570.1 µF
10 V
C620.1 µF
10 V
L7
0.1 µF10 V
C61
10 µF10 V0.1 µFC63
10 V
C60
910
8141271622
M2301−ND
FERRITEBEAD
BEADM2301−ND
FERRITE
TP16
Each of the power inputs is heavily filtered to minimize the affect noise mayhave on the audio component. The power rails are actually split into analogand digital rails. BVDD and DVDD are the digital rails for the AIC23. HPVDD andAVDD are the analog rails. The LC circuits minimize any high frequency noisefrom entering the AIC23 whose harmonics could potentially cause noise in theaudio.
Resistor R49 allows for the grouping of the grounds for the AIC23 such thatthey connect at a single point to the system ground. This technique is used toinsure that the PCB layout software does not allow the ground to be connectedon a common ground plane.
Audio Codec
1-56
1.7.6 OMAP5912 Interface
Figure 1−28 illustrates the design of the interface between the OMAP5912and the AIC23 CODEC.
Figure 1−28. AIC23 OMAP5912 Interface
I2C.SDA
I2C.SDL
MCBSP1.DX
R144 22
R146 22MCBSP1.FSX
MCBSP1.DR
MCBSP1.CLKR145 20K
VDD_3VA
19
20
18
17
23
24
4
6
5
7
3
21
26
25
LLINEIN
RLINEIN
MICIN
MICBIAS
SDIN
SCLK
DIN
DOUT
LRCIN
LRCOUT
BCLK
CS
XTO
XTL_MCLK
U17TLV320AIC23PW
DG
ND
AG
ND
HP
GN
D
LOUT
ROUT
LHPOUT
RHPOUT
CLKOUT
HPVDD
AVDD
BVDD
DVDD
VMID
MODE
12
13
2
9
10
8
14
1
27
16
22
The mode of the AIC23 control interface is controlled by the MODE pin. If themode pin is tied low, then the interface is a 2-wire interface or I2C. If the modepin is tied high, then it is in the SPI mode. In the OMAP5912 target moduledesign, the interface is set to 2-wire mode. In 2-wire mode, the data transferuses SDIN for the serial data and SCLK for the serial clock. The start conditionis a falling edge on SDIN while SCLK is high. The seven bits following the startcondition determine which device on the 2-wire bus receives the data. R/Wdetermines the direction of the data transfer. The TLV320AIC23 is a write-onlydevice and responds only if R/W is 0. The device operates only as a slavedevice whose address is selected by setting the state of the CS pin as definedin Table 1−10.
Table 1−10. AIC23 I2C Address Definition
CS State Address
0 0011010
1 0011011
Audio Codec
1-57OMAP5912 Target Module Major Components
In the OMAP5912 target module design, this signal is pulled high via R145.The I2C bus is used to set up all control functions on the AIC23.
McBSP1 is used from the OMAP5912 as the audio channel interface for theAIC23. The McBSP1 is set up as an I2S interface. McBSP1 is used becausein the OMAP5912 the DSP has direct access to McBSP1.
The AIC23 is set up as the master. Thus, the AIC23 provides the frame syncand clock to the OMAP5912. McBSP1.DX is the input path to the AIC23 whileMCBSP1.DR is the output path. McBSP1.CLK is the clock output from theAIC23. McBSP1.FSX is the frame clock for the data signal.
Compact Flash
1-58
1.8 Compact Flash
The OMAP5912 target module has a Compact Flash interface that supportsboth Type I and Type II cards. Figure 1−29 details the design of the interface.
Figure 1−29. Compact Flash Socket Design
FLASH.A14FLASH.A1
FLASH.A3FLASH.A2
FLASH.A6FLASH.A7
FLASH.A5FLASH.A4
FLASH.A12FLASH.A11
FLASH.A10FLASH.A13
FLASH.A9FLASH.A8
20191817161514121110
8443534
AD0AD1
AD3AD2
AD7AD6AD5AD4
AD8AD9AD10REGIOWRIORD
D00D01D02D03D04D05D06D07D08D09D10D11D12D13D14D15
212223234564748492728293031
VCCVCC
FLASH.D0FLASH.D1
FLASH.D3FLASH.D2
FLASH.D5FLASH.D6FLASH.D7
FLASH.D4
FLASH.D9
FLASH.D13
FLASH.D15FLASH.D14
FLASH.D12
FLASH.D10FLASH.D11
FLASH.D8
3813
VDD_3V3PTC1
PTC, 1206
C4410 µF
10 V0.01 µF
C85
(2,9,10) FLASH.A[1..25]
P14
FLASH.D[0..15] (2,9,10)
R10610 K
R10910 K
VDD_3V3
2625
nCFLASH.CD1 (5,9)nCFLASH.CD2 (5,9)
CD1CD2
33VS1VS2
40
BVD1BVD2
4645
Compact Flash Connector_0
5
7
3
U20B74LVC2G125
(2,9) nFLASH.BE0
(10) CFLASH_EN
74LVC2G125U20A
(2,9) nFLASH.BE0
1
2 6
C830.1 µF10 V
VDD_3V3
8
4R107 47K
R10
4R
105
R29
2R
106
R29
3
397
32
10K
10K
1K10K
1K
VDD_3V3
(2,9,10) nFLASH.OE(2,9,10) nFLASH.WE
R999 n.m.(5,9) nCFLASH.IREQ(2,9,10) FLASH.RDY
(5,9) nCFLASH.IOIS16
936
37422443
(5,9) nCFLASH.RESET41
(5,9) GPIO62R1000 0 1
50
CSELCE1CE2OEWE
RDY/BSYWAITWPINPACK#RESET
GNDGND
1.8.1 Integrated Interface
The OMAP5912 has an integrated control interface that allows for a CompactFlash device to be connected directly to the OMAP5912. The Compact Flashcontroller (CFC) interfaces a Compact Flash and a classical memory interface.Control signals from the memory interface are processed through the CFC todrive a Compact Flash card, and control signals from Compact Flash areprocessed to perform a data transfer to the memory interface.
Compact Flash
1-59OMAP5912 Target Module Major Components
1.8.2 Compact Flash Interface Signals
Signals on the OMAP5912 are converted to Compact Flash control signalswhen the Compact Flash is accessed. Table 1−11 defines how the signalfunctions change when the Compact Flash is accessed.
Table 1−11. OMAP5912 Compact Flash Interface
Compact Flash Name Name I/O Compact Flash Description
A10−A1 FLASH.A[10−1] OUT Address bus
A0 FLASH.A[14] OUT Address bus
REG FLASH.A[13] OUT Attribute memory select
IOWR FLASH.A[12] OUT I/O data write
IORD FLASH.A[11] OUT I/O data read
WAIT FLASH.RDY IN Wait
WE FLASH.WE OUT Strobe
CE2 FLASH.BE[1] OUT Card enable
CE1 FLASH.BE[0] OUT Card enable
D15−D0 FLASH.D[15:0] I/O Data bus
OE FLASH.OE OUT Output enable
WPIOIS16
CFLASH.IOIS16 IN Write protect8/16 bits selection
RESET CFLASH.RESET OUT Reset
CD1 CFLASH.CD1 IN Card detect
CD2 CFLASH.CD2 IN Card detect
RDY/BSYIREQ
CFLASH.IREQ IN Ready for new data
1.8.3 CFLASH.IREQ
Currently, the CFLASH.IREQ in not working as defined. Therefore, the abilityto connect the CFLASH.IREQ to either the predefined CFLASH.IREQ pin orto GPIO62 was added. The default configuration uses GPIO62, although thiscould change in the future.
Compact Flash
1-60
1.8.4 Address Decode Logic
Within the OMAP5912, the Compact Flash interface can be placed atCS0−CS3 by setting a register in the OMAP5912. The OMAP5912 targetmodule design recognizes either CS1 or CS2 only in its design. CS2 is thedefault selection in order to not interfere with the Ethernet controller that islocated at CS1.
No external chip select signal is needed as this is generated on the BE0 andBE1 pins from the OMAP5912. However, BE0 and BE1, when not being usedto access the compact flash card, can still be active during other memoryaccesses, which could lead to false enables being sent to the compact flashcard. Therefore, the BE0 and BE1 pins must be qualified with an external chipselect signal called CFLASH_EN. This signal is used to activate twoSN74LVC2G125 buffers. When qualified with the CFLASH_EN signal, theBE0 and BE1 signals are allowed to pass to the Compact Flash interface.Resistors R292 and R293 are set at 1K to allow for a fast rise time when theCFLASH_EN signal is driven high because this causes the buffers to tri-state.CFLASH_EN is connected to CS2.
Figure 1−30 shows the decode logic for the CFLASH_EN signal.
Figure 1−30. CFLASH_EN Signal Decode Logic
14
13
15
A
B
GGND
VSS Y0Y1Y2Y3
VDD_3V3
16
8
U4B
74LVC139
1211109
(2,9) FLASH.A23
(2,9) FLASH.A24
(2,9) nFLASH.CS1A
R162 NO_POPR163 0
R161(2,9) nFLASH.CS2
0500:0000 − 057F:FFFF
0580:0000 − 05FF:FFFF
0480:0000 − 04FF:FFFF
CFLASH_EN (8)
nEX_CS3(5)
nEX_CS4(5)0400:0000 − 047F:FFFF
U4B is half of an SN74LVC139™ decoder. The CFLASH_EN signal enablesthe CE buffers for the Compact Flash interface. This Compact Flash interfacecan reside in either CS1 or CS2. CS2 is the default configuration, meaningR161 is loaded and R162 is not loaded.
The Compact Flash interface is active for the entire chip select range selected.Depending on what specific addresses are selected, the Compact Flashinterface takes on the characteristics of a specific compact flash mode. Thecompact flash card supports the following access modes:
Common memory Attribute memory
Compact Flash
1-61OMAP5912 Target Module Major Components
The controller manages access to the different modes of the Compact Flash(access protocol in these modes follows the Compact Flash standard).Table 1−12 shows which address range implements which access mode forthe Compact Flash interface.
Table 1−12. Compact Flash Memory Mapping
Space NameStart Address and
CS Address Stop Address Size
Compact Flash memory space 0000:0000 0000:07FF 2K bytes
Compact Flash attribute space 0000:0800 0000:0FFF 2K bytes
1.8.5 Data Bus Interface
The data bus is connected to the Compact Flash interface and is used as withany normal memory device interface.
1.8.6 Power interface
Power to the Compact Flash interface is supplied by the 3.3 V supply. PTC1is a self-healing current-limiting device. This is provided in lieu of a fuse device.When the current exceeds 1A max, the resistance of the PTC goes up, limitingthe current to the Compact Flash interface. The hold current is specified at500ma.
JTAG/Multi-ICE Interface
1-62
1.9 JTAG/Multi-ICE Interface
A 14-pin header is provided for access to the standard JTAG interface. Inaddition, a 20-pin header is provided for access to the Multi-ICE connector.
1.9.1 JTAG/Multi-ICE Features
The JTAG/Multi-ICE interface provides the following features:
JTAG port Buffer Standard 14-pin JTAG connector 20 Pin Multi-ICE Connector Ability to reset the ARM processor for the Multi-ICE interface Strappable JTAG reset nTRST pull down Disable pin for ADM shutdown
1.9.2 Design Description
The OMAP5912 provides the signals for the JTAG interface. The JTAGinterface is routed through U8, which is an SN74LVC244AGQN™ buffer.Series resistors R57−62 and R66−67 are intended to control the over andundershoot of the signals. Resistors R54−56 and R64−65 provide additionalpull up current for the signals as needed. These values can be adjusted duringthe testing phase of the board.
Figure 1−31 illustrates the design of the JTAG interface on the OMAP5912target module.
JTAG/Multi-ICE Interface
1-63OMAP5912 Target Module Major Components
Figure 1−31. JTAG Interface DesignVDD_3V3
R13210 K
JP1
CON3
2
4
6
8
10
12
14
2
4
6
8
10
12
14
1
3
5
7
9
11
13
P2
R1191K
R57 33
R58 33
R59 33
TRST_MAINn
TMS_MAIN1
3
5
7
9
11
13
TDI_MAIN
TDO_MAIN R60 33
R60 33TCKR_MAIN
R60 33TCK_MAIN
JTAG_EMU0
C22
0.01 µF
10 V
1
3
5
7
9
11
13
15
17
19
2
4
8
6
12
16
14
10
20
18
P3
HEADER 10x2
VDD_3V3
Sh 6, MPU_nRESET
JTAG_EMU1
VDD_3V3
R67 33
R66, 33
R644.7K
R65
4.7K
VDD_3V3
100K
100K
100K
VDD_3V3
R291 10K
A1
B1
C1
D1
E3
D2
C3
B2
A2
A4
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1OE
2OE
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
VCC
GND
U8
SN74LVC244AGQN
B4
C4
D4
E4
E2
D3
C2
B3
A3
E1C23
0.01 µF
10 V
VDD3V3
TDO
nTRST
TMS
TDI
TCK
RTCK
nEMU0
nEMU1
OMAP5912
T15
R13
M10
U17
P13
T14
U16
N11
P11
76
69
70
71
74
75
72
73
TCK
nEMU1
nEMU0
RTCK
TDO
TMS
nTRST
TDI
P2 is the connector for the 14-pin JTAG connector. Pin 6 is removed and actsas a polarization key for the standard JTAG connector. JP1 is used to set thedefault termination of the nTRST signal to either being pulled down, for thestandard JTAG, or pulled up, for the Multi-ICE interface.
P3 is the connector for the Multi-ICE cable. The polarity of the nTRST signalis different on the Multi-ICE than it is on the standard JTAG.
The U8 buffer is normally enabled via the pull down resistor R291. When theOMAP5912 target module is plugged into a motherboard or other test board,the JTAG interface on the OMAP5912 target module can be disabled by pullingthis pin high. This allows the JTAG signals to used on the other board asneeded. Access to the JTAG signals and the control pin is found on P11.
USB Port
1-64
1.10 USB Port
A standard USB Host Port interface is provided through a standard Type Aconnector. This can be used to connect such devices as:
Keyboard Mouse Digital cameras
The design supports the configuring of the USB port to provide client sidecapabilities. Both host and client operations are discussed.
1.10.1 USB Features
The OMAP5912 USB host controller communicates with USB devices at theUSB low-speed (1.5M bit-per-second maximum) and full-speed (12Mbit-per-second maximum) data rates. It is compatible with the Universal SerialBus Specification Revision 2.0 and the Open HCI—Open Host ControllerInterface Specification for USB, Release 1.0a.
A single USB Type B connector is provided on the OMAP5912 target module.Power is provided by the OMAP5912 target module through this connector topower external devices.
1.10.2 Design Description
Figure 1−32 illustrates the design diagram of the USB interface.
Figure 1−32. USB Host Design
OCEN
IN2IN1
GND
OUT1OUT2OUT3
1
DC
(5) GPIO9(6) USB_PWR_EN
54
32
678
C81220 µFTANT
R97R98
2727
U18
TPS2045
R10110K
R10310K
R10015K
R9915K
R169 1.5K(5) USB_PUEN
(5) USB_DM(5) USB_DP
GND13
57
GND
GNDGND
AB
CD
U19
SN75240PW
86
24
512345
S+5V−DATA+DATAGNDS
P4
USB−A
VDD_3V3
USB Port
1-65OMAP5912 Target Module Major Components
1.10.2.1 Host Operation
The USB.DM, USB.DP, and GPIO9 signals are used on the OMAP5912 toimplement the USB host interface.
USB.DM and USB.DP provide the plus and minus polarity of the interfacesignals directly to the USB connector P4 through a pair of 27 Ω resistors.Initialization of the OMAP5912 device to support this mode of operationrequires proper setting of the top-level pin multiplexing for pins USB.DP andUSB.DM and selection of an HMC_MODE value, which routes a hostcontroller port to pin group 0. OTG_SYSCON_1.USB0_TRX_MODE must beset to 3 to allow proper operation of the integrated USB transceiver.OMAP5912 integrated pull downs for pins USB.DP and USB.DM do not meetthe USB specifications for D+ and D– pull downs. The external 15K pull downresistors, R199 and R100, are implemented to meet this requirement.USB.PUEN is used in the GPIO mode to detect the over current mode. Properinitialization of the OMAP5912 device to support the host mode of operationon pin P4 requires setting of the top-level pin multiplexing.
To select the USB Host mode, GPIO9 needs to be high (default selection), andball P4 on OMAP5912 (USB.PUEN) needs to be placed into high Z state (bysetting FUNC_MUX_CTRL_D[5:3] = 100) in order to negate the impact of the1.5k Ω resistor pull up on the D+ signal.
See section 1.10.2.2, Client Operation, for information on activating the Clientmode of operation.
U16 is a TPS2014 power distribution switch. The TPS2014 power distributionswitches are intended for applications where heavy capacitive loads and shortcircuits are likely to be encountered. The high-side switch is a 95-mWn-channel MOSFET. The switch is controlled by a logic enable that iscompatible with 3-V logic. Gate drive is provided by an internal charge pumpdesigned to control the power switch rise times and fall times to minimizecurrent surges during switching. The charge pump requires no externalcomponents and allows operation from supplies as low as 4 V. When theoutput load exceeds the current-limit threshold or a short is present, theTPS2014 limits the output current to a safe level by switching into aconstant-current mode, and the over-current logic output is set to low.Continuous heavy overloads and short circuits increase the power dissipationin the switch and cause the junction temperature to rise. A thermal protectioncircuit is implemented, which shuts the switch off to prevent damage when thejunction temperature exceeds its thermal limit. An under-voltage lockout isprovided to ensure the switch is in the off state at start-up. The TPS2014 isdesigned to limit at 1.2 A. C81 is a low ESR capacitor required for the outputof the TPS2014.
USB Port
1-66
U19 is a USB port transient protection device. The SN75240 is a dual transientvoltage suppressor designed to provide additional electrical noise transientprotection to two USB ports. Any cabled I/O can be subjected to electricalnoise transients from various sources. These noise transients can causedamage to the OMAP5912 if they are of sufficient magnitude and duration. TheSN75240 significantly increases the port ESD protection level and reduces therisk of damage to the large and expensive circuits of the USB port.
U10 is the TPS65010 power management device. In order to save as manyGPIO pins on the OMAP5912 as possible, the GPIO pin on the TPS65010 wasused as the enable pin for the TPS2014. A high on EN turns off the powerswitch and the bias for the charge pump, driver, and other circuitry to reducethe supply current to less than 10 mA. A logic-zero input restores bias to thedrive and control circuits, and turns the power on. To access the GPIO pin onthe TPS65010, the I2C interface is used to communicate to the GPIO pin.
Access to the USB.DM, USB.DP, and USB.PUEN (GPIO58) signals can beobtained through the B connector P10, if use by the expansion cards isdesired. For this to happen, nothing can be plugged into the USB connectorP4.
1.10.2.2 Client Operation
With the use of an external adapter (See section 3.11, USB Client Adapter),the USB interface can be converted for use as a Client interface.
Resistor R169 is connected to the USB_PUEN signal as shown inFigure 1−32. USB_PUEN is required to activate the client interface. In the hostmode, this pin is left tri-stated. By default U18 is not enabled. This must be leftdisabled in the Client mode.
The external adapter connects to P4 and converts it to the client gender. R169is used to signal the host that Client mode is active and ready to be identified.This does not interfere with host operation as the USB.PUEN signal is notactivated through software.
To select USB Client (function) with the use of an external adapter, GPIO9must be low, and the USB.PUEN signal must be muxed onto the P4 ball (setFUNC_MUX_CTRL_D[5:3] = 000).
USB Port
1-67OMAP5912 Target Module Major Components
1.11 Serial Port
Access to a single serial port with an RS232 level driver through a DB9connector is provided. This is used for downloading and connecting to a serialdebugger or terminal device.
1.11.1 Features
Features of the serial interface are:
Default OMAP5912 UART1 connection Optional OMAP5912 UART3 connection 240K baud max speed DB9 male connector Disable pin accessible through the expansion connectors TX,RX signals Ground
1.11.2 Design Description
Figure 1−33 illustrates the design diagram of the serial interface.
Figure 1−33. Serial Port Interface
R115
R116
0, 0603
n.m. 0, 0603
R117
R118
0, 0603
n.m. 0, 0603
T12
K17
U13
K15
43
47
42
45
53
R1200, 0603
2
5
3
4
UART1.TX
UART3.TX
UART1.RX
UART3.RX
OMAP5912
B Conn
R10210K
C420.1 µF
10V
5
6
11
9
1
12
0.1 µF10V
C40
4
2
VDD_3V3
C1+
C1−
C2+
C2−
DIN
ROUT
EN
FORCEON
GND
14
U14
MAX3221
FORCEOFF
INVALID
RIN
DOUT
16
10
13
8
VCC
C380.1 µF10V
VDD_3V3
U6SN74AHC1G04DCKR
10V
C410.1 µF
C390.1 µF10V
V−
V+
RS232_TX1
RS232_RX1
5
9
4
8
3
7
2
6
1
11
DSUB9Male
10
P8
USB Port
1-68
Serial port UART1 is the default serial port used from the OMAP5912. The portcan be switched to UART3 by removing R115 and R117 and installing R116and R118. R116 and R118 are not populated on the board.The UART1 andUART3 signals from the OMAP5912 are also available on ExpansionConnector B for use by the expansion cards. If the use of these signals isneeded, pin 53 on the B Connector can be pulled high and the RS232 driveris disabled through the SN74AHC1G04 inverter.
The RS232 driver function is performed by U14, a TI MAX3221, whichconverts the signals from the OMAP5912 to the required RS232 levels. Theoutput levels of the MAX3221 swing + 3 V and − 3 V. While this is more thanadequate to drive a terminal or PC located in the area, it may not be adequateto drive over long distances. If long distance is a requirement, the signals needto be boosted to higher levels.
Pins 4 and 6 are looped back on each other to allow for the detection of theOMAP5912 target module by the applications running on the PC.
Ethernet
1-69OMAP5912 Target Module Major Components
1.12 Ethernet
The OMAP5912 target module is equipped with a 10Mb Ethernet port. Thissection describes the Ethernet interface and how it connects to theOMAP5912 processor.
1.12.1 Ethernet Circuit Design
Figure 1−34 illustrates the design of the Ethernet interface on the OMAP5912target module.
Figure 1−34. 10 Mb Ethernet Design
ENEEPEEDQ/SDOUTEEDIEECSEESKINTR0/IREQ/INTRINTR1/INPACKINTR2/DTACK/0INTR3/DTACT/1IOCS16/IOIS16SBHE/CE2BALE/WEIORD/XDSIOWR/R/WMEM/OEAEN/REG/ASIOCHRDY/WAITRESETPWRDWN/TXCLKBSELED/RXDLINKLED/TXDRXLED/RXCLKTXLED/TXENTPETXPDTPETXPTPETXDNTPETXNTXN/CRSTXP/COLLCOLNCOLPRECNRECPTPERXNTPERXPRBIASXENDECEN16OM/PCMCIAXTAL1XTAL2IOS0IOS1IOS2
11 19 38 48 8959 71 79 98
VDD_3V3
VDD AVDDVDD
D0D1D2D3D4D5D6D7D8D9
D10D11D12D13D14D15
A0A1A2A3A4A5A6A7A8A9
A10/FWEA11/FCS
A12A13A14A15A16A17A18
A19/CE1
100
Grounded pins
LAN91C96−TQFP
55 FLASH.D056 FLASH.D1
5857
FLASH.D3FLASH.D2
63626160
FLASH.D7FLASH.D6FLASH.D5FLASH.D4
FLASH.D989 FLASH.D10
7 FLASH.D8
1514131210
FLASH.D15FLASH.D14FLASH.D13
FLASH.D11FLASH.D12
2627283031323334353637394041424344454647
VDD_3V3
OMAP5912
nFLASH.CS1AFLASH.A24FLASH.A23
LAN_INTROLAN_RESETnFLASH.WEnFLASH.OE
12345
1820
17
49
52
5051
21
2425
23
68
80
8281
7677
7473
7572
6970
53
6667
65
95
88
91
9493
90
8485
83
9799
963 2
C7920pF
10V 10V
20pF
C78
R12110K
R9610K
LAN_INTRO
nFLASH.OEnFLASH.WE
FLASH.RDYLAN_RESET
DIDOCSSK
3412
GND
VCC
ORGDC
FXP200−20
20.000 MHz
R12210K
4
Chip select
C430.01µF10V
VDD_3V3
67
8
U13AT93C46
D5LEDRED
TXLED
R123330
0603 0603330
R124
RXLEDYELLEDD6
R126
BSELEDYEL
D8LED
33006030603
330R125
LINKEDGRNLEDD7
VDD_3V3
R127 13R128 5.1
R130R129
5.113
TX+TXCT
TX−RX+
RXCTRX−
R131 100
153161214
TD+
RD−
TD−
RD+
T1
E2009
86
911
22K
R133
12345678
P9
RJ45
A1A2A3A4A5A6A7A8S0 S1
R160
0.0603GND AGND
Ethernet
1-70
The following sections break down the design and provide detailed descriptionof each section. Included in the descriptions are:
Interrupt Memory address decode LAN91C96™ Crystal circuit Output section EEPROM Status LEDS
1.12.2 Interrupt
The interrupt line from the LAN91C96 device connects to GPIO0 on theOMAP5912. Pin 93 nROM/nPCMCIA is open, which puts the LAN91C96 inLocal Bus mode. In this mode the LAN_INTR0 is an active high line. On theschematic the signal LAN_INTR0 is shown to be active high.
1.12.3 Memory Address Decode
The second half of U4, a 74LVC139™ device from Phillips Electronics, is usedto create the address decode for the Ethernet controller and the CompactFlash. Figure 1−35 illustrates the design of the decode circuit.
Figure 1−35. Ethernet Address Decode Logic
14
13
15
A
B
GGND
VSS Y0
Y1
Y2
Y3
VDD_3V3
16
8
U4B
74LVC139
12
11
10
9
(2,9) FLASH.A23
(2,9) FLASH.A24
(2,9) nFLASH.CS1A
R162 NO_POP
R163 0
R161(2,9) nFLASH.CS2
0500:0000 − 057F:FFFF
0580:0000 − 05FF:FFFF
0480:0000 − 04FF:FFFF
CFLASH_EN (8)
nEX_CS3(5)
nEX_CS4(5)0400:0000 − 047F:FFFF
CS1A can be shared with the Compact Flash circuit or the Compact Flashcircuit can have its own address chip select. There are two different scenariosthat are supported by this design:
Compact Flash and Ethernet share CS1A Compact Flash uses CS2 and Ethernet uses CS1A
The default configuration is that the Compact Flash occupies CS2 and theEthernet occupies CS1A.
Ethernet
1-71OMAP5912 Target Module Major Components
1.12.3.1 Chip Select Shared
CS1A from the OMAP5912 is used as the primary chip select. Address linesA24 and A23 from the OMAP5912 are also used to minimize the amount of theCS1A block that is being used by the LAN91C96. Address line A24 must below and A23 must be high to select the LANC9196 device. This results in aneffective address range of 0480:0000−04FF:FFFF for the Compact Flash. Useaddress 0490:0000 as the base address for the LAN91C96 in this scenario.
1.12.3.2 Compact Flash CS2 and Ethernet CS1A
The Compact Flash is mapped to CS2 and the Ethernet is mapped to CS1Aas the default configuration.
1.12.3.3 Expansion Chip Selects
Two signals are provided for use by the expansion cards. These are nEX_CS3and nEX_CS4. These signals are brought out onto the expansion connectors.
1.12.4 LAN91C96
The LAN91C96 Ethernet Transceiver from SMSC provides the interface forthe Ethernet function on the OMAP5912 target module. The features of theLAN91C96 are:
ISA/PCMCIA single-chip ethernet controller
A subset of Motorola 68000 Bus Interface Support
Supports full duplex switched ethernet
Supports enhanced Transmit Queue Management
6K bytes of on-chip RAM
Supports IEEE 802.3 (ANSI 8802-3) Ethernet Standards
Automatic detection of TX/RX polarity reversal
Simultasking early transmit and early receive functions
Enhanced early transmit function
Receive counter for enhanced early receive
Hardware memory management unit
Optional configuration via Serial EEPROM interface (jumperless)
Ethernet
1-72
Supports single + 3.3 V VCC Designs
6 Bit Data and Control Paths
Fast Access Time (40 ns)
Pipelined Data Path
Handles Block Word Transfers for any Alignment
High Performance Chained (”Back-to-Back”) Transmit and Receive
Dynamic Memory Allocation Between Transmit and Receive
Flat Memory Structure for Low CPU Overhead
Buffered Architecture, Insensitive to Bus Latencies (NoOverruns/Underruns)
Integrated 10BASE-T Transceiver Functions:
Driver and Receiver
Link Integrity Test
Receive Polarity Detection and Correction
10 Mb/s Manchester Encoding/Decoding and Clock Recovery
Automatic Retransmission, Bad Packet Rejection, and Transmit Padding
External and Internal Loopback Modes
Four Direct Driven LEDs for Status/ Diagnostics
1.12.5 Crystal
An external 20 MHZ crystal is used to supply the clock source for theLAN91C96. The crystal was chosen as a lower cost option.
Ethernet
1-73OMAP5912 Target Module Major Components
1.12.6 Output Section
Figure 1−36 shows the design of the output section of the Ethernet circuitry.
Figure 1−36. Ethernet Output Section
ENEEP
EEDQ/SDOUT
EEDI
EECS
EESK
INTR0/IREQ/INTR
INTR1/INPACK
INTR2/DTACK/0
INTR3/DTACT/1
IOCS16/IOIS16
SBHE/CE2
BALE/WE
IORD/XDS
IOWR/R/W
MEM/OE
AEN/REG/AS
IOCHRDY/WAIT
RESET
PWRDWN/TXCLK
BSELED/RXD
LINKLED/TXD
RXLED/RXCLK
TXLED/TXEN
TPETXPD
TPETXP
TPETXDN
TPETXN
TXN/CRS
TXP/COLL
COLN
COLP
RECN
RECP
TPERXN
TPERXP
RBIAS
XENDEC
EN16
OM/PCMCIA
XTAL1
XTAL2
IOS0
IOS1
IOS2
11 19 38 48 8959 71 79 98
VDD AVDDVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/FWE
A11/FCS
A12
A13
A14
A15
A16
A17
A18
A19/CE1
LAN91C96−TQFP
55
56
58
57
63
62
61
60
8
9
7
15
14
13
12
10
26
27
28
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
47
1
2
3
4
5
18
20
17
49
52
50
51
21
24
25
23
68
80
82
81
76
77
74
73
75
72
69
70
53
66
67
65
95
88
91
94
93
90
84
85
83
97
99
96
R127 13
R128 5.1
R130
R129
5.1
13TX+
TXCT
TX−
RX+
RXCT
RX−
R131 100
1
5
3
16
12
14
TD+
RD−
TD−
RD+
T1
E2009
8
6
9
11
1
2
3
4
5
6
7
8
P9
RJ45
A1
A2
A3
A4
A5
A6
A7
A8S0 S1
GND AGND
Ethernet
1-74
1.12.7 EEPROM
Figure 1−37 is the interface between the EEPROM and the LAN91C96Ethernet Controller.
Figure 1−37. Ethernet EEPROM
ENEEP
EEDQ/SDOUT
EEDI
EECS
EESK
INTR0/IREQ/INTR
INTR1/INPACK
INTR2/DTACK/0
INTR3/DTACT/1
IOCS16/IOIS16
SBHE/CE2
BALE/WE
IORD/XDS
IOWR/R/W
MEM/OE
AEN/REG/AS
IOCHRDY/WAIT
RESET
PWRDWN/TXCLK
BSELED/RXD
LINKLED/TXD
RXLED/RXCLK
TXLED/TXEN
TPETXPD
TPETXP
TPETXDN
TPETXN
TXN/CRS
TXP/COLL
COLN
COLP
RECN
RECP
TPERXN
TPERXP
RBIAS
XENDEC
EN16
OM/PCMCIA
XTAL1
XTAL2
IOS0
IOS1
IOS2
11 19 38 48 8959 71 79 98
VDD AVDDVDD
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/FWE
A11/FCS
A12
A13
A14
A15
A16
A17
A18
A19/CE1
LAN91C96−TQFP
55
56
58
57
63
62
61
60
8
9
7
15
14
13
12
10
26
27
28
30
31
32
33
34
35
36
37
39
40
41
42
43
44
45
46
47
1
2
3
4
5
18
20
17
49
52
50
51
21
24
25
23
68
80
82
81
76
77
74
73
75
72
69
70
53
66
67
65
95
88
91
94
93
90
84
85
83
97
99
96
DI
DO
CS
SK
3
4
1
2
GND
VCC
ORG
DC
R12210K
C430.01µF10V
VDD_3V3
6
7
8
U13
AT93C46
VDD_3V3
GND AGND
R1600,06035
The LAN91C96 has the ability to retrieve configuration information from aserial EEPROM on reset or power-up. The serial EPROM acts as storage ofconfiguration and IEEE Ethernet address information.
Ethernet
1-75OMAP5912 Target Module Major Components
The device used is the AT93C46™ EEPROM from Atmel Corporation. TheAT93C46 provides 1024 bits of serial electrically erasable programmable readonly memory (EEPROM) organized as 64 words of 16 bits each. The ORG pinis pulled high, which controls the bit configuration.
Pin 1 on the LAN91C96 is the EEPROM enabled pin. It has an internal pull-upin the LAN91C96. If the EEPROM is not to be used, then R160 must bepopulated. The default is that R160 is not installed. Power for the AT93C46 isprovided by the 3.3 V voltage rail, which is the same rail as is used by theLAN91C96.
1.12.8 Status LEDS
There are four status LEDS on the LAN91C96 device. Table 1−13 defines themeaning of each LED and the corresponding color for each LED and how eachof the status LEDS are used by the LANC9196.
Table 1−13. Ethernet Status LEDs
LED Function
TX Activated by transmit activity.
RX Activated by receive activity.
LINK Reflects the link integrity status.
BSE Board select LED. Activated when the board space is accessed, namely on accesses to theLAN91C96 register space or the ROM area decoded by the LAN91C96. The signal is stretched to125 ms.
2-1
Expansion Connectors
This section defines the type and pinout of the expansion connectors for thesystem. In order to insure proper operation of the system, the functions of eachpin on the connector are static. Not all pins on the connectors are used by allprocessors.
A lot of the pins have multiple functions that they can perform. All of theexpansion cards have access to all of the functions found on each pin ifneeded. The default naming convention does not show any additionalfunctions in the name; however, the additional functions are defined in theOMAP5912 Applications Processor (literature number SPRS231) data sheet.If certain signals are used by the OMAP5912 target module in something otherthan the default mode, this is also indicated. Descriptions for the signals onlycover the signal as it is used on the OMAP5912 target module.
The following sections cover each of the four expansion connectors.
Topic Page
2.1 Connector A 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Connector B 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Connector C 2-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Connector D 2-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 Connector Specification 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2
Connector A
2-2
2.1 Connector A
Connector A contains the Flash Bus and its control signals. It also contains theSD/MMC interface for the OMAP5912. Table 2−1 shows the pinout of the AConnector.
Table 2−1. Connector A Pinout
Name No. Name Name
GND 1 2 GND
GND 3 4 GND
3.3 V 5 6 3.3 V
3.3 V 7 8 3.3 V
9 10
MPU_BOOT 11 12 MMC.CMD
MMC.DAT2 13 14 MMC.DAT3
MMC.DAT0 15 16 MMC.DAT1
MMC.CLK 17 18 FLASH.ADV
FLASH.RDY 19 20 FLASH.CLK
FLASH.BE0 21 22 FLASH.BE1
FLASH.WE 23 24 FLASH.WP
FLASH.RP 25 26 FLASH.OE
FLASH.CS3 27 28 FLASH.CS2U
FLASH.CS2 29 30 FLASH.CS1U
FLASH.CS1 31 32 FLASH.D[15]
FLASH.D[14] 33 34 FLASH.D[13]
FLASH.D[12] 35 36 FLASH.D[11]
FLASH.D[10] 37 38 FLASH.D[9]
FLASH.D[8] 39 40 FLASH.D[7]
FLASH.D[6] 41 42 FLASH.D[5]
FLASH.D[4] 43 44 FLASH.D[3]
FLASH.D[2] 45 46 FLASH.D[1]
Connector A
2-3Expansion Connectors
Table 2−1. Connector A Pinout (Continued)
Name NameNameNo.
FLASH.D[0] 47 48 GPIO1
FLASH.A25 49 50 FLASH.A24
FLASH.A23 51 52 FLASH.A22
FLASH.A21 53 54 FLASH.A20
FLASH.A19 55 56 FLASH.A18
FLASH.A17 57 58 FLASH.A16
FLASH.A15 59 60 FLASH.A14
FLASH.A13 61 62 FLASH.A12
FLASH.A11 63 64 FLASH.A10
FLASH.A9 65 66 FLASH.A8
FLASH.A7 67 68 FLASH.A6
FLASH.A5 69 70 FLASH.A4
FLASH.A3 71 72 FLASH.A2
FLASH.A1 73 74 nEX_CS3
nEX_CS4 75 76 FLASH_DIS
GND 77 78 GND
GND 79 80 GND
Connector B
2-4
2.2 Connector BExpansion Connector B contains the serial buses such as SPI, McBSP, MCSI,and standard serial ports. Table 2−2 shows the pin out of the B connector.
Table 2−2. Expansion Connector B Pin Out
Name No. Name
GND 1 2 GND
GND 3 4 GND
DC 5 6 DC
DC 7 8 DC
3.3 V 9 10 3.3 V
3.3 V 11 12 3.3 V
NC 13 14 NC
RTC_WAKE_INT 15 16 MCBSP1.FSX
MCSI1.SYNC 17 18 MCSI1.CLK
MCSI1.DIN 19 20 MCSI1.DOUT
MCSI2.SYNC 21 22 MCSI2.CLK
MCSI2.DIN 23 24 MCCS2.DOUT
BCLK 25 26 MCLK_REQ
BCLK_REQ 27 28 CLK32K_OUT
MCLK 29 30 MCBSP1.DX
MCBSP1.CLKS 31 32 MCBSP1.DR
NC 33 34 NC
MCBSP1.CLKX 35 36 MCBSP2.DR
MCBSP2.FSR 37 38 MCBSP2.CLKX
MCBSP2.DX 39 40 MCBSP2.CLKR
MCBSP2.FSX 41 42 UART3.TX
UART3.RX 43 44 UART1.RTS
UART1.Tx 45 46 UART1.CTS
UART1.RX 47 48 UART2.CTS
Connector B
2-5Expansion Connectors
Table 2−2. Expansion Connector B Pin Out (Continued)
Name NameNo.
UART2.TX 49 50 UART2.RX
UART2.RTS 51 52 UART2.BCLK
UART1.DIS 53 54 BFAIL
USB_DM 55 56 RTC_ON_OFF
USB_DP 57 58 USB_PUEN
RESET_IN 59 60 nRESET_OUT
GPIO 4 61 62 GPIO 8
MCBSP3.CLKX 63 64 GPIO 11
MPUI04 65 66 MPUI03
JTAG_DIS 67 68 GPIO62
nTRST 69 70 TMS
TDI 71 72 nEMU0
nEMU1 73 74 TCK
RTCK 75 76 TDO
GND 77 78 GND
GND 79 80 GND
Connector C
2-6
2.3 Connector CExpansion Connector C contains the camera, LCD, GPIO, I2C, and GPIOpins. Table 2−3 shows the pin out of the C connector.
Table 2−3. Connector C Pin Out
Name No. Name
GND 1 2 GND
GND 3 4 GND
DC 5 6 DC
DC 7 8 DC
3.3 V 9 10 3.3 V
3.3 V 11 12 3.3 V
NC 13 14 NC
GPIO7 15 16 GPIO 3
GPIO2 17 18 GPIO 6
GPIO 9 19 20 GPIO 13
GPIO 12 21 22 GPIO 15
GPIO14 23 24 MPUIO2
MPUIO1 25 26 CAM.EXCLK
CAM.D0 27 28 CAM.D1
CAM.D2 29 30 CAM.D3
CAM.D4 31 32 CAM.D5
CAM.D6 33 34 CAM.D7
CAM.LCLK 35 36 CAM.HS
CAM.VS 37 38 CAM.RST
I2C.SDA 39 40 I2C.SCL
LCD.P0 41 42 LCD.P1
LCD.P2 43 44 LCD.P3
LCD.P4 45 46 LCD.P5
LCD.P6 47 48 LCD.P7
Connector C
2-7Expansion Connectors
Table 2−3. Connector C Pin Out (Continued)
Name NameNo.
LCD.P8 49 50 LCD.P9
LCD.P10 51 52 LCD.P11
LCD.P12 53 54 LCD.P13
LCD.P14 55 56 LCD.P15
LCD.PCLK 57 58 LCD.AC
LCD.VS 59 60 LCD.HS
KB.C0 61 62 KB.C1
KB.C2 63 64 KB.C3
KB.C4 65 66 KB.C5
KB.R0 67 68 KB.R1
KB.R2 69 70 KB.R3
KB.R4 71 72 UWIRE.SDI
UWIRE.CS0 73 74 UWIRE.CS3
UWIRE.SDO 75 76 UWIRE.SCLK
GND 77 78 GND
GND 79 80 GND
Connector D
2-8
2.4 Connector D
Expansion connector D is mainly reserved for future expansion to allow othercards that meet the OMAP5912 target module form factor, but needsadditional signals to be routed to the expansion cards. Table 2−4 shows thepin out of the D connector.
Table 2−4. Expansion Connector D Pin Out
Name No. Name
GND 1 2 GND
GND 3 4 GND
DC 5 6 DC
DC 7 8 DC
3.3 V 9 10 3.3 V
3.3 V 11 12 3.3 V
13 14
GND 15 16 VLYNQ.TX1
GND 17 18 VLYNQ.TX0
GND 19 20 VLYNQ.CLK
GND 21 22 VLYNQ.RX1
GND 23 24 VLYNQ.RX0
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
Connector D
2-9Expansion Connectors
Table 2−4. Expansion Connector D Pin Out (Continued)
Name NameNo.
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
63 64
65 66
67 68
69 70
71 72
73 74
75 76
GND 77 78 GND
GND 79 80 GND
Connector Specification
2-10
2.5 Connector Specification
Each expansion connector is a Hirose FX2 series 1.27 mm pitch connector.This is required due to the minimum height restrictions from board to board.This connector and the mating connector give a .484”(12.3 mm) spacingbetween cards. Figure 2−1 is a picture of the connector.
Figure 2−1. Expansion Connector
Each connector has 2 rows with 40 pins per row. The Hirose part number forthe connector is FX2−80P−1.27SV. The target module uses the header part.The connector is a surface mount device. Surface mount connectors arerequired for the Expansion cards to allow for connectors to be placed on bothsides of the board and still be aligned with each other.
3-1
I/O Connectors
This section defines the pin outs of each of the I/O connectors on theOMAP5912 target module.
Topic Page
3.1 Serial 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Ethernet 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 JTAG 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 MultiICE 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 DC Power 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Compact Flash 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Headphones 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Line In 3-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.9 Microphone In 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.10 USB Host 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.11 USB Client Adapter 3-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 3
Serial
3-2
3.1 Serial
Table 3−1 defines the pin out of the DB9 connector on the OMAP5912 targetmodule.
Table 3−1. Serial Connector Pin out
Description Name No. Name Description
1 2 RX Receive Input
Transmit Output TX 3 4
Ground GND 5 6
7 8
9
All other pins on the DB9 connector are not connected.
3.2 Ethernet
Table 3−2 defines the pin out of the RJ45 connector.
Table 3−2. Ethernet Pin out
No. Name Description
1 TX+ Plus side of transmit pair
2 TX− Minus side of receive pair
3 RX+ Plus side of receive pair
4
5
6 RX− Minus side of receive pair.
7
8
JTAG
3-3I/O Connectors
3.3 JTAG
Figure 3−1 defines the pin out of the JTAG connector on the OMAP5912 targetmodule.
Figure 3−1. JTAG Pinout
1
3
5
7
9
11
13
2
4
6
8
10
12
14
TRST
GND
NC
GND
GND
GND
EMU1
TMS
TDI
3.3 V
TDO
TCKR
TCK
EMU0
Multi-ICE
3-4
3.4 Multi-ICE
Figure 3−2 is the pin out of the Multi-ICE connector.
Figure 3−2. Multi-ICE Connector Pin Out
1
3
5
7
9
11
13
15
17
19
2
4
6
8
10
12
14
16
18
20
Vsupply
GND
GND
GND
GND
GND
GND
GND
GND
GND
VTref
nTRST
TDI
TMS
TCK
RTICK
TDO
nSRST
DBGRQ
DBGACK
DC Power
3-5I/O Connectors
3.5 DC Power
Figure 3−3 shows the pin configuration of the DC connector on theOMAP5912 target module.
Figure 3−3. DC Power Jack Pin Out
DC
GND
3.6 Compact Flash
Table 3−3 is the pin out of the Compact Flash connector.
Table 3−3. Compact Flash Connector Pin Out
Function Function
Mem I/O Pin Mem I/O
GND −−− 1 26 −−> nCD1
D03 <−> 2 27 <−> D11
D04 <−> 3 28 <−> D12
D05 <−> 4 29 <−> D13
D06 <−> 5 30 <−> D14
D07 <−> 6 31 <−> D15
nCE1 −−> 7 32 <−− nCE2
A10 −−> 8 33 −−> nVS1
!OE −−> 9 34 <−− NU nIORD
A09 −−> 10 35 <−− NU nIOWR
Compact Flash
3-6
Table 3−3. Compact Flash Connector Pin Out (Continued)
Function Function
PinMem I/OMemPinI/O
A08 −−> 11 36 <−− nWE
A07 −−> 12 37 −−> RDY/BSY IREQ
VCC −−− 13 38 −−− VCC
A06 −−> 14 39 <−− nCSEL
A05 −−> 15 40 −−> nVS2
A04 −−> 16 41 <−− RESET
A03 −−> 17 42 −−> nWAIT
A02 −−> 18 43 −−> NU nINPACK
A01 −−> 19 44 <−− nREG
A00 −−> 20 45 <−> BVD2(H) nSPKR
D00 <−> 21 46 <−> BVD1(H) !STSCHG
D01 <−> 22 47 <−> D08
D02 <−> 23 48 <−> D09
WP !IOIS16 −−> 24 49 <−> D10
nCD2 <−− 25 50 −−− GND
Figure 3−4 is the mechanicals of the CF connector used on the OMAP5912target module.
Compact Flash
3-7I/O Connectors
Figure 3−4. Compact Flash Connector
Headphones
3-8
3.7 Headphones
Table 3−4 is the pin out of the headphone jack. Figure 46 gives the locationsof the pin numbers.
Table 3−4. Headphone Pin out
Description Name No.
Left Channel Out Left 1
2
3
Right Channel Out Right 4
Ground GND 5
Figure 3−5. Headphone Pin out
1
2
3
4
5
Line In
3-9I/O Connectors
3.8 Line In
Table 3−5 is the pin out of the Lin In jack on the OMAP5912 target module.Figure 3−6 gives the pin out of the connector.
Table 3−5. Line In Pin Out
Description Name No.
Left Channel In Left In 1
2
3
Right Channel IN Right In 4
Ground GND 5
Figure 3−6. Line In Pin Out
1
2
3
4
5
Microphone In
3-10
3.9 Microphone In
Table 3−6 is the pin assignments for the Microphone input jack. Figure 3−7gives the pin out of the connector.
Table 3−6. Microphone Input Pin Out
Description Name No.
Ground GND 1
Microphone In MIC In 2
3
4
5
Figure 3−7. Microphone Jack Pin Out
1
2
3
4
5
3.10 USB Host
Table 3−7 gives the pin out of the USB host connector.
Table 3−7. USB Host Pinout
Description Name No.
+ 5 V power output + 5 V 1
Negative polarity data − DATA 2
Positive polarity data + DATA 3
Ground GND 4
USB Client Adapter
3-11I/O Connectors
3.11 USB Client Adapter
Figure 3−8 is the adapter used to convert the Host interface to the Clientinterface.
Figure 3−8. USB Client Adapter
This adapter is made by Video Products Inc.
Part Number Description UPC Code
USBAF−USBBF USB Adapter and Gender Changers : USB AFemale to B Female Adapter
It can be purchased at www.vpi.us
4-1
Mechanical Specifications
This section defines the physical requirements for each of the card types.
Topic Page
4.1 OMAP5912 Target Module Card 4-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 4
OMAP5912 Target Module Card
4-2
4.1 OMAP5912 Target Module Card
This section defines the mechanical dimensions and configuration of theOMAP5912 target module card. The exact dimensions of the module aresubject to change based on the final layout of the PCB. Figure 4−1 gives thegeneral outline and component placement of the OMAP5912 target modulefrom the top side.
Figure 4−1. OMAP5912 Target Module Top Side
5,550”
3,550”
Figure 4−2 shows the OMAP5912 target module from the back side.
OMAP5912 Target Module Card
4-3Mechanical Specifications
Figure 4−2. OMAP5912 Target Module Back Side
5-1
Component Locations
The following sections describe where on the OMAP5912 target module thedifferent components can be found.
Topic Page
5.1 Key Components 5-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.2 Connectors and Jumpers 5-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5.3 Indicators 5-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 5
Key Components
5-2
5.1 Key Components
Figure 5−1 shows the key components on the top side of the OMAP5912target module.
Figure 5−1. OMAP5912 Target Module Key Top Side Components
Ethernet LEDsFLASH
EthernetAIC23
uuICE
JTAG OMAP5912DDR SDRAM
TPS65010
Connectors and Jumpers
5-3Component Locations
5.2 Connectors and Jumpers
Figure 5−2 defines the connectors and jumpers for the OMAP5912 targetmodule.
Figure 5−2. OMAP5912 Target Module Connectors
EthernetHeadphones
USB Port
RS232
RESET
LINE IN
LINE OUT
DC IN
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
uuICE
JTAG
JP1
ÉÉÉÉÉÉÉÉÉÉÉÉ
ÉÉÉÉ
Full boot
Fast boot
JP3
Indicators
5-4
5.3 Indicators
Figure 5−3 shows the placement of the indicators on the OMAP5912 targetmodule.
Figure 5−3. OMAP5912 Target Module Indicators
LED GPIO
Power
Flashing LED
RX
TXBSEL
LINK
A-1
Appendix A
Component Locations
The following figures illustrate the board layouts for the OMAP5912 targetmodule.
Topic Page
A.1 Top Side Component Locations A-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
A.2 Bottom Side Component Locations A-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix A
Top Side Component Locations
A-2
A.1 Top Side Component Locations
Bottom Side Component Locations
A-3Component Locations
A.2 Bottom Side Component Locations
B-1
Appendix A
OMAP5912 Target Module Dimensions
5,550
3,550
3,250
5,250
.125 DIA., 4 PLCS.
0.150
0.150
Appendix B
B-2
3,550
3,259
0.150
0.125
5,250
2,500
5,550
3,000
0.400
0.150
C-1
Appendix A
OMAP5912 Target Module Schematics
This appendix contains the schematics for the OMAP5912 target module.
Appendix C
Appendix C- Schematics
G. Coley
Revision A release.
NO
TE
S:
Version
A1
Date
G. Coley
Updated Symbol to official symbol. Make corrections for a few typos.
1. All resisto
rs are in th
e 0402 packag
e un
less oth
erwise sp
ecified.
2. Th
ere is an E
SD
ring
arou
nd
the o
uter ed
ges o
f the b
oard
on
the to
pan
d b
otto
m sid
e.
A
1
OM
AP
5912 Starter K
it
B
110
Monday
, July 26, 2004
G. C
oley
Notes P
ageTitle :
Size
Docum
ent Num
berR
ev
Date:
Sheet
of
12203 Southw
est Freew
ayS
tafford, Texas 77477
Ca
talog O
MA
P G
roup
Modified by
:
This document contains
information on a product under
developm
ent and is issued forev
aluation purposes only.
Features characteristic data
and other information are
subject to change.
3. Th
e ES
D rin
g is co
nn
ected to
the stan
do
ffs and
extend
s arou
nd
the ed
ge o
f the b
oard
.
Author
Notes
A
7/26/04
5/11/04
VD
D_3V
3
FLA
SH
.A23
R12
0
R17
0
FLA
SH
.A24
FLA
SH
.D9
FLA
SH
.RD
Y
FLA
SH
.D2
FLA
SH
.D8
FLA
SH
.A21
FLA
SH
.A15
nFLA
SH
.CS
1B(9)
nFLA
SH
.BE
0
nFLA
SH
.CS
2
FLA
SH
.D1
FLA
SH
.D11
RN
6
RP
AC
K8-22
116
215
314
413
512
611
710
89
R7
0
R13
0
nFLA
SH
.BE
0
FLA
SH
.A15
FLA
SH
.D9
FLA
SH
.A24
CS
1B
nFLA
SH
.RP
(9)
FLA
SH
.A19
R19
0
R9
0
FLA
SH
.D[0..15]
(8,9,10)
FLA
SH
.A7
FLA
SH
.A2
FLA
SH
.A22
FLA
SH
.A22
R211
22
R30
10K
FLA
SH
.A19
nFLA
SH
.OE
(8,9,10)
VD
D_3V
3
FLA
SH
.D1
VD
D_3V
3
FLA
SH
.D14
FLA
SH
.A3
R27
0
FLA
SH
.D0
R21
0
nFLA
SH
.BE
0(8,9)
FLA
SH
.D14
R10
0
R2
0
X
R213
22
X
FLA
SH
.D4
FLA
SH
.A3
R28
0
R
nFLA
SH
.WP
nFLA
SH
.CS
1B
FLA
SH
.D6
nFLA
SH
.WP
FLA
SH
.D6
Offset
FLA
SH
.D0
FLA
SH
.A14
FLA
SH
.A13
FLA
SH
.A20
SLOT 2
0600:0000X
GP
IO1
(9)
FLA
SH
.A5
FLA
SH
.A[1..25]
(8,9,10)
FLA
SH
.A25
R209
22
R23
0
U2
28FxxxK
3 [J3] (4-32 MB
ytes)
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
F2
E2
G3
E4
E5
G5
G6
H7
E1
E3
F3
F4
F5
H5
G7
E7
H2
B2
H4
B4
F8
G8
D4
C6
C8
E6
F6
F7
A8
G1
H8
H3
A6
D5
H6
D6
A4
G2
H1
F1
B6
G4
E8
B8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VS
SQ
[DN
U]
VS
SV
SS
CE
OE
WE
RP
WP
[DN
U]
A20
CLK
[DN
U]
AD
V[D
NU
]W
AIT[D
NU
]
A21
A22
A23[N
C]
VC
CV
CC
VC
CQ
VS
SQ
[VS
S]
VC
CQ
[DN
U]
VP
EN
RF
U[A
0]R
FU
[CE
2]R
FU
[BY
TE]
RF
U
VC
CQ
STS
RF
U[C
E1]
P
0C00:0000
nFLA
SH
.CS
XB
FLA
SH
.A13
M
FLA
SH
.D1
CS
3
FLA
SH
.D5
FLA
SH
.A21
FLA
SH
.D3
FLA
SH
.A6
FLA
SH
.A16
R32
0
FLA
SH
.D13
FLA
SH
.RD
Y
R35
0
CS
2
FLA
SH
.D8
RN
3R
PA
CK
8-22
116
215
314
413
512
611
710
89
nFLA
SH
.RP
FLA
SH
.A5
FLA
SH
.D4
RN
2
RP
AC
K8-22
116
215
314
413
512
611
710
89
nFLA
SH
.CS
XA
FLA
SH
.D11
FLA
SH
.A16
FLA
SH
.DIS
(9)
FLA
SH
.A22
R18
0
NOR FLASH
FLA
SH
.A8
FLA
SH
.A8
EM
IFS
U3E
OM
AP
5912-ZD
Y
L6K
1L1M
1L2J7M
2L4K
6N
1L5N
2M
4M
3K
7P
1R
1N
4
D3
C2
E4
E3
D2
C1
E2
D1
E1
F2
F1
F5
G3
G4
G2
G5
G6
H3
H4
F4
H5
H2
J2J4J3J8 J6M5
P3
K2
J1H6
R3
N3
F3
K3
H14
T1M15
FLA
SH
.RD
YF
LAS
H.C
LKF
LAS
H.D
[0]F
LAS
H.D
[1]F
LAS
H.D
[2]F
LAS
H.D
[3]F
LAS
H.D
[4]F
LAS
H.D
[5]F
LAS
H.D
[6]F
LAS
H.D
[7]F
LAS
H.D
[8]F
LAS
H.D
[9]F
LAS
H.D
[10]F
LAS
H.D
[11]F
LAS
H.D
[12]F
LAS
H.D
[13]F
LAS
H.D
[14]F
LAS
H.D
[15]
FLA
SH
.A[1]
FLA
SH
.A[2]
FLA
SH
.A[3]
FLA
SH
.A[4]
FLA
SH
.A[5]
FLA
SH
.A[6]
FLA
SH
.A[7]
FLA
SH
.A[8]
FLA
SH
.A[9]
FLA
SH
.A[10]
FLA
SH
.A[11]
FLA
SH
.A[12]
FLA
SH
.A[13]
FLA
SH
.A[14]
FLA
SH
.A[15]
FLA
SH
.A[16]
FLA
SH
.A[17]
FLA
SH
.A[18]
FLA
SH
.A[19]
FLA
SH
.A[20]
FLA
SH
.A[21]
FLA
SH
.A[22]
FLA
SH
.A[23]
FLA
SH
.A[24]
FLA
SH
.CS
1
FLA
SH
.CS
2F
LAS
H.C
S3
FLA
SH
.OE
FLA
SH
.WE
FLA
SH
.BE
[1]F
LAS
H.B
E[0]
FLA
SH
.AD
VF
LAS
H.W
PF
LAS
H.R
P
FLA
SH
.A[25]
FLA
SH
.CS
2U
MP
U_B
OO
T
FLA
SH
.CS
1U
[*]GP
IO1
nFLA
SH
.AD
V(9)
FLA
SH
.A24
FLA
SH
.CLK
FLA
SH
.A14
R210
22
VD
D_3V
3
FLA
SH
.D0
nFLA
SH
.BE
1(8,9)
FLA
SH
.D12
FLA
SH
.D13
FLA
SH
.D5
FLA
SH
.A10
NOR FLASH
FLA
SH
.A17
FLA
SH
.A7
FLA
SH
.A20
R11
0
VD
D_3V
3R
3110K
FLA
SH
.D5
FLA
SH
.A1
R110
10K
nFLA
SH
.CS
1A(9,10)
FLA
SH
.D14
FLA
SH
.D8
FLA
SH
.A16
FLA
SH
.A1
Q
FLA
SH
.A22
SLOT 1
FLA
SH
.D3
FLA
SH
.A7
R14
0R
150
nFLA
SH
.WE
C68
.01UF
/10V
P
FLA
SH
.A2
FLA
SH
.D10
nFLA
SH
.CS
XA
FLA
SH
.D2
FLA
SH
.A10
R20
0
MP
U_B
OO
T(9)
nFLA
SH
.CS
2B(9)
FLA
SH
.A12
R26
0
nFLA
SH
.OE
FLA
SH
.A9
FLA
SH
.A2
R208
22
R
FLA
SH
.D10
FLA
SH
.A17
R1
10K
R33
0
FLA
SH
.D10
RN
1
RP
AC
K4-10K
12345
678
VD
D_3V
3
FLA
SH
.A18
FLA
SH
.A5
FLA
SH
.A6
C69
.01UF
/10V
NO
TE: CS
1B is only valid for 32M
B.
FLA
SH
.D6
FLA
SH
.A14
FLA
SH
.A18
R205
22R
220
nFLA
SH
.RP
FLA
SH
.D4
nFLA
SH
.WE
FLA
SH
.D11
FLA
SH
.A21
FLA
SH
.A9
R34
0
O
nFLA
SH
.CS
3(9)
FLA
SH
.A[1..25]
(8,9,10)
R38
0
FLA
SH
.D15
R29
10K
FLA
SH
.D3
R24
0
QnF
LAS
H.C
SXB
FLA
SH
.CLK
FLA
SH
.D2
FLA
SH
.A25
FLA
SH
.A4
R204
22
FLA
SH
.A23
FLA
SH
.A11
R212
22
L
R111
10K
FLA
SH
.D9
FLA
SH
.A12
FLA
SH
.D15
FLA
SH
.D15
FLA
SH
.A8
FLA
SH
.A13
R206
22R
250
FLA
SH
.D13
FLA
SH
.A23
R207
22
R203
22
FLA
SH
.D7
C67
.01UF
/10V
VD
D_3V
3
FLA
SH
.A4
N
FLA
SH
.A17
R8
0
FLA
SH
.CLK
(9)
FLA
SH
.D12
FLA
SH
.A19
FLA
SH
.A18
R201
22
C2
.01UF
/10V
nFLA
SH
.AD
V
FLA
SH
.A23
FLA
SH
.A3Chip S
elect
nFLA
SH
.OE
nFLA
SH
.CS
3
FLA
SH
.A4
FLA
SH
.A11
R16
0
R294
10K
nFLA
SH
.WP
(9)
R202
22
VD
D_3V
3
nFLA
SH
.AD
V
FLA
SH
.D7
RN
4
RP
AC
K8-22
116
215
314
413
512
611
710
89
VD
D_3V
3
FLA
SH
.D12
FLA
SH
.A10
FLA
SH
.A24
R214
22R
21522
nFLA
SH
.WE
(8,9,10)
U4A
74LVC
139
231
4567
168
ABG
Y0
Y1
Y2
Y3
VCCGND
R36
0
VD
D_3V
3
nFLA
SH
.CS
2(9,10)
FLA
SH
.A12
FLA
SH
.A20
VD
D_3V
3
<Doc>
A1
OM
AP
5912 Starter K
it
B
210
Monday
, July 26, 2004
G. C
oley
NO
R F
lash Mem
oryTitle :
Size
Docum
ent Num
berR
ev
Date:
Sheet
of
12203 Southw
est Freew
ayS
tafford, Texas 77477
Ca
talo
g OM
AP
Gro
up
Modified by
:
This document contains
information on a product under
developm
ent and is issued forev
aluation purposes only.
Features characteristic data
and other information are
subject to change.
FLA
SH
.A11
0800:0000
FLA
SH
.RD
Y(8,9,10)
FLA
SH
.A15
FLA
SH
.A1
FLA
SH
.A9
R37
0
C1
.01UF
/10V
FLA
SH
.D7
FLA
SH
.A6
RN
5R
PA
CK
8-22
116
215
314
413
512
611
710
89
U1
28FxxxK
3 [J3] (4-32 MB
ytes)
A1
B1
C1
D1
D2
A2
C2
A3
B3
C3
D3
C4
A5
B5
C5
D7
D8
A7
B7
C7
F2
E2
G3
E4
E5
G5
G6
H7
E1
E3
F3
F4
F5
H5
G7
E7
H2
B2
H4
B4
F8
G8
D4
C6
C8
E6
F6
F7
A8
G1
H8
H3
A6
D5
H6
D6
A4
G2
H1
F1
B6
G4
E8
B8
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VS
SQ
[DN
U]
VS
SV
SS
CE
OE
WE
RP
WP
[DN
U]
A20
CLK
[DN
U]
AD
V[D
NU
]W
AIT[D
NU
]
A21
A22
A23[N
C]
VC
CV
CC
VC
CQ
VS
SQ
[VS
S]
VC
CQ
[DN
U]
VP
EN
RF
U[A
0]R
FU
[CE
2]R
FU
[BY
TE]
RF
U
VC
CQ
STS
RF
U[C
E1]
SD
RA
M.D
1
SD
RA
M.D
QS
L
R94
10
nSD
RA
M.W
E
R247
0
C71
.01UF
/10V
SD
RA
M.A
7
nSD
RA
M.D
QM
U
Mobile DDR
U7
A7
A8
A9
B7
B8
A1
C7
C8
B1
D7
D8
A3
E7
C9
G7
G8
G9
H7
H8
H9 J7J8 J9
K7
K8
D1B9
K2
K3 J1 J2 J3
H1
H2
G2
F1
E3
E9
D2
D3
C1
C2
C3
F9
B2
B3
D9
A2
E1
H3
F3
E2
E8
F2
F7
F8
G1
G3
K1K9
VDDQ5D0
VDD2
D1
D2
VSS3
D3
D4
VDDQ3
D5
D6
VSSQ1
D7
VDDQ2
WE
CA
SR
AS
CS
BA
0B
A1
A10/A
P
A0
A1
A2
A3
VDDQ1VSSQ2
A4
A5
A6
A7
A8
A9
A11
CK
VSS1
D8
VDDQ4
D9
D10
VSSQ3
D11
D12
VDD1
D13
D14
VSSQ4 D15
VSSQ5
A12
NC
1
UD
QS
LDQ
S
UD
M
A13
LDM
CK
E
CK
VSS2VDD3
<Doc>
A1
OM
AP
5912 Starter K
it
B
310
Monday
, July 26, 2004
G. C
oley
DD
R S
DR
AM
Title :
Size
Docum
ent Num
berR
ev
Date:
Sheet
of
12203 Southw
est Freew
ayS
tafford, Texas 77477
Cata
log O
MA
P G
roup
Modified by
:
This document contains
information on a product under
developm
ent and is issued forev
aluation purposes only.
Features characteristic data
and other information are
subject to change.
SD
RA
M.A
4
C66
.01uF
SD
RA
M.D
0
C4
.01UF
/10V
C3
.01UF
/10V
nSD
RA
M.C
SS
DR
AM
.D2
SD
RA
M.D
13
VD
D_S
DR
AM
SD
RA
M.B
A0
SD
RA
M.D
6
C70
.01UF
/10V
SD
RA
M.D
3
R249
0
SD
RA
M.D
2
SD
RA
M.A
11
SD
RA
M.A
2
SD
RA
M.D
4
SD
RA
M.D
10
nSD
RA
M.D
DR
.CLK
SD
RA
M.A
12
K4x56163DPE(L/F)C2 =100MHZ..16Mx16...32MB...256Mb...Samsung 60 Ball (6x10)
VD
D_S
DR
AM
SD
RA
M.A
10
SD
RA
M.D
11S
DR
AM
.D8
SD
RA
M.A
3
SD
RA
M.C
LK
R296
22
R233
22
R93
0
K4x28163PEVG100 =100MHZ..8Mx16...16MB...128Mb...Samsung 60 Ball (6x10)
RN
7R
PA
CK
8-22
116
215
314
413
512
611
710
89
SD
RA
M.C
KE
SD
RA
M.A
5
SD
RA
M.D
QS
H
SD
RA
M.D
12
SD
RA
M.D
9
RN
9R
PA
CK
4-22
1 2 3 45678
SD
RA
M.D
12
R245
0S
DR
AM
.D0
RN
11R
PA
CK
4-10K
1234 5
678
SD
RA
M.A
0
SD
RA
M.D
7
RN
10R
PA
CK
8-22
116
215
314
413
512
611
710
89
R246
0
SD
RA
M.D
3
SD
RA
M.D
8
EM
IFF
U3A
OM
AP
5912-ZD
Y
B10
C10
B11B
9A
11B
8B
12C
9B
7A
3B
6B
3A
5A
4B
5B
4
E8
E9
F8
F9
C6
A10
E10
C8
D9
C3
F7
A1
B2
C5
C4
A7
B13
A8
E6
D5
D4
D10
E7
C7
A12
A2
A6
SD
RA
M.D
[15]S
DR
AM
.D[14]
SD
RA
M.D
[13]S
DR
AM
.D[12]
SD
RA
M.D
[11]S
DR
AM
.D[10]
SD
RA
M.D
[9]S
DR
AM
.D[8]
SD
RA
M.D
[7]S
DR
AM
.D[6]
SD
RA
M.D
[5]S
DR
AM
.D[4]
SD
RA
M.D
[3]S
DR
AM
.D[2]
SD
RA
M.D
[1]S
DR
AM
.D[0]
SD
RA
M.A
[12]S
DR
AM
.A[11]
SD
RA
M.A
[10]S
DR
AM
.A[9]
SD
RA
M.A
[8]S
DR
AM
.A[7]
SD
RA
M.A
[6]S
DR
AM
.A[5]
SD
RA
M.A
[4]S
DR
AM
.A[3]
SD
RA
M.A
[2]S
DR
AM
.A[1]
SD
RA
M.A
[0]
SD
RA
M.B
A[0]
SD
RA
M.B
A[1]
SD
RA
M.C
LKS
DR
AM
.CK
ES
DR
AM
.DQ
MU
SD
RA
M.W
E
SD
RA
M.C
AS
SD
RA
M.R
AS
SD
RA
M.A
[13]
SD
RA
M.C
S
SD
RA
M.D
QM
L
SD
RA
M.D
QS
HS
DR
AM
.DQ
SL
SD
RA
M.C
LKX
SD
RA
M.B
A1
SD
RA
M.A
6
nSD
RA
M.C
AS
SD
RA
M.D
9
nSD
RA
M.D
QM
L
SD
RA
M.D
15
SD
RA
M.D
13
SD
RA
M.D
14
SD
RA
M.D
4
SD
RA
M.D
5
SD
RA
M.D
11
SD
RA
M.D
7S
DR
AM
.D5
nSD
RA
M.R
AS
SD
RA
M.D
[0..15]
SD
RA
M.D
14S
DR
AM
.D15
R92
0
SD
RA
M.D
10
VD
D_S
DR
AM
R248
10
SD
RA
M.A
1
SD
RA
M.A
8
RN
8R
PA
CK
8-22
116
215
314
413
512
611
710
89
NOTE: SDRAM.DDR.CLK and SDRAM.CLK routes
must be the same length and routed next
to each other at 4mil spacing..
R43
10K
SD
RA
M.D
1
SD
RA
M.A
9
SD
RA
M.D
6
VD
D_3V
3
VD
D_3V
3
C101
.1UF
/10V, n.m
.
VD
D_3V
3
R55100K
ON
_OF
F(9)
TCK
R_M
AIN
R291
10K
R57
33
R89
10K, 0402
C11
10pf,10v
C100
.01uF
VD
D_S
DR
AM
MP
U_nR
ES
ET
(6)
JP1
CO
N3
123
VD
D_D
LL
TRS
T_MA
INn
L9
FE
RR
ITE B
EA
D M
2301-ND
R301
NO
PO
P
VD
D_3V
3
J2
HE
AD
ER
10X2 135791113151719
2468101214161820
R46
n.m.,0603
VD
D_3V
3
R59
33
R654.7K
C10
10pf,10v
+C
8
10uf/10V
R44
n.m.,0603
VD
D_D
SP
VD
D_3V
3
VD
D_3V
3
VD
D_3V
3
Y2
SS
P-T6
32.768MH
Z
12
3
5
C17
.01uF/10V
Y1
CS
10_12.0000MA
BJ
12
TDO
(9)
+C
80
10uf/10V
C97
.01uF
R58
33
C22
.01uF/10V
C84
.01uF/10V
BC
LK(9)
C16
.01uF/10V
Clock,
Re
set, andJTA
G
U3C
OM
AP
5912-ZD
Y
R2
P2
U11
U10
N12
N8
U17
T15
M10
P13
R13
U16
N11
T14
R14
T17
T11
N14
R9
P10
U3
T7R12
L10
OS
C1_IN
OS
C1_O
UT
OS
C32K
_IN
OS
C32K
_OU
T
RS
T_OU
T
PW
RO
N_R
ES
ET
TDI
TDO
TMS
TCK
TRS
T
EM
U0
EM
U1
RTC
K
CO
NF
BF
AIL/E
XT_FIQ
CLK
32K_IN
MP
U_R
ST
VS
S
RTC
_ON
_OF
F
MC
LKM
CLK
RE
Q
BC
LKR
EQ
BC
LK
VD
D_S
DR
AM
R52
10K
R166
0
MC
LKR
EQ
(9)
TDI_M
AIN
<Doc>
A1
OM
AP
5912 Starter K
it
B
410
Monday
, July 26, 2004
G. C
oley
JTAG
/OS
C/P
ower &
GN
DTitle :
Size
Docum
ent Num
berR
ev
Date:
Sheet
of
12203 Southw
est Freew
ayS
tafford, Texas 77477
Ca
talog
OM
AP
Gro
up
Modified by
:
This document contains
information on a product under
developm
ent and is issued forev
aluation purposes only.
Features characteristic data
and other information are
subject to change.
TCK
_MA
IN
TCK
(9)
R66
33
VD
D_C
OR
E
R165
0
R47
10
U8
SN
74LVT244B 20
2468
18161412
1
10
19 11131517
9753
Vcc
1A1
1A2
1A3
1A4
1Y1
1Y2
1Y3
1Y4
1OE
GN
D
2OE
2A1
2A2
2A3
2A4
2Y1
2Y2
2Y3
2Y4
C5
10pf,10v
R133
10K
VD
D_3V
3
C13
10pf,10v
VD
D_3V
3
R304
20K, n.m
.
VD
D_C
OR
E
VD
D_C
OR
E
TMS
_MA
IN
+C
6
10uf/10V
C23
.01uF/10V
C92
.01uF
C95
.01uF
VD
D_C
OR
E
BC
LKR
EQ
(9)
R168
0
JTAG
_DIS
(9)
TDI
(9)
VD
D_S
DR
AM
nEM
U1
(9)
R60
33
R54100K
Cut pin 6 off.
TDO
_MA
IN
MP
U_nR
ES
ET
(6)
nTRS
T(9)
R67
33
Po
wer and
Ground
U3D
OM
AP
5912-ZD
Y
T6U
2
J15M
13
T13
B1
G1
G7
L3
D11D
8D
6D
7
T10
J9N13
M12
N5
M6
L7 E5
E13
H9
P17
G11
F12
T16M
7T3
R10
J10
H11
K11
K8
K9
K10
K5
G8
C11
H1
C14
F6
H10
L11
E14
G10L9
H8
G9
H7
A9
G12
K4
DV
DD
3D
VD
D2
DV
DD
8D
VD
D9
DV
DD
7
DV
DD
5_0
DV
DD
5_2
VS
S
DV
DD
5_1
DV
DD
4_0D
VD
D4_1
DV
DD
4_2D
VD
D4_3
DV
DD
6
VS
S
VS
S
VS
SV
SS
VS
S
VS
S
VS
SV
SS
VS
S
CV
DD
A
VS
S
VS
S
CV
DD
_2C
VD
D_1
CV
DD
1
DV
DD
RTC
CV
DD
3_0
CV
DD
3_2C
VD
D3_1
VS
SV
SS
VS
S
CV
DD
_0
CV
DD
2_0
CV
DD
_3
LDO
.FILTE
R
DV
DD
1_0
VS
S
VS
S
VS
S
NC
_0
CV
DD
3_3
CV
DD
RTC
VS
SC
VD
D2_1
CV
DD
2_2
CV
DD
DLL
DV
DD
1_1
NC
_1
C12
.01uF/10V
R53
0
TMS
(9)
VD
D_3V
3
VD
D_3V
3
VD
D_3V
3
C19
.01uF/10V
C98
.01uFR
6133
R119
1K
RTC
K(9)
R113
22V
DD
_3V3
R45
n.m.,0603
R644.7K
VD
D_3V
3U
22D
K/S
G8002C
AP
CB
-ND
(12.000MH
Z)
3
21
4O
UT
GN
DE
N
VC
C+
C9
10uf/10V
VD
D_3V
3
JTAG_EMU0
C99
.01uF
R295
47K
VD
D_3V
3
C18
.01uF/10V V
DD
_RTC
J1
EH
DR
_SM
_14P
12
34
56
78
910
1112
1314
12
34
56
78
910
1112
1314
VD
D_3V
3
MC
LK(7,9)
R302
0
C96
.01uF
nRE
SE
T.OU
T(9)
nEM
U0
(9)
C93
.01uF
C21
.01uF/10V
R51
10K
VD
D_S
DR
AM
C15
1uF, 10V
, X5R, 0402
R56100K
C90
.01uF
VD
D_D
SP
BF
AIL
(9)
C20
.01uF/10V
JTAG_EMU1
C14
.01uF/10V
VD
D_3V
3
VD
D_3V
3
C91
.01uF
R62
33
R112
22
+C
7
10uf/10V
R303
0
R50
10K
R167
0
nPW
RO
N_R
ES
ET
(6)
R48
10
CA
M.D
7
UW
IRE
.SD
O(9)
MC
SI1.S
YN
C(9
)
R29
92
2
CA
M.D
5
CA
M.D
0
MC
SI2.C
LK
(9)
UA
RT
2.RTS
(9)
KB
.C5
UA
RT
1.CTS
(9)
GP
IO3
(9)
CA
M.D
[0..7]
(9)
CA
M.V
S(9
)
LCD
.P1
1
CA
M.D
3
MC
BS
P1
.CLK
S(7
,9)
LO
W_P
WR
(6)
I2C.S
CL
(6,7,9)
OM
CB
SP
2.FS
R(8
)
KB
.R4
(9)
LCD
.P1
UA
RT
3.RX
(8,9)
GP
IO14
(9)
KB
.C1
(9)
CA
M.D
6
nCF
LA
SH
.RE
SE
T(8,9)
UW
IRE
.SD
I(9)
KB
.R1
(9)
LCD
.P0
MC
BS
P1
.CLK
X(7,9)
R30
01
K
GP
IO11
(9)MM
C.C
LK(9)
LCD
.PC
LK(9
)
KB
.R0
KB
.C4
(9)
LCD
.P4
LA
N_
INTR
0(1
0)
LCD
.VS
(9)
MP
UIO
3(8,9)
LCD
.P7
MC
SI1.C
LK
(9)
KB
.C3
RN
12
RP
AC
K8
-22
116
215
314
413
512
611
710
89
MC
BS
P1
.DX
(7,9)
Peripherals
U3B
OM
AP
591
2-ZD
Y
M16
M1
7L1
4L1
5
P1
6M
11
T2
U1
F14C17B17E15D16F17F15E17E16D17F13
J17
J16
J14
H13
J11
H17
H15
H16
J12
J13
G16
H12
P4
N1
5L1
2
M1
4N
16
K1
2
K1
3
L13
J5
A1
7B
16
C16
D14
E1
2C
15A
16
D13
C13
F1
1A
15
B1
4A
13
E1
1D
12C
12
D15
A1
4F
10
B1
5
L17
K1
4K
16
P7
U7
R6
P9
N7
M8
R8
U9
T9
N1
7
L16
F1
6G
13G
15G
14G
17
U5
U6
N6
R5
T5
L8
P12P11U15N10
U8P8T8R7
T4
P6
R4
U4
R1
1M
9U
13
T12
K1
5K
17
P5
R16R17R15P14P15
N9U12
U14 GPIO2
GP
IO4
GP
IO6
GP
IO7
I2C.S
CL
I2C.S
DA
US
B.D
PU
SB
.DM
KB.C[0]KB.C[1]KB.C[2]KB.C[3]KB.C[4]KB.C[5]KB.R[0]KB.R[1]KB.R[2]KB.R[3]KB.R[4]
CA
M.D
[0]C
AM
.D[1]
CA
M.D
[2]C
AM
.D[3]
CA
M.D
[4]C
AM
.D[5]
CA
M.D
[6]C
AM
.D[7]
CA
M.H
SC
AM
.VS
CA
M.L
CL
KC
AM
.EX
CL
K
US
B.P
UE
N
MP
UIO
1M
PU
IO2
MP
UIO
4M
PU
IO5
CA
M.R
ST
Z
GP
IO1
1
GP
IO3
GP
IO6
2
LC
D.P
[0]L
CD
.P[1]
LC
D.P
[2]L
CD
.P[3]
LC
D.P
[4]L
CD
.P[5]
LC
D.P
[6]L
CD
.P[7]
LC
D.P
[8]L
CD
.P[9]
LC
D.P
[10]
LC
D.P
[11]
LC
D.P
[12]
LC
D.P
[13]
LC
D.P
[14]
LC
D.P
[15]
LC
D.H
SL
CD
.PC
LK
LC
D.A
CLC
D.V
S
GP
IO1
3G
PIO
14
GP
IO1
5
GP
IO8
GP
IO9
MP
UIO
3
MM
C.D
AT
3M
MC
.CM
D/S
PI.D
OM
MC
.CL
KM
MC
.DA
T0/S
PI.D
IM
MC
.DA
T1
MM
C.D
AT
2
GP
IO0
GP
IO1
2
MC
BS
P1
.CLK
XM
CB
SP
1.CL
KS
MC
BS
P1
.FS
XM
CB
SP
1.DX
MC
BS
P1.D
R
MC
BS
P2
.CLK
XM
CB
SP
2.C
LKR
MC
BS
P2
.FS
XM
CB
SP
2.F
SR
MC
BS
P2.D
XM
CB
SP
2.DR
MCSI1.DINMCSI1.DOUTMCSI1.CLKMCSI1.SYNC
MCSI2.SYNCMCSI2.CLKMCSI2.DOUTMCSI2.DIN
[Z]U
AR
T2.R
TSU
AR
T2
.CTS
[Z]U
AR
T2.T
XU
AR
T2
.RX
[Z]U
AR
T1.R
TSU
AR
T1
.CTS
UA
RT
1.R
X[Z
]UA
RT1
.TX
UA
RT
3.R
X[Z
]UA
RT3
.TX
UA
RT
2.B
CLK
[Z]UWIRE.CS3[Z]UWIRE.CS0
UWIRE.SDOUWIRE.SDI
UWIRE.SCLK
RTC_WAKE_INTCLK32K_OUT
[Z]MCBSP3.CLKX
GP
IO2
(9)
R25
61
0K
MC
SI2.S
YN
C(9
)
MC
BS
P1
.DR
(7,9
)
LCD
.P8
US
B_D
P(9)
CA
M.E
XC
LK
(9)V
DD
_3
V3
LCD
.P1
5
KB
.R2
RN
13
RP
AC
K8
-221
162
153
144
135
126
117
108
9
VD
D_3
V3
GP
IO7
(9)
UA
RT
2.BC
LK(9)
CA
M.H
S(9
)
LCD
.P6
KB
.C0
GP
IO62
(9)
I2C.S
DA
(6,7,9)
OM
CB
SP
2.FS
X(8
)
UA
RT
1.TX(8,9)
KB
.R3
(9)
LCD
.P1
2
CA
M.D
1
LCD
.P1
0
GP
IO13
(9)
CA
M.D
2
nC
FL
AS
H.IR
EQ
(8,9)
KB
.C0
(9)K
B.C
1
KB
.R0
(9)
LCD
.P1
3
LCD
.P3
OM
CB
SP
2.CL
KX
(8)
RN
15
RP
AC
K4
-22
12345 6 7 8
GP
IO9
(9)
LCD
.HS
(9)
nC
FL
AS
H.C
D2
(8,9)
MC
SI1.D
OU
T(9)
KB
.C3
(9)
KB
.R3
GP
IO6
(9)
MC
BS
P1
.FS
X(7,9)
WA
KE
UP
_IN
T(9
)
UA
RT
2.CTS
(9)
MC
SI2.D
IN(9)
UA
RT
2.RX
(9)
LCD
.P5
MC
BS
P3
.CLK
X(9)
CA
M.D
4
LCD
.P9
KB
.C2
UW
IRE
.CS
3(9)
MC
SI1.D
IN(9)
LCD
.P2
US
B_D
M(9)
<Doc
>A
1
OM
AP
591
2 S
tarter K
it
B
51
0M
ond
ay, Ju
ly 2
6, 20
04
G. C
oley
Pe
riphe
ral C
onn
ectio
ns
Title
:
Size
Do
cum
ent N
umb
erR
ev
Date:
Sh
eet
of
1220
3 S
outhw
es
t Fre
ewa
yS
taffo
rd, Te
xas 7
7477
Cata
log O
MA
P G
roup
Mo
dified b
y:
This do
cum
ent c
ontain
sinfo
rmation
on a p
rodu
ct und
er
dev
elop
men
t and is
issu
ed fo
rev
alua
tion p
urpos
es o
nly.
Fea
tures
cha
racte
ristic
data
and oth
er inform
atio
n aresu
bjec
t to c
hang
e.
UA
RT
1.RTS
(9)
GP
IO4
(9)
CA
M.R
ST
(9)
CA
M.L
CL
K(9
)
OM
CB
SP
2.CL
KR
(8)
US
B_P
UE
N(9)
KB
.R4
UA
RT
2.TX(9)
UA
RT
3.TX(8,9)
MP
UIO
2(9) P
WR
_IN
T(6,9)
RN
14
RP
AC
K4
-221 2 3 4
5678G
PIO
15(9)
R5
1K
MP
UIO
4(6,9)
KB
.C2
(9)
UA
RT
1.RX
(8,9)
KB
.R2
(9)
UW
IRE
.CS
0(9)
KB
.C4
GP
IO12
(9)
OM
CB
SP
2.DR
(8)
nCF
LA
SH
.IOIS
16(8,9)
KB
.C5
(9)
OM
CB
SP
2.DX
(8)
GP
IO8
(9)
JP
3
CO
N3
123
UW
IRE
.SC
LK
(9)
nC
FL
AS
H.C
D1
(8,9)
LCD
.AC
(9)
MC
SI2.D
OU
T(9)
LCD
.P1
4
R2
55
10K
KB
.R1
LC
D.P
[0..15
](9
)
CL
K3
2K_
OU
T(9
)
TP11
1
I2C.S
CL
(5,7,9)I2C
.SD
A(5,7,9)
R861K
Place close to th
e OM
AP
Processo
r.
VD
D_3
V3
R91
1M,1%,0603
DC
R78
n.m..0603
P7
DC
8
SH
6
.01, 0603
VD
D_3V
3
+
C76
22uf/10V
R83
93.1K 1%
C25
1uF
, 10V, X5R
, 0402
nP
G
VB
AT
C77
1uF, 10
V, X5R
, 0402
R84150,0603
C28
22uF,10V
1.5V
VD
D_D
LL
VD
D_3V
3
Z1
1
C31
1uF, 10V
, X5R, 0402
VD
D_S
DR
AM
TP19
1
R69.01,0805
VD
D_D
SP
SH
1.01, 0603
D9
LED
, GR
N
DC 5V In,
regulated 4A
<Doc>
A1
OM
AP
5912 S
tarter Kit
B
610
Monday
, July 26, 2004
G. C
ole
y
Pow
er M
anagem
entTitle :
Size
Docum
ent Num
berR
ev
Date:
Shee
tof
12203 S
outhw
est F
reeway
Stafford, Te
xas 77477
Catalog O
MA
P G
roup
Modified by
:
This docum
ent con
tainsinform
ation on a product u
nderde
velopm
ent and is issued for
evaluation purpose
s only.
Features characteristic data
and other inform
ation aresu
bject to
change.
R71
n.m
.,0805
TP31
TP81
TP41
R72
270K,1%
,0603
VD
D_C
OR
E
250-500K
D1
SMCJ6.0A
U5
TPS
71501DC
K43
51
2
Vin
NC
OU
T
FB
G
PW
R_IN
T(5,9)
TP12
1
Delete D9 use PG.
D2
LED
, GR
N
nPW
RO
N_R
ES
ET
(4)
DC
_IN
F1
2.5A_Q
uickBlow1
2
Vref .5V
TP171
+C
30
2.2uF/10V
R79
10K,0603
PTH for standoff and 4-40 Screw
S1
SP
NO
_B3S
AA
ABB
B
SH
7.01, 0603
R871K
TP71
JP2
HD
R3, n.m
.123
SH
4
.01, 0603TP
10
1
R8115K
C75
.47uF/10V
R82
243K 1%
R75
10K
Place close to the OMAP5912.
TP201
VD
D_3V
3
+C
27
10uf/10V
Z3
1
US
B_P
WR
_EN
(9)
C291
uF, 10V
, X5R, 0402
Place close to
the OMAP5912.
VD
D_C
OR
E
BA
TT_TE
MP
Po
wer M
anag
emen
t
TP61
VD
D_3V
3_MA
IN
+C
33
4.7uf/10V
R114
10, 0603
Z4
1
RE
SE
T_IN(9)
VD
D_R
TC
R95
10, 0603
TP51
Re
se
t
DC
_IN_F
US
ED
LOW
_PW
R(5)
U9
TPS
71501D
CK
43
51
2
Vin
NC
OU
T
FB
G
VD
D_3V
A
TP11
VD
D_3
V3
SH
2.01, 0603
R73
1M,1
%,0603
R297
NO
PO
P
CHARGER SECTION
SWITCHER
U10
TPS
65010_1
123
4 56 7 8910 11
12
13
14
151618 17 1920
21
2223 242526
27
28
29
30
31
32
33
34
35
36
37
38
39
40
43
42 41
4445
46
47
48
DE
FC
OR
E
LED
2
VIB
L2
VIN
CO
RE
VC
CV
INM
AIN
_A
VIN
MA
IN_
B
L1_A
L1_B
PG
DE
FA
MIN
VM
AIN
PS
_SE
Q
PG
ND
1_A
PG
ND
1_B
GP
IO3
GP
IO4
VIN
2V
LDO
2
AGND1
VIN
1
VF
B_LD
O1
VLD
O1
GP
IO2
GP
IO1
NC
IFL
SB
SD
AT
SC
LK
HO
T_RE
SE
T
MP
U_R
ES
ET
RE
SP
WR
ON
PW
RF
AIL
INT
LOW
_PO
WE
R
ISE
T
TS
BA
TT_CO
VE
R
AC
US
BV
BA
T_A
VB
AT_
B
AGND2AGND3
PG
ND
2
PB
_ON
OF
F
VC
OR
E
Center positiv
e.C
24
.47uF
/10V
R76
10K
R88
10K
+C
32
2.2uF/10V
Z2
1
R8510K
TP91
DS
P P
ow
er C
on
trol
R74
1.6K, 0603
R80
10K
R68
0
R90
243K,1%,0603
R77
0,0603
R4
0
MAX 3.0V
SH
5.01, 0603
R70
330,0603
R3
NO
PO
P
SH
3
.01, 0603
L26.8u
H
C74
.47uF/10V
ESD Ring
LAN
_RE
SE
T(10)
+C
26
220uF
TP2
11
P2
4 H
EA
DE
R, n.m
.1234
MP
U_nR
ES
ET
(4)
L110uH
TP18
1
Pla
ce close to the O
MA
PP
rocessor.
D3
LED
, GR
N
DC
TP21
U1
1FD
C6331L
432
6 5
1
VIN
VO
UT
VO
UT
R1/C
1
ON
/OF
F
R2
MC
BS
P1
.FS
X(5
,9)
C5
4
220p
F,10
V
R14
42
2
VD
D_3
VA
C6
1.1
UF
/10V
MC
BS
P1
.CLK
S(5
,9)
C55
220p
F,1
0V
C5
6
.1uF
/10VL4
FE
RR
ITE B
EA
D M
230
1-ND
L5
FE
RR
ITE
BE
AD
M2
301-N
D
R29
82
2
+
C5
110
0UF
,6.3V
MC
BS
P1.D
R(5,9)
MC
BS
P1
.CLK
X(5
,9)
MC
LK(4
,9)
<D
oc>
A1
OM
AP
591
2 Starte
r Kit
B
710
Mon
day, J
uly 2
6, 2004
T. Tran
Aud
io CO
DE
CTitle :
Size
Doc
umen
t Num
ber
Rev
Da
te:
Sh
eet
of
122
03 S
outh
we
st Freew
ay
Staffo
rd, Tex
as 77477
Ca
talog O
MA
P G
roup
Mo
dified b
y:
This
docu
ment c
ontain
sin
forma
tion on a produ
ct unde
rd
eve
lopme
nt and is is
sued
fore
valu
ation purpo
ses o
nly.
Fe
atures ch
aracteristic
data
and
othe
r information are
sub
ject to chang
e.
C62
.1U
F/10V
TP1
4
1
VD
D_3
VA
R1
4333
0T
P15
1
R1
4133
0
MIC_IN
U1
7TL
V32
0AIC
23P
W1
2
13
1920181745325 26 21
22
127
28
910
1115
16
814
2
7 6 2324
LOU
T
RO
UT
LLIN
EIN
RLIN
EIN
MIC
INM
ICB
IAS
DIN
LR
CIN
BC
LK
XTL
_MC
LK
XTO
CS
#
MO
DE
BV
DD
DV
DD
DGND
LH
PO
UT
RH
PO
UT
HPGNDAGND V
MID
HP
VD
DA
VD
D
CLK
OU
T
LR
CO
UT
DO
UT
SD
INS
CLK
C57
.1UF
/10V
R149
n.m.,0
603
R49
0,08
05C
64
.1UF
/10V
, n.m
.
I2C.S
DA
(5,6,9)
R13
6
5.6
K
R1
395.6K
C5
2
220p
F,10
V
C6
3
.1UF
/10V
R1
3720
K
L7
FE
RR
ITE B
EA
D M
230
1-ND
I2C.S
CL
(5,6,9)
TP1
3
1
C53
1uF
,10V
,A
P6
Ste
reo In
3421
+C
6010
uf/10V
LINE_IN
+C
58
10uf/10
V
U21
DK
/SG
8002
CA
PC
B-N
D(12
.000M
HZ
)3
21
4O
UT
GN
DE
N
VC
C
L8
FE
RR
ITE
BE
AD
M23
01-N
D
MC
BS
P1
.DX
(5,9
)
C4
91
uF,10V
,A
HEADPHONE OUT
VD
D_
3VA
R1
50
20K
, n.m.
R1
4520
KR
146
22
C59
.1UF
/10V
PW
R14
7
22,0603
L6
FE
RR
ITE
BE
AD
M23
01-N
D
C48
220p
F,1
0V
R1
34
5.6K
L3F
ER
RITE
BE
AD
M2
301-N
D
Joining analog and digital
grounds by the CODEC
P5
Stereo
In
3 4 2 1
VD
D_
3V3
R1
421K
R13
82
0K
R1
404
7K
R1
4833
, n.m.
TP
161
R1
355.6K
+
C50
100U
F,6.3V
P1
Ste
reo In
3421
PIN 2 TO
3???
VL
YN
Q.R
X1(9
)
VD
D_
3V3
UA
RT3
.TX(5,9)
FLA
SH
.D1
2F
LAS
H.A
13
CF
LAS
H_
EN
(10)
FLA
SH
.A5
MC
BS
P2.D
R(9)
U15
SN
74C
BTLV
3257
235611101413151
47912
168
1A1B2A2B3A3B4A4BGA
/B
1Y2Y3Y4Y
VCCGND
Co
mp
act Flash
R10510K
C73
.01uF
VL
YN
Q.TX1
(9)
R10910K
R159
20K
R120
0,0603
R10610K
U16
SN
74C
BTLV
3257
235611101413151
47912
168
1A1B2A2B3A3B4A4BGA
/B
1Y2Y3Y4Y
VCCGND
OM
CB
SP
2.C
LK
X(5
)
nCF
LAS
H.IO
IS16
(5,9)
FLA
SH
.D7
nCF
LAS
H.C
D1
(5,9)
R102
10K
FLA
SH
.D9
R11
70,0603
C3
8
.1UF
/10V
RS
232_R
X1
MC
BS
P2.D
X(9)
FLA
SH
.A14
FLA
SH
.D1
5
FLA
SH
.A2
FLA
SH
.A7
OM
CB
SP
2.C
LK
R(5
)
RS
232_TX
1
MC
BS
P2.C
LK
R(9)
R10810K
C83
.1UF
/10V
FLA
SH
.D6 V
DD
_3V
3
FLA
SH
.A[1
..25]
(2,9,10)
FLA
SH
.D2
MC
BS
P2.F
SX
(9)
<Doc>
A1
OM
AP
5912 S
tarter Kit
B
81
0M
onday
, July 2
6, 2004
G. C
ole
y
Com
pact Flash
, RS
232, V
lynq
Title :
Size
Do
cument N
umbe
rR
ev
Date:
She
etof
12203 S
outh
we
st Freew
ayS
tafford, Texas 77
477
Catalog O
MA
P G
roup
Modified by
:
This docum
ent contains
inform
ation o
n a product un
derdev
elopm
ent a
nd is iss
ued for
evaluation p
urposes
only
.F
eatures cha
racteristic d
ataand oth
er informatio
n are
subject to chan
ge.
C39
.1UF
/10V
R1
000
0
+C
44
10uf/10V
R2921KR2931K
R10410K
nCF
LAS
H.C
D2
(5,9)
OM
CB
SP
2.F
SX
(5)
VD
D_3
V3
MP
UIO
3(5,9)
FLA
SH
.D0
FLA
SH
.D1
4
GP
IO62
(5,9)
R15
310
MC
BS
P2.C
LK
X(9)
FLA
SH
.D3
OM
CB
SP
2.DX
(5)
R1
5110
C85
.01uF
C37
.1U
F/10V
FLA
SH
.A12
FLA
SH
.D[0..1
5](2
,9,10)
R11
8n.m
.,0603
R156
10
R1
54100
K
VD
D_
3V3
MC
BS
P2.F
SR
(9)
C3
6
.1UF
/10V
R157
10
R1
07
47K
PTC
1P
TC
, 1206
U6
SN
74A
HC
1G0
4DC
KR
24
53
VD
D_3V
3
FLA
SH
.D4
nCF
LA
SH
.IRE
Q(5,9)
C40
.1U
F/10V
VL
YN
Q.R
X0(9
)
FLA
SH
.D1
UA
RT
1.RX
(5,9)
UA
RT_D
IS(9
)
FLA
SH
.A9
VD
D_3
V3
nCF
LAS
H.R
ES
ET
(5,9)
R15
210
C41
.1UF
/10V
VD
D_3V
3
FLA
SH
.D1
0F
LAS
H.A
10
R9
99
0
R11
50,0603
R15
520K
R158
10
P8
DS
UB
9-Male
594837261
1011
SH
806
03-R-S
hort
OM
CB
SP
2.F
SR
(5)
FLA
SH
.A11
C42
.1U
F/10V
nF
LA
SH
.WE
(2,9,10)
FLA
SH
.A3
nFLA
SH
.BE
1(2,9)
VL
YN
Q.TX0
(9)
UA
RT
3.RX
(5,9)
U20B
74LV
C2
G125
53
7
+C
65
10uf/1
0V
FLA
SH
.D8
VL
YN
Q.C
LK(9)
UA
RT1
.TX(5,9)
FLA
SH
.A8
P14
Com
pact F
lash C
onnec
tor_0
1
23456
7 89 10 11 12 1314 15 16 17 18 19 202
12
22
3
242
52
6
27
28
29
30
31
32
33
34 353637 3839
40
41 4243 44
45
46
47
48
49
50G
ND
D0
3D
04
D0
5D
06
D0
7
CE
1
A10
OE
A09
A08
A07
VC
C
A06
A05
A04
A03
A02
A01
A00
D0
0D
01
D0
2
WP
CD
2C
D1
D1
1D
12
D1
3D
14
D1
5
CE
2
VS
1
IOR
DIO
WR
WE
RD
Y/B
SY
VC
C
CS
EL
VS
2R
ES
ET
WA
IT
INP
AC
K#
RE
G
BV
D2
BV
D1
D0
8D
09
D1
0
GN
D
nF
LA
SH
.OE
(2,9,10)
VD
D_3
V3
FLA
SH
.D1
1
FLA
SH
.A4
U14
MA
X3221
1 2456
8
14 15
16
3 7
9
13
10
12 11
EN
C1+
C1-
C2+
C2-
RIN
GND VCC
FO
RC
EO
FF V+ V-
RO
UT
DO
UT
INV
AL
ID
FO
RC
EO
N
DIN
Deb
ug
RS
-232 Tran
sceiver
nFLA
SH
.BE
0(2,9
)
OM
CB
SP
2.D
R(5
)
FLA
SH
.A1
FLA
SH
.D1
3V
DD
_3V3
FLA
SH
.RD
Y(2
,9,10)
FLA
SH
.A6
FLA
SH
.D5
R11
6n.m
.,0603
U20A
74LV
C2
G125
26
1 84
TMS
(4)
UW
IRE
.SC
LK(5)
nCF
LAS
H.IR
EQ
(5,8)
FLA
SH
.D1
GP
IO13
(5)
nFLA
SH
.OE
(2,8,10)
FLA
SH
.A15
FLA
SH
.A8
LCD
.AC
(5)
FLA
SH
.A[1..25]
(2,8,10)
FLA
SH
.D2
R100
15K
UA
RT_D
IS(8)
VD
D_3V
3
LCD
.P12
CONN A
P10
FX2-80P
-1.27SV
12
34
56
78
910
7372
7170
6968
6766
6564
6362
6160
5958
5756
5554
5352
5150
4948
4746
4544
4342
4140
3938
3736
3534
3332
3130
2928
2726
2524
2322
2120
1918
1716
1514
1312
11
7475
7677
7879
80
GN
D1
GN
D5
GN
D2
GN
D6
3.3V1
3.3V3
3.3V2
3.3V4
NC
1N
C3
FLA
SH
.A1
FLA
SH
.A2
FLA
SH
.A3
FLA
SH
.A4
FLA
SH
.A5
FLA
SH
.A6
FLA
SH
.A7
FLA
SH
.A8
FLA
SH
.A9
FLA
SH
.A10
FLA
SH
.A11
FLA
SH
.A12
FLA
SH
.A13
FLA
SH
.A14
FLA
SH
.A15
FLA
SH
.A16
FLA
SH
.A17
FLA
SH
.A18
FLA
SH
.A19
FLA
SH
.A20
FLA
SH
.A21
FLA
SH
.A22
FLA
SH
.A23
FLA
SH
.A24
FLA
SH
.A25
GP
IO1
FLA
SH
.D0
FLA
SH
.D1
FLA
SH
.D2
FLA
SH
.D3
FLA
SH
.D4
FLA
SH
.D5
FLA
SH
.D6
FLA
SH
.D7
FLA
SH
.D8
FLA
SH
.D9
FLA
SH
.D10
FLA
SH
.D11
FLA
SH
.D12
FLA
SH
.D13
FLA
SH
.D14
FLA
SH
.D15
FLA
SH
.CS
1F
LAS
H.C
S1B
FLA
SH
.CS
2F
LAS
H.C
S2B
FLA
SH
.CS
3F
LAS
H.O
EF
LAS
H.R
PF
LAS
H.W
PF
LAS
H.W
EF
LAS
H.B
E1
FLA
SH
.BE
0F
LAS
H.C
LKF
LAS
H.R
DY
FLA
SH
.AD
VM
MC
.CLK
MM
C.D
AT1
MM
C.D
AT0
MM
C.D
AT3
MM
C.D
AT2
MM
C.C
MD
MP
U_B
OO
T
nEX_C
S3
nEX_C
S4
FLA
SH
.DIS
GN
D3
GN
D7
GN
D4
GN
D8
<Doc>
A1
OM
AP
5912 Starter K
it
B
910
Monday
, July 26, 2004
G. C
oley
Expansion C
onnectors, US
B H
ostTitle :
Size
Docum
ent Num
berR
ev
Date:
Sheet
of
12203 Southw
est Freew
ayS
tafford, Texas 77477
Ca
talog O
MA
P G
rou
p
Modified by
:
This document contains
information on a product under
developm
ent and is issued for
evaluation purposes on
ly.
Features characteristic data
and other information a
resubject to change.
ON
_OF
F(4)
LCD
.P4
VD
D_3V
3
FLA
SH
.RD
Y(2,8,10)
CA
M.D
5
FLA
SH
.A16
DC
CA
M.H
S(5)
CA
M.D
1
FLA
SH
.A9
VD
D_3V
3
MC
SI2.C
LK(5)
UA
RT2.R
X(5)
VLY
NQ
.TX1(8)
UW
IRE
.CS
3(5)
MC
BS
P2.C
LKX
(8)
GP
IO12
(5)
KB
.C2
(5)
nFLA
SH
.CS
2(2,10)
CO
NN
B
P11
FX2-80P
-1.27SV
12
34
56
78
910
1112
55
14
57
1617
1819
2021
2223
242527
26
2928
33
3031
32
3534
3736
3938
4140
6970
7172
7374
7576
7778
7980
4345474951535961636567
4244464850526062646668 545658
1315
GN
DG
ND
GN
DG
ND
DC
DC
DC
DC
VC
C_3V
3V
CC
_3V3
VC
C_3V
3V
CC
_3V3
US
B_D
M
NC
US
B_D
P
MC
BS
P1.F
SX
MC
SI1.S
YN
CM
CS
I1.CLK
MC
SI1.D
INM
CS
I1.DO
UT
MC
SI2.S
YN
CM
CS
I2.CLK
MC
SI2.D
INM
CS
I2.DO
UT
BC
LKB
CLK
RE
QM
CLK
RE
Q
MC
LKC
LK32K
_OU
T
NC
MC
BS
P1.D
XM
CB
SP
1.CLK
SM
CB
SP
1.DR
MC
BS
P1.C
LKX
NC
MC
BS
P2.F
SR
MC
BS
P2.D
R
MC
BS
P2.D
XM
CB
SP
2.CLK
X
MC
BS
P2.F
SX
MC
BS
P2.C
LKR
NTR
ST
TMS
TDI
NE
MU
0N
EM
U1
TCK
RTC
KTD
OG
ND
GN
DG
ND
GN
D
UA
RT3.R
XU
AR
T1.TXU
AR
T1.RX
UA
RT2.TX
UA
RT2.R
TSU
AR
T1.DIS
RE
SE
T_ING
PIO
4M
CB
SP
3.CLK
XM
PU
IO4
JTAG
_DIS
UA
RT3.TX
UA
RT1.R
TSU
AR
T1.CTS
UA
RT2.C
TSU
AR
T2.RX
UA
RT2.B
CLK
nRE
SE
T.OU
TG
PIO
8G
PIO
11M
PU
IO3
GP
IO62
BF
AIL
ON
_OF
FU
SB
_PU
EN
NC
RTC
_WA
KE
_INT
MC
LK(4,7) B
CLK
RE
Q(4)
LCD
.P5
FLA
SH
.D0
nEM
U0
(4)
US
B_P
WR
_EN
(6)
FLA
SH
.A6
GP
IO15
(5)
nCF
LAS
H.C
D1
(5,8)
FLA
SH
.A17
KB
.C1
(5) MC
BS
P2.F
SR
(8)
UA
RT1.R
X(5,8)
UA
RT1.C
TS(5,8)
nFLA
SH
.WP
(2)
FLA
SH
.D3
GP
IO62
(5)
LCD
.P8
FLA
SH
.A25
VD
D_3V
3
MC
BS
P2.C
LKR
(8)
GP
IO7
(5)
nFLA
SH
.BE
0(2,8)
VD
D_3V
3
MC
SI1.D
IN(5)
CLK
32K_O
UT
(5)
UW
IRE
.CS
0(5)
FLA
SH
.A3
R97
27
CA
M.D
3U
18
TPS
2045
1
2 3 54678
GND
IN1
IN2
OC
EN
OU
T1O
UT2
OU
T3
+C
81
220uF,TA
NT
GP
IO14
(5)
US
B_P
UE
N(5)
LCD
.P9
CA
M.D
4
LCD
.P[0..15]
(5)
FLA
SH
.A[1..25]
(2,8,10)
TCK
(4)
UA
RT2.R
TS(5)
MC
BS
P1.D
X(5,7)
GP
IO11
(5)
GP
IO2
(5)
LCD
.PC
LK(5)
LCD
.P10
MP
UIO
2(5)
LCD
.P0
KB
.C3
(5)
VLY
NQ
.TX0(8)
FLA
SH
.A13
LCD
.P11
FLA
SH
.D4
FLA
SH
.D10
VD
D_3V
3
FLA
SH
.D13
DC
MC
BS
P2.D
X(8)
RE
SE
T_IN(6)
MC
BS
P3.C
LKX
(5)
FLA
SH
.A14
R169
1.5K
MC
SI2.D
IN(5)
KB
.C5
(5)
US
B_D
P(5)
nEX_C
S3
(5)
FLA
SH
.D15
VLY
NQ
.RX1
(8)nF
LAS
H.B
E1
(2,8)
FLA
SH
.A7
FLA
SH
.DIS
(2)
UW
IRE
.SD
O(5)
I2C.S
DA
(5,6,7)
FLA
SH
.D[0..15]
(2,8,10)
TDO
(4)
UA
RT2.B
CLK
(5)
KB
.R4
(5)
LCD
.P13
CA
M.E
XCLK
(5)
UA
RT1.R
TS(5)
LCD
.P2
MP
U_B
OO
T(2)
FLA
SH
.A18
GP
IO4
(5)
CA
M.R
ST
(5)
MC
BS
P1.D
R(5,7)
nRE
SE
T.OU
T(4)
FLA
SH
.A5
MC
SI2.S
YN
C(5)
P4
US
B-A
1234 56
+5V-D
ATA
+DA
TAG
ND
SS
LCD
.P6
FLA
SH
.A19
US
B_D
M(5)
FLA
SH
.A2
KB
.R1
(5)
MC
LKR
EQ
(4)
FLA
SH
.A12
TDI
(4)
MC
BS
P2.F
SX
(8)
CA
M.V
S(5)
nTRS
T(4)
nFLA
SH
.CS
1A(2,10)
LCD
.VS
(5)
LCD
.P[0..15]
(5)
BF
AIL
(4)
nFLA
SH
.WE
(2,8,10)
FLA
SH
.D11
KB
.R2
(5)
DC
nCF
LAS
H.R
ES
ET
(5,8)
FLA
SH
.D9
Conn D
P13F
X2-80P-1.27S
V
135791113
24681012143637
3839
4041
4243
4445
4647
4849
5051
5253
5455
5657
5859
6061
6263
6465
6667
6869
7071
72
7778
7980
1516
1718
1920
2122
2324
2526
2728
2930
3132
3334
357374
7576
GN
DG
ND
DC
DC
VC
C_3V
3V
CC
_3V3
NC
GN
DG
ND
DC
DC
VC
C_3V
3V
CC
_3V3
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
GN
DG
ND
GN
DG
ND
GN
DV
LYN
Q.TX1
GN
DV
LYN
Q.TX0
GN
DV
LYN
Q.C
LKG
ND
VLY
NQ
.RX1
GN
DV
LYN
Q.R
X0N
CN
CN
CN
CN
CN
CN
CN
CN
CN
CN
C
NC
NC
NC
NC
DC
LCD
.HS
(5)
FLA
SH
.CLK
(2)
nCF
LAS
H.C
D2
(5,8)
LCD
.P14
LCD
.P15
UA
RT2.C
TS(5)
UA
RT2.TX
(5)
R101
10K
R98
27
MC
SI1.D
OU
T(5)
nFLA
SH
.CS
1B(2)
FLA
SH
.D14
FLA
SH
.D12
FLA
SH
.D5
VD
D_3V
3
MC
SI1.S
YN
C(5)
FLA
SH
.A20
KB
.R0
(5)
PW
R_
INT
(5,6)
LCD
.P7
CA
M.D
6
JTAG
_DIS
(4)
BC
LK(4)
RTC
K(4)
FLA
SH
.A23
UA
RT3.TX
(5,8)
CA
M.LC
LK(5)
R99
15K
GP
IO1
(2)
CA
M.D
[0..7](5)
VD
D_3V
3
CA
M.D
7
FLA
SH
.A10
MP
UIO
3(5,8)
GP
IO9
(5)
DC
KB
.R3
(5)
UA
RT3.R
X(5,8)
nCF
LAS
H.IO
IS16
(5,8)
US
B_P
UE
N(5)
nEX_C
S4
(5)
VLY
NQ
.CLK
(8)M
CS
I1.CLK
(5)
FLA
SH
.A11
GP
IO3
(5)
US
B_D
P(5)
FLA
SH
.D7
FLA
SH
.A21
MC
BS
P1.C
LKS
(5,7)
R103
10K
Conn C
P12F
X2-80P-1.27S
V
135791113
246810121415
1617
1819
2021
2223
2425
74
2728
2930
3132
3334
35
26
373638
394142
4344
4546
4748
4950
5152
5354
5556
5758
5960
6162
6364
6566
6768
6970
71
7673
72
7778
7980
75
40
GN
DG
ND
DC
DC
VC
C_3V
3V
CC
_3V3
NC
GN
DG
ND
DC
DC
VC
C_3V
3V
CC
_3V3
NC
GP
IO7
GP
IO3
GP
IO2
GP
IO6
GP
IO9
GP
IO13
GP
IO12
GP
IO15
GP
IO14
MP
UIO
2M
PU
IO1
UW
IRE
.CS
3
CA
M.D
0C
AM
.D1
CA
M.D
2C
AM
.D3
CA
M.D
4C
AM
.D5
CA
M.D
6C
AM
.D7
CA
M.LC
LK
CA
M.E
XCLK
CA
M.V
SC
AM
.HS
CA
M.R
STZ
I2C.S
DA
LCD
.P0
LCD
.P1
LCD
.P2
LCD
.P3
LCD
.P4
LCD
.P5
LCD
.P6
LCD
.P7
LCD
.P8
LCD
.P9
LCD
.P10
LCD
.P11
LCD
.P12
LCD
.P13
LCD
.P14
LCD
.P15
LCD
.PC
LKLC
D.A
CLC
D.V
SLC
D.H
SK
B.C
0K
B.C
1K
B.C
2K
B.C
3K
B.C
4K
B.C
5K
B.R
0K
B.R
1K
B.R
2K
B.R
3K
B.R
4
UW
IRE
.SC
LKU
WIR
E.C
S0
UW
IRE
.SD
I
GN
DG
ND
GN
DG
ND
UW
IRE
.SD
O
I2C.S
CL
GP
IO8
(5)
WA
KE
UP
_INT
(5)
nFLA
SH
.RP
(2)
MP
UIO
4(5,7)
LCD
.P1
FLA
SH
.D6
DC
US
B_D
M(5)
nEM
U1
(4)
nFLA
SH
.AD
V(2)
KB
.C4
(5)
nFLA
SH
.CS
2B(2)
FLA
SH
.D[0..15]
(2,8,10)
CA
M.D
2
UW
IRE
.SD
I(5)
VD
D_3V
3
MC
BS
P2.D
R(8)
I2C.S
CL
(5,6,7)
MC
BS
P1.F
SX
(5,7)
FLA
SH
.A24
DC
MM
C.C
LK(5)
GP
IO9
(5)
LCD
.P3
U19
SN
75240PW
1
2
3
45
6
7
8G
ND
C
GN
D
DG
ND
B
GN
D
A
MC
SI2.D
OU
T(5)
VLY
NQ
.RX0
(8)
CA
M.D
0
FLA
SH
.A22
GP
IO6
(5)
FLA
SH
.D8
MC
BS
P1.C
LKX
(5,7)
FLA
SH
.A1
UA
RT1.TX
(5,8)
CA
M.D
[0..7](5)
KB
.C0
(5)
FLA
SH
.A4
nFLA
SH
.CS
3(2)
C87
.01uF
FLA
SH
.A2
R128
5.1
R132
22K
nFLA
SH
.CS
1A(2,9)
C82
.01uF
0480:0000 - 04FF:FFFF
FLA
SH
.D4
D5
LED
,RE
D
LAN
_RE
SE
T(6)
VD
D_3V
3
nFLA
SH
.CS
2(2,9)
T1E2009
8691114 12 16 3 15
TD+
TD-
RD
+
RD
-R
X-R
XCT
RX+
TX-
TX+TXC
T D7
LED
, GR
N
P9
RJ45
12345678
109
A1
A2
A3
A4
A5
A6
A7
A8
S0S1
VD
D_3V
3
R130
5.1
U4B
74LVC
139
141315
1211109
168ABG
Y0
Y1
Y2
Y3
VCCGND
0580:0000 - 05FF:FFFF
VD
D_3V
3
U13
AT93C
46
12 34
5
67
8CS
SK DI
DO
GND
OR
GD
C
VCC
FLA
SH
.A1
FLA
SH
.D1
FLA
SH
.A24
(2,9)
FLA
SH
.D3
FLA
SH
.D12
0500:0000 - 057F:FFFF
R122
10K
GROUNDED PINS
+C
35
10uf/10V
LINK
LED
Y3FXP
200-2020.000M
HZ
12 nFLA
SH
.WE
(2,8,9)R
125330, 0603
R126
330, 0603
CF
LAS
H_E
N(8)
FLA
SH
.D8
RXLE
D
FLA
SH
.A3
VD
D_3V
3
D8
LED
,YE
LC
34.01uF
FLA
SH
.D9
VD
D_3V
3
R127
13
C46
.01uF/10V
D6
LED
,YE
L
FLA
SH
.D14
FLA
SH
.A[1..25]
(2,8,9)
FLA
SH
.D0
BS
ELE
DF
LAS
H.D
13
C78
20pf,10V
FLA
SH
.D6
nEX_C
S3
(5)
R96
10K
R161
NO
PO
P
nEX_C
S4
(5)
C72
.01uF
C47
.01uF/10V
C86
.01uF
FLA
SH
.D7
<Doc>
A1
OM
AP
5912 Starter K
it
B
1010
Monday
, July 26, 2004
G. C
oley
10Mb E
therentTitle :
Size
Docum
ent Num
berR
ev
Date:
Sheet
of
12203 Southw
est Freew
ayS
tafford, Texas 77477
Catalog
OM
AP
Gro
up
Modified by
:
This document contains
information on a product under
developm
ent and is issued forev
aluation purposes only.
Features characteristic data
and other information are
subject to change.
C45
.01uF/10V
VD
D_3V
3
FLA
SH
.D[0..15]
(2,8,9)
FLA
SH
.D10
TXLED
0400:0000 - 047F:FFFF
VD
D_3V
3
R160
0, 0603
C88
.01uF
FLA
SH
.D5
R131
100
nFLA
SH
.OE
(2,8,9)
R162
FLA
SH
.A23
(2,9)
R124
330, 0603R
123330, 0603
U12
LAN
91C96-TQ
FP
99 12345
78910
11
12131415
1718
19
2021232425
2627283031323334353637
38
394041424344454647
48
4950515253
55565758
59
60616263
656667686970
71
7273 74 757677
79
80818283848588
89
90919394959697
98
1006222954649216788687
IOS
2
EN
EE
PE
ED
O/S
DO
UT
EE
DI
EE
CS
EE
SK
D8
D9
D10
D11
VDD
D12
D13
D14
D15
INTR
0/IRE
Q/IN
TRIN
TR1/IN
PA
CK
VDD
INTR
2/DTA
CK
/0IN
TR3/D
TAC
T/1IO
CS
16/IOIS
16S
BH
E/C
E2
BA
LE/W
E
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/F
WE
VDD
A11/F
CS
A12
A13
A14
A15
A16
A17
A18
A19/C
E1
VDD
IOR
D/XD
SIO
WR
/R/W
ME
M/O
EA
EN
/RE
G/A
SIO
CH
RD
Y/W
AIT
D0
D1
D2
D3
VDD
D4
D5
D6
D7
RE
SE
TP
WR
DW
N/TXC
LKB
SE
LED
/RXD
LNK
LED
/TXDR
XLED
/RXC
LKTXLE
D/TXE
N
AVDD
TPE
TXDP
TPE
TXNTP
ETXD
NTP
ETXP
TXN/C
RS
TXP/C
OLL
AVDD
CO
LNC
OLP
RE
CN
RE
CP
TPE
RXN
TPE
RXP
RB
IAS
AVDD
XEN
DE
CE
N16
OM
/PC
MC
IAXTA
L1XTA
L2IO
S0
IOS
1
VDD
GNDGNDGNDGNDGNDGNDGNDGNDAGNDAGNDAGND
FLA
SH
.D15
FLA
SH
.D11
R129
13
R163
0
FLA
SH
.RD
Y(2,8,9)
R121
10KC
43.01uF
/10V
FLA
SH
.D2
C79
20pf,10V
LAN
_INTR
0(5)
D-1
Appendix A
Current Measurement Procedures
This appendix describes how to use the test points on the OMAP5912 targetmodule to take current measurements for each of the voltage rails.
D.1 Basic Principle D-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.2 Basic Measuring Techniques D-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.3 Connection Methods D-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix D
Basic Principle
D-2
D.1 Basic Principle
The basic concept is measuring the voltage drop across a .1 Ω resistor todetermine the total current consumed. This technique is voltage levelindependent. The formula used to determine the current is:
Voltage Drop /resistor = Current (ma)
The table below shows the measured voltage drop across a .1 Ω resistor foreach of the subsequent current flows:
Voltage Drop Current(ma)
.0001 1
.001 10
.05 50
.01 100
.02 200
.05 500
.1 1000
The reason such a small value has been chosen is to do the following:
Limit the power
Limit the size of the resistor
Limit the voltage drop to a point where it minimizes the impact on the actualvoltage level
D.2 Basic Measuring Techniques
Care must be taken to minimize the impact on the operation of the circuitry onthe voltage rails while taking the measurements. There are two basic ways inwhich the voltage drop across the resistors can be measured withoutimpacting the operation of the circuit:
Mill volt Voltmeter Good for steady state current readings Poor response to current changes
Oscilloscope Good for real-time measurement Good for storage of the data Good response to current changes
Connection Methods
D-3Current Measurement Procedures
D.3 Connection Methods
Following are the connection methods and setup for each of these methods.
D.3.1 Connecting a Voltmeter to Measure Voltage Drop
Voltmeter Power and Ground
Insure that the voltmeter used is either battery powered or if ACpowered, that the ground of the meter is isolated from the earth andsystem ground. We don’t want to tie one side of the resistor to groundwhile attempting the test . It results in shorting out the voltage supply.
1) Power off the system.
2) Set the meter to the Mv setting
3) Set the scale to 1000 mv
4) Connect the voltmeter as shown in Figure D−1:
Figure D−1. Connecting Voltmeter to Measure Voltage
TPxTPx
SHx
10 MV
5) Turn on the system power.
6) The voltage displayed is in mV. A display of 10 mV is equal to 100 ma.
Connection Methods
D-4
D.3.2 Connecting an Oscilloscope to Measure Voltage Drop
Oscilloscope Power and Ground
Insure that the Oscilloscope used is either battery powered or if ACpowered, that the ground of the scope is isolated from the earth andsystem ground. We don’t want to tie one side of the resistor to groundwhile attempting the test. It results in shorting out the voltage supply.
This test takes two probes for the test. It takes the voltage measured at TPxand add it to the inverted level measured at TPy, giving the differential voltagebetween the two points displayed on the Oscilloscope.
1) Power off the system.
2) Set the Oscilloscope as follows:
a) A channel to DCb) B channel to DCc) Set trigger source as Ad) Set A channel to .01 V/DIVe) Set B channel to .01 V/DIVf) Set B channel to invertedg) Set A channel + B channel (Add)h) Set to .1 Sec/Div (Various settings are OK)
3) Connect the Oscilloscope as shown in Figure D−2:
Figure D−2. Connecting Oscilloscope to Measure Voltage
TPx TPySHx
CH A CH A Trig
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
4) Turn on the system power.
5) The voltage displayed is in mV. A display of 10 mV is equal to 100 ma.
Connection Methods
D-5Current Measurement Procedures
6) Current can be measured over time by getting the value at any pointacross the trace. As current loads change, the voltage display changes.An example scope display is shown below.
D.3.3 Connecting an Oscilloscope to Trigger Data Collection
Another function of the oscilloscope is to trigger the collection of data. This canbe useful when you want to measure the current based upon an event fromsoftware or during a specific period where the software is in a particular pieceof code.
The following procedure shows how to set things up for this technique. Thisrequires a 4-channel scope.
1) Power off the system.
2) Set the Oscilloscope as follows:
a) A channel to dcb) B channel to dcc) Set trigger source as externald) Set A channel to .01 V/DIVe) Set B channel to .01 V/DIVf) B channel invertedg) Set A channel + B channelh) Set to .1 Sec/Div
Connection Methods
D-6
3) Connect the Oscilloscope as shown in Figure D−3:
Figure D−3. Connecting Oscilloscope for Data Collection
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
TPx TPxSHx
CH A CH A Trig
External trigger point such as a GPIO pin
4) Turn on the system power.
5) The voltage displayed is in mV. A display of .100 mV is equal to 10 ma.
6) Using the storage mode of the scope, current can be measured during theevent or triggered by the event. As current loads change, the voltagedisplay changes. An example scope display is shown below.
By measuring the voltage at multiple points within the trigger window, theaverage current can be calculated.
Index
Index-1
Index
3 V power design 1-28
3 V power supply 1-18, 1-28 to 1-29
3.3 V power design 1-26
3.3 V power supply 1-18, 1-25 to 1-27
AACT93C46 EEPROM 1-75
address bus for Flash memory 1-44
address decode logic for compact Flashmemory 1-60
address decode logic for Flash memory 1-44 to1-45resistor options 1-45
audio CODECAIC23 audio inputs 1-51 to 1-52AIC23 audio outputs 1-52 to 1-53AIC23 clocking 1-53 to 1-54AIC23 I2C address definitions 1-56AIC23 power design 1-55design diagram 1-50OMAP5912 to AIC23 interface 1-56 to 1-58
AVDD analog power 1-55
Bbattery configuration diagram 1-40
battery mode 1-39 to 1-41optional configuration diagram 1-40 to 1-41
BE0 pin 1-60
BE1 pin 1-60
BFAIL pin 1-16
board dimensions B-1 to B-2
bottom side component locations A-3
BVDD digital power 1-55
CC25 filter 1-39C30 capacitor 1-29C32 capacitor 1-25C48 1-52C52 1-52CFLASH_EN signal 1-60chip select resistor options for Flash memory 1-45client operation mode of USB port 1-66compact Flash
address decode logic 1-60 to 1-61CFLASH_EN decode logic 1-60data bus interface 1-61integrated interface 1-58CFLASH.IREQ 1-59interface signals 1-59memory mapping 1-61power interface 1-61 to 1-62socket design 1-58
compact flash circuit 1-70compact Flash connector pinout 3-5 to 3-7component listing for OMAP5912 target mod-
ule 1-2 to 1-4component locations A-1
connectors and jumpers 5-3indicators 5-4key components 5-2
CONF pin 1-17connector A pinout 2-2connector B pinout 2-4 to 2-6connector C pinout 2-6 to 2-8connector D pinout 2-8 to 2-10control interface for power management 1-19, 1-30
to 1-32control signals for Flash memory 1-44core voltage 1-38
Index
Index-2
core voltage circuit design 1-38
Core voltage rail 1-19
CSXA signal 1-44
CSXB signal 1-44
current measurement proceduresbasic principle D-2basic techniques D-2connection methods D-3 to D-6
DD4 LED 1-23
data bus for Flash memory 1-44
DC Input block 1-18
dc power connector pinout 3-5
DDR SDRAMdiscussion 1-47Elpida EDK2516CBBH DDR Device 1-49 to
1-50circuit design 1-48
default core voltage 1-30
digital current input 1-22 to 1-23
DLL block 1-19
DLL voltage 1-36 to 1-37adjustment 1-37circuit design 1-36
DSP block 1-19
DSP voltage control 1-35design diagram 1-35
DVDD digital power 1-55
Eethernet
circuit design 1-69crystal 1-72EEPROM 1-74 to 1-75output section 1-73interrupt line 1-70LAN91C96 transceiver 1-71memory address decode 1-70 to 1-71status LEDs 1-75 to 1-76
ethernet address decode logic figure 1-70
ethernet connector pinout 3-2
ethernet interface design diagram 1-69
expansion connectors 2-1connector A 2-2 to 2-3connector B 2-4 to 2-5connector C 2-6 to 2-7connector D 2-8 to 2-9connector specification 2-10
FFCC warning viiFLASH circuit design 1-42Flash memory
address bus 1-44address decode logic 1-44 to 1-45address decode resistor options 1-45chip select resistor options 1-45circuit design 1-42 to 1-43control signals 1-44data bus 1-44general-purpose mode support 1-46 to 1-47supported configurations 1-41
flash memory bus memory map 1-5 to 1-6
Ggeneral-purpose mode support 1-46 to 1-47GPIO1 signal 1-44GPIO9 signal 1-65, 1-66
Hheadphones connector pinout 3-8host operation mode of USB port 1-65HPVDD analog power 1-55
II/O connectors 3-1
compact Flash 3-5 to 3-7dc power 3-5headphones 3-8JTAG 3-3line in 3-9microphone in 3-10Multi-ICE 3-4ethernet 3-2serial 3-2USB client adapter 3-11 to 3-12USB host 3-10
Index
Index-3
I2C serial interface 1-32 to 1-64INT pin 1-32
JJ4 header 1-39JP1 1-63JP2 1-39JP2 option jumper 1-23JTAG connector pinout 3-3JTAG/Multi-ICE interface
design description 1-62 to 1-64features 1-62
LL2 inductor 1-27LAN_INTRO signal 1-70LAN91C96 transceiver 1-71, 1-74LDO1 of the TPS65010 1-25LDO2 of the TPS65010 1-29LED2 1-31line in connector pinout 3-9LOW_PWR pin 1-21, 1-31
MMcBSP1 1-57McBSP1.CLK 1-57McBSP1.DR 1-57McBSP1.DX 1-57McBSP1.FSX 1-57MCLK signal 1-54mechanical specifications of OMAP5912 target
module 4-1 to 4-4memory address decode for ethernet 1-70 to 1-71memory map
flash bus 1-5 to 1-6SDRAM 1-7
MICBIAS output 1-52microphone in connector pinout 3-10MODE pin 1-56MPU_BOOT signal 1-44MPU_RESET signal 1-12Multi-ICE connector pinout 3-4
NnEX_CS3 signal 1-71nEX_CS4 signal 1-71notational conventions vnPWRON_RESET signal 1-12nTRST signal 1-63
OOMAP5912 processor
clock interface 1-10 to 1-1112 HMZ clock 1-11crystal configuration 1-11oscillator configuration 1-11
configuration pins 1-16 to 1-18packages 1-8power connections 1-13 to 1-15reset interface 1-12 to 1-13
OMAP5912 target module, block diagram 1-4OMAP5912 target module back side mechanical
specifications 4-3OMAP5912 target module dimensions B-1 to B-2OMAP5912 target module schematics C-1 to C-12OMAP5912 target module top side mechanical
specifications 4-2ON_OFF pin 1-17oscilloscope connecting for data collection D-5 to
D-6oscilloscope connecting for voltage drop D-4 to
D-5
PP11 1-63P2 connector 1-63P3 connector 1-63P4 pin of USB connector 1-65, 1-66P6 connector 1-52P7 power jack 1-23power budget for OMAP5912 target module sec-
tions 1-19 to 1-20power management circuitry
3 V power design 1-283 V supply 1-28 to 1-293.3 V power design 1-263.3 V supply 1-25 to 1-27
Index
Index-4
power management circuitry (continued)battery mode 1-39 to 1-41block diagram 1-18 to 1-19control interface 1-30 to 1-32core voltage 1-38digital current input 1-22 to 1-23DLL voltage 1-36 to 1-37DSP voltage control 1-35power budget 1-19 to 1-20real time clock power 1-33 to 1-34SDRAM power design 1-24SDRAM voltage 1-24 to 1-25TPS65010 1-20 to 1-22
PTC1 device 1-61
RR100 pull down resistor 1-65
R115 resistor 1-68
R117 resistor 1-68
R118 resistor 1-68
R134 resistor 1-52
R136 resistor 1-52
R139 resistor 1-52
R145 resistor 1-57
R160 resistor 1-75
R169 resistor 1-66
R199 pull down resistor 1-65
R291 resistor 1-63
R49 resistor 1-55
R54−62 resistors 1-62
R64−66 resistors 1-62
R74 resistor 1-39
R77 resistor 1-38
R78 resistor 1-38
R79 resistor 1-39
R90 resistor 1-36
R91 resistor 1-36
real time clock power 1-33 to 1-34design diagram 1-33 to 1-34voltage adjustment 1-34
related documentation vii
related documentation from Texas Instruments vi
RS232 driver function 1-68
RTC block 1-19
Sschematics for the OMAP5912 target module C-1
to C-12SCL pin 1-32SCLK 1-56SDA pin 1-32SDIN 1-56SDRAM memorymap 1-7SDRAM rail 1-18SDRAM voltage 1-24 to 1-25serial connector pinout 3-2serial interface design diagram 1-67serial port
design 1-67features 1-67RS232 driver function 1-68
STING 1-56supported configurations of Flash memory 1-41SW! 1-31
TTLV320AIC23 1-51top side component locations A-2TPS65010 integrated circuit 1-18, 1-21
Vcc input filter 1-23TPS65010 control interfaces diagram 1-30trademarks vii
UU10 power management device 1-66U14 signal 1-68U16 power distribution switch 1-65U19 USP port transient protection device 1-66U4 74LVC139 device half 1-70U4B half of SN74LVC139 decoder 1-60U5 TPS71501 LDO regulator 1-36U8 SN74LVC244AGQN buffer 1-62 to 1-64U9 FDC6331L integrated power switch 1-35U9 TPS71501 LDO regulator 1-33UART1 serial port 1-68UART3 serial port, switching to by changing resis-
tors 1-68
Index
Index-5
USB client adapter connector 3-11 to 3-12USB host connector pinout 3-10USB interface design diagram 1-64USB port
client operation mode 1-66selecting 1-66
design description 1-64features 1-64host operation mode 1-65
selecting 1-65USB.DM signal 1-65USB.DP signal 1-65USB.PUEN signal 1-66
VVCORE ouput voltage 1-38VDD_3V3 power 1-15
measure current consumption 1-27
VDD_3VA power, measure current consump-tion 1-29
VDD_CORE power 1-15measure current consumption 1-38
VDD_DLL power 1-14measure current consumption 1-37
VDD_DSP pin 1-15measure current consumption 1-35
VDD_RTC power 1-15measure current consumption 1-34
VDD_SDRAM power 1-15measure current consumption 1-25
voltmeter connecting D-3
XX2 external crystal oscillator 1-54