Ofdm Proposed Paper

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A Pipelined Implementation of OFDM

Synchronization for Wireless LAN

M.Janani priya, P.G Scholar, Department of ECE,Anna University of Technology, Coimbatore.

AbstractThe orthogonal frequency-division

multiplexing access technique has recently been

attracting considerable interest especially for wireless

local area networks (WLANs).The use of IFFT/FFT

as an efficient way to realize the OFDM function and

the concept of the guard interval to avoid the

intersymbol interference (ISI) and inter-carrier

interference (ICI). This is reflected by the adoption of

this technique in applications such as digital

audio/video broadcast (DAB/DVB), wireless LAN

(802.11a and HiperLAN2), broadband wireless(802.16) and xDSL. In parallel, Field Programmable

Gate Arrays (FPGAs) are also emerging as a

fundamental paradigm in the implementation of these

standards. This is due to their increased capabilities

(speed and resources).The use of IFFT/FFT as an

efficient way to realize the OFDM function and the

concept of the guard interval to avoid the intersymbol

interference (ISI) and inter-carrier interference (ICI).

Index TermsFPGA, WLAN, OFDM, 802.11a

I. INTRODUCTION

OFDM can be seen as either a modulation

technique or a multiplexing technique. One of themain reasons to use OFDM is to increase the

robustness against frequency selective fading or

narrowband interference. In a single carrier system,

a single fade or interferer can cause the entire linkto fail, but in a multicarrier system, only a small

percentage of the subcarriers will be affected. Error

correction coding can then be used to correct for

the few erroneous subcarriers.

Wireless communications standards and

digital subscriber lines technology, in addition to

other communication technologies, are utilizing the

widely adopted Orthogonal Frequency Division

Multiplex (OFDM) technique. This is due to the

genuine advantage of OFDM over single carriersystem in multi-path fading channels. Among the

standards that are based on OFDM are the IEEE

802.11a&g for Wireless Local Area Networks

(WLANs), Wi-Fi, and the growing IEEE802.16 for

Metropolitan Access, Worldwide Interoperability

for Microwave Access (WiMAX). The fast growthof these standards has paved the way for OFDM to

be among the widely adopted standards and to be

as a fundamental candidate for the construction of

the next generation telecommunication networks.

OFDM is of great interest by researchers and

research laboratories all over the world. It has

already been accepted for the new wireless local

area network standards IEEE 802.11a, High

Performance LAN type 2 (HIPERLAN/2) andMobile Multimedia Access Communication

(MMAC) Systems. Also, it is expected to be used

for wireless broadband multimedia

communications. Data rate is really what

broadband is about. The new standards specify bit

rates of up to 54 Mbps. Such high rate imposeslarge bandwidth, thus pushing carriers for values

higher than UHF band. For instance, IEEE802.11a

has frequencies allocated in the 5- and 17- GHz

bands.

II. TDS-OFDM SYSTEM MODEL

The frame structure of a TDS-OFDM

system signal frame consists of two parts, a frame

head and a frame body as well. The LPN -length

frame head, serving as TGI, is composed of a pre-amble, a PN sequence and a post-amble. The frame

head PN(n) is a series of complex-valued symbolswith QPSK constellation of which the real and

imaginary parts are identical. The PN sequence

with Lm samples is generated based on m-sequence,

and the pre-/post-amble is the cyclical extensionsof the PN and has the length of Lpre and Lpost,

respectively. OFDM modulation is applied to the

frame body, i.e. the Nc -length inverse discrete

Fourier transformation (IDFT) block.

A base-band TDS-OFDM system is shown

in Fig.1 without forward-error-coding (FEC) part.

At the transmitter side, the random bit stream is

mapped to complex-valued symbols, and each

block bearing Nc data symbols is modulated by

means of IDFT (implemented by IFFTinversefast FT) to generate a frame body. The PN head

(namely frame head) is inserted in the start of each

frame body to construct a signal frame, and the

symbol rate of both parts is 1/T=7.56 MSPS. The

transmitted signal s(t) is generated by an SRRC

(squared root raised cosine) filter. Meanwhile in thereceiver, the received signal r(t), interfered by

multi-path channel and CFO, is 4-fold over-

sampled with a certain SFO. The nominal sampling

period Ts=T/4. Then the SFO and CFO of the

received signal are corrected in the synchronizer


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Fig.1.The base-band model of the TDS-OFDM system

SFR & CFR. The PN head is removed from the

filtered signal, which needs the help of frame

timing and of the estimated channel impulse

response (CIR). From the separated frame body,data symbols are demodulated by DFT

(implemented by FFTfast FT). The channel

equalizer eliminates channel distortions, and then

the de-mapper transforms the equalized symbols

into the output bits.

For reducing spectral overhead on pilot,

time-domain synchronous OFDM(TDS-OFDM)

replaces cyclic prefix (CP) with pseudo-noise (PN)

sequence and removes pilot from OFDM signal.

Thanks to its higher channel throughout, TDS-

OFDM has been adopted as one of the key

modulation schemes for Chinese standard of digital

terrestrial television broadcasting (DTTB).

The digital baseband receiver, one of the

key parts in an OFDM system, plays an importantrole in determining the overall transmission

performance. Design and implementation of the

OFDM receiver have been topics of intense activity

for researchers and engineers since OFDM was

invented. Numerous papers have been published to

address issues concerning OFDM receiver design,including the issue of synchronization for received

signals. An OFDM system is very vulnerable to

synchronization errors and there are more stringent

requirements for synchronization tasks in an

OFDM receiver than in others. In addition to the

initial estimation for synchronization parameters,further elimination of residual synchronization

errors (including carrier-frequency and timing

errors or offsets) is absolutely necessary. The

absence of an efficient error elimination scheme in

the OFDM receiver would severely degrade the

overall system performance. Obviously, how to

design an efficient and robust elimination schemefor residual synchronization errors is a critical issue

while implementing a digital OFDM receiver.

Error elimination is mainly composed of

two processing tasks, error estimation and error

correction. Various algorithms have been proposedto estimate both the carrier frequency offset (CFO)

and the sampling time offset (STO) using phases or

phase differences of signals at pilot subcarriers.

Underlying these algorithms is the least-squares

(LS) line-fitting method or its weighted version. In

order to obtain good estimation accuracy, the

number of pilot subcarriers per OFDM symbol

should be large enough; otherwise, for many burst-

type OFDM systems (such as IEEE 802.11a/g

WLANs and 802.16d/e BWA systems), due to very

limited number of pilot subcarriers per OFDMsymbol, phase differences have to be averaged over

many OFDM symbols for the sake of noise

suppression. However, averaging across many

symbols calls for large data storage and slows

down the estimators response to diminishing

residual errors.

III. OFDM SYSTEM WITH PIPELINING

IMPLEMENTATION

The simple form for a point-to-pointOFDM system could be considered as a mirroring

of the transmitter building blocks into the receiver


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side. Figure 2, presents the basic building blocks

that are used in both the transmission and reception

sides. The signals associated with each block are

Fig.2. OFDM System Model

highlighted to determine the digital and analog

parts of the design, as well as the serial and parallel

feeding..

Moreover, to eliminate the banks of

subcarrier oscillators and coherent demodulators

required by frequency-division multiplex,completely digital implementations could be built

around special-purpose hardware performing the

fast Fourier transform (FFT), which is an efficient

implementation of the DFT. Recent advances in

very-large-scale integration (VLSI) technology

make high-speed, large-size FFT chips

commercially affordable. Using this method, both

transmitter and receiver are implemented using

efficient FFT techniques that reduce the number of

operations from N2 in DFT down to N log N. In the

1980s, OFDM was studied for high-speed modems,digital mobile communications, and high-density

recording. One of the systems realized the OFDMtechniques for multiplexed QAM using DFT and

by using pilot tone, stabilizing carrier and clock

frequency control and implementing trellis coding

are also implemented. Moreover, various-speed

modems were developed for telephone networks.

A. Pipelining Design:

The design makes use of pipelining, and

this was mainly achieved through duplicating the

memory elements (registers or RAMs); that will

buffer the incoming stream of bits while the

previous stream is being processed. The first stage

in the PHY transmitter architecture is scrambling,where the data bits are fed to the generator

polynomial described by the following

equation:

S(x) = X7 + X4 + 1.

A straight forward translation of the

scrambling function into hardware is based on ashift register and two 2- input XOR gates.

These hardware entities are used to

represent the polynomial generator.

B. QAM:

To perform IFFT, the interleaved bits are

translated or mapped into two components the In-

phase and the Quadrature (I and Q) components.

Depending on the PHY mode and the data rate

selected, the OFDM sub-carriers are modulatedusing BPSK, QPSK, 16-QAM or 64-QAM. The

interleaved bits are grouped into chunks of NBPSC(1, 2, 4 or 6) bits, respectively. The grouped bits are

used to address the specific ROM and to be

mapped into the corresponding I/Q values as per

the selected modulation scheme.

C. Mapper Architecture:

The mapper is implemented with 4 ROMs,

one for each modulation scheme. The ROMs

contain the corresponding value of the I and Q

values, where the grouped bits are used to index

these ROMs and obtain the corresponding I/Q pair.

Moreover, the values stored in the ROMs are

normalized with the normalization factor k, as pereach modulation scheme. This will reduce the


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introducing 4 multipliers to normalize the resulting

I/Q pair [2]. The representation of these I and Q

values is based on a fixed point representation with16 bits width and a 12 bits as a fractional part.

The mapper produces only 48 data sub-

carriers, whereas the IFFT stage requires 64 pairsof I and Q. The pilot sub-carriers (4 pilots) are

added at specific locations, to assist the receiver inperforming channel estimation and frame detection.

Those pilots are put in sub-carriers -21,-7, 7 and 21,

and are based on BPSK modulation. This was

implemented as a block used to store the generated

I/Q pairs by the mapper, and also to add both the

zero and pilot subcarriers. To achieve that, two

single-port distributed RAMs with a size of (64*16

bit) were used to store the I/Q pairs in their

corresponding locations, and to provide pipelining

capability at this stage as well.

D.IFFT:

Next in the chain comes the IFFT block.

This block was the only main block not designed in

VHDL by the author, the Intellectual Property (IP)

core available in the Xilinx development

environment (ISE) was utilized [7]. The generatedIP was implemented to run in a pipelining

streaming I/O mode for continuous processing of

the arriving data instead of working on the whole

symbol samples all at once. This capability came

from the pipelining provided by the previous and

the next stages, where each generated I/Q pair in

the I/Q bank is fed to the IFFT processor. Next,after the required number of cycles by the IFFT

block, the generated real and imaginary pairs are

forwarded to the CP block.

The last 16 samples of the generated

OFDM symbol are copied into the beginning to

form the cyclic prefix. In the 802.11a standard, the

last 16 samples of the IFFT output are replicated at

the beginning to form an 80 sample complete

OFDM symbol. These 16 samples correspond to a

0.8 s period, which is considered as the maximum

delay in the multipath environment. This stage was

implemented by using two single-port distributedRAMs. The first is of a size 16*16 bits, which is

used to store the cyclic prefix samples. The other

RAM is of a size 64*16 bits, and it is used to holdthe OFDM symbol samples. Again, another copy of

each RAM (CP and Symbol RAMs) is added to

provide pipelining.

E. Synchronization:

To avoid inter-symbol interference and tomaintain the orthogonality of the OFDM signal, the

last L samples in a frame are duplicated at the start

of the frame. This technique is used in most OFDM

systems and is referred to as adding a cyclic prefix.The synchronization algorithm uses the correlation

between these identical data blocks to estimate the

time and frequency offset. To maintain reliable

communication, the system needs to besynchronized both in time and in frequency. In this

paper, we refer to time synchronization as finding

the frame start of an OFDM block.

Synchronizing the phase of the sample

clock is not necessary, and sample-clocksynchronization will therefore not be considered in

this paper. The requirements for the time offset

estimation depend on the length of the CP and the

length of the channel impulse response. If the FFT

window is positioned in the part of the cyclic prefix

which is not affected by the previous symbol due to

channel dispersion, the only effect of the output

symbols from the FFT will be a phase shift

proportional to the time offset. The difference in

phase shift between two consecutive subcarriers

will however be constant for all subcarriers. Sincethis difference is constant for all subcarriers, and

our data is differentially modulated, we can

estimate the phase offset and compensate for it

before the data is demodulated. By this technique, a

small time offset will not yield any significant

performance degradation.

IV.CONCLUSION

An OFDM synchronization unit is

presented. The algorithm is computationally

intensive, but by making proper simplifications, itis shown that a hardware implementation is

feasible. Several optimizations to reduce thecomplexity have been designed. Because of

overlapping multicarrier modulation technique it

save almost 50% of bandwidth and also reduce

crosstalk between subcarriers.

V. REFERENCES

1. Guanghui Liu and Sergey V. Zhidkov,A CompositePN-Correlation Based Synchronizer for TDS-OFDM

Receiver,IEEE TRANSACTIONS ON

BROADCASTING, VOL. 56, NO. 1, MARCH 2010pp.no.77-85.

2. Chang.K, Sobelman.G, Saberinia and Tewfik.A,Transmitter Archeiticture for Pulsed OFDM, in theproc. of the 2004 IEEE Asia-Pacific conf. on circuitsand systems, Vol. 2, Issue 6-9, Tainan, ROC, Dec.

2004.

3. Fu.J, Wang.J, Song.J, Pan, and Yang, A simplifiedequalization method for dual PN-sequence padding

TDS-OFDM systems, IEEE Trans. Broadcast., vol.

54, no. 4, pp. 825830, Dec. 2008.

4. Garcia.J, FPGA-Based Hardware Implementationsof OFDM Modules for IEEE 802 standards: A

common design, Thesis Report, Tonantzintla,Mexico, Sep.2005 pp.no.98-105.

5. Hieskala.J and Terry.J , OFDM Wireless LANs: ATheoretical and Practical Guide,SAMS Publishing,U.S, 2002.


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6. Prasad.R, OFDM for Wireless CommunicationSystems. Artech House, Inc. Boston, 2004.

7. Shousheng.H and Torkelson.M Designing pipelineFFt processor for OFDM (de) modulation,(1988)in

proc.URSI Int ,symp. on signal syst Electron,Vol29,pp.257-262

8. Stefan Johansson, Martin Nilsson and Peter Nilsson,An OFDM Timing Synchronization ASIC,

Department of Applied Electronics, LundUniversitypp.no.324-327.

9. uan I. Montojo, and Laurence. B Milstein ChannelEstimation for Non-Ideal OFDM Systems,(2010)IEEE Transactions On Communications, Vol. 58,

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Ofdm Proposed Paper