Embed Size (px)
Citation preview
O-RAN Intel® FPGA IP DesignExample User Guide
Updated for Intel® Quartus® Prime Design Suite: 21.2
IP Version: 1.5.1
SubscribeSend Feedback
UG-20317 | 2021.09.14Latest document on the web: PDF | HTML
Contents
1. About the O-RAN Intel® FPGA IP Design Example...........................................................3
2. Getting Started with the O-RAN Intel FPGA IP Design Example...................................... 42.1. Generating the O-RAN IP Design Example.................................................................4
2.1.1. O-RAN IP Design Example Parameters..........................................................62.2. Simulating the O-RAN IP Design Example................................................................. 6
2.2.1. Simulating the O-RAN Design Example for Intel Agilex F-Tile Devices.............. 152.2.2. Enabling Dynamic Reconfiguation to the Ethernet IP..................................... 152.2.3. O-RAN IP Design Example Testbench.......................................................... 15
2.3. Operating the O-RAN IP Design Example.................................................................162.3.1. Generating and Downloading the Programming .elf File............................. 20
3. O-RAN Intel FPGA IP Design Example Functional Description....................................... 23
4. O-RAN IP Design Example User Guide Archives............................................................ 31
5. Document Revision History for the O-RAN Intel FPGA IP Design Example User Guide.. 32
Contents
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
2
1. About the O-RAN Intel® FPGA IP Design ExampleThe design example allows you to simulate, compile, and test your O-RAN IP instanceon various development boards. The design example includes Ethernet IP, eCPRI IP,eCPRI IOPLL, PTP IOPLL, and a test wrapper.
The compiled hardware design example runs on the:
• Intel® Agilex™ F-Series Transceiver-SoC Development Kit for the E-tile designexamples
• Intel Arria® 10 GX Signal Integrity Development Kit
• Intel Stratix® 10 GX Transceiver Signal Integrity Development Kit for the H-tiledesign examples
• Intel Stratix 10 TX Transceiver Signal Integrity Development Kit for the E-tiledesign examples
The design example on F-tile devices supports simulations only.
Related Information
• O-RAN Intel FPGA IP User Guide
• O-RAN Intel FPGA IP Device Support
• About the O-RAN Intel FPGA IP
• eCPRI Intel FPGA IP User Guide
• IOPLL Intel FPGA IP Core User Guide
• Intel Agilex F-series Transceiver SoC Development Kit
• Arria 10 GX Transceiver Signal Integrity Development Kit User Guide
• Intel Stratix 10 GX Transceiver Signal Integrity Development Kit User Guide
• Intel Stratix 10 TX Transceiver Signal Integrity Development Kit User Guide
UG-20317 | 2021.09.14
Send Feedback
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of IntelCorporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Intel assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to inwriting by Intel. Intel customers are advised to obtain the latest version of device specifications before relyingon any published information and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
2. Getting Started with the O-RAN Intel FPGA IP DesignExample
2.1. Generating the O-RAN IP Design Example
Quickly configure your custom IP variation in the IP Parameter Editor and generate adesign example.
Before you begin, ensure both the eCPRI Intel FPGA IP and ORAN Intel FPGA IP areinstalled in the <quartus_installation_dir>/ip/altera_cloud directory.
1. Create an Intel Quartus® Prime Pro Edition project in which to integrate your IP.
a. In the Intel Quartus Prime Pro Edition, click File ➤ New Project Wizard tocreate a new Intel Quartus Prime project, or File ➤ Open Project to open anexisting Quartus Prime project. The wizard prompts you to specify a device.
b. Specify the device family that meets the speed grade requirements for the IP.
c. Click Finish.
2. In the IP Catalog, select O-RAN Intel FPGA IP.The New IP Variation window appears.
3. Specify a top-level name for your new custom IP variation.The parameter editor saves the IP variation settings in a file named<your_ip>.ip.
4. Click OK. The parameter editor appears.
UG-20317 | 2021.09.14
Send Feedback
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of IntelCorporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Intel assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to inwriting by Intel. Intel customers are advised to obtain the latest version of device specifications before relyingon any published information and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
Figure 1. O-RAN IP Parameter Editor
5. Specify the parameters for your IP variation. Refer to Parameters for informationabout specific IP parameters.
6. Click the Design Example tab and specify the parameters for your designexample.
Figure 2. Design Example Parameter Editor
7. Click Generate HDL.The Generation dialog box appears.
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
Send Feedback O-RAN Intel® FPGA IP Design Example User Guide
5
8. Specify output file generation options, and then click Generate.The IP variation files generate according to your specifications.
9. Click Finish. The parameter editor adds the top-level .ip file to the currentproject automatically. If you are prompted to manually add the .ip file to theproject, click Project ➤ Add/Remove Files in Project to add the file.
10. After generating and instantiating your IP variation, make appropriate pinassignments to connect ports and set any appropriate per-instance RTLparameters.
Related Information
O-RAN IP Parameters
2.1.1. O-RAN IP Design Example Parameters
Table 1. O-RAN IP Design Example Parameters
Parameter Values Description
GenerateExampleDesign for
Simulation Select to generate the simulation files. For example for F-tile designs thatsupport simulation only.
Synthesis Select to generate the synthesis files
Synthesis &Simulation
Select to generate the synthesis and simulation files.
Generate FileFormat
VerilogVHDL Select either Verilog HDL or VHDL as the format for generated RTL filessimulation and synthesis. Some submodules are generated in mixed (bothVerilog HDL and VHDL) formats.
Select board Agilex SIDevelopment Kit
Select to allow you to test the design example on the selected Inteldevelopment kit. The wizard automatically selects the target device to matchthe device on the selected Intel development kit. Select AGFB014R24A2E3Vfor an Intel Agilex 10 E-tile device. If your board revision has a different speedgrade of these devices above, you can correct it.
Arria SignalIntegrityDevelopment Kit
Select to allow you to test the design example on the selected Inteldevelopment kit. The wizard automatically selects the target device to matchthe device on the selected Intel development kit. Select 10AX115S2F45I1SGfor an Intel Arria 10 device. If your board revision has a different speed gradeof these devices above, you can correct it.
Stratix 10 SignalIntegrityDevelopment Kit
Select to allow you to test the design example on the selected Inteldevelopment kit. The wizard automatically selects the target device to matchthe device on the selected Intel development kit. Select 1SX280HU2F50E2VGfor Intel Stratix 10 H-Tile and 1ST280EY2F55E2VG for Intel Stratix 10 E-Tile.If your board revision has a different speed grade of these devices above, youcan correct it.
No DevelopmentKit
Select to exclude development kit hardware for the design example. Forexample for F-tile designs that support simulation only.
Number ofchannels
1 to 4 Select the number of channels to generate in the design example.
2.2. Simulating the O-RAN IP Design Example
1. Turn on Example Design ➤ Files Types Generated ➤ Simulation.
2. Run the script to simulate the testbench in the ModelSim, VCS, or VCS MXsimulators.
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
6
Table 2. Simulation Scripts
Simulator File Directory Script
ModelSim Altera SE <variation name> oran_testbench/simulation/setup_scripts/mentor run_vsim.do
VCS <variation name>oran _testbench/simulation/setup_scripts/synopsys/vcs
run_vcs.sh
VCSMX <variation name>oran _testbench/simulation/setup_scripts/synopsys/vcsmx
run_vcsmx.sh
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
Send Feedback O-RAN Intel® FPGA IP Design Example User Guide
7
Figure 3. Transmitter Top-Level Simulation
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
8
Figure 4. Transmitter Top-Level Simulation (Zoomed)
Figure 5. Receiver Top-Level Simulation
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
Send Feedback O-RAN Intel® FPGA IP Design Example User Guide
9
Figure 6. Receiver Top-Level Simulation (Zoomed)
Figure 7. Simulation Transcript Window (Number of Channels = 4)
# Waiting for RX alignment# RX deskew locked# RX lane aligmnent locked# Waiting for link fault clear# Link fault clear# MAC Source Address 0_0 Channel 0: 33445566# MAC Source Address 0_1 Channel 0: 00007788# MAC Destination Address 0_0 Channel 0: 33445566# MAC Destination Address 0_1 Channel 0: 00007788# MAC Destination Address 1_0 Channel 0: 11223344# MAC Destination Address 1_1 Channel 0: 00005566# MAC Destination Address 2_0 Channel 0: 22334455# MAC Destination Address 2_1 Channel 0: 00006677# MAC Destination Address 3_0 Channel 0: 44556677# MAC Destination Address 3_1 Channel 0: 00008899# MAC Destination Address 4_0 Channel 0: 66778899# MAC Destination Address 4_1 Channel 0: 0000aabb# MAC Destination Address 5_0 Channel 0: 778899aa# MAC Destination Address 5_1 Channel 0: 0000bbcc# MAC Destination Address 6_0 Channel 0: 8899aabb# MAC Destination Address 6_1 Channel 0: 0000ccdd# MAC Destination Address 7_0 Channel 0: 99aabbcc# MAC Destination Address 7_1 Channel 0: 0000ddee# eCPRI Common Control Channel 0: 00000041# Enable interrupt eCPRI Common Control Channel 0: 00000241# eCPRI version Channel 0: 2# Disable Oran RX Window Enable Channel 0: 00000000# Disable Oran TX Window Enable Channel 0: 00000000# Enable Oran Static Functional Mode Channel 0: 00000000# Oran Static Static udCompHdr Channel 0: 00000083# MAC Source Address 0_0 Channel 1: 33445566# MAC Source Address 0_1 Channel 1: 00007788# MAC Destination Address 0_0 Channel 1: 33445566# MAC Destination Address 0_1 Channel 1: 00007788# MAC Destination Address 1_0 Channel 1: 11223344# MAC Destination Address 1_1 Channel 1: 00005566# MAC Destination Address 2_0 Channel 1: 22334455# MAC Destination Address 2_1 Channel 1: 00006677# MAC Destination Address 3_0 Channel 1: 44556677# MAC Destination Address 3_1 Channel 1: 00008899# MAC Destination Address 4_0 Channel 1: 66778899# MAC Destination Address 4_1 Channel 1: 0000aabb
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
10
# MAC Destination Address 5_0 Channel 1: 778899aa# MAC Destination Address 5_1 Channel 1: 0000bbcc# MAC Destination Address 6_0 Channel 1: 8899aabb# MAC Destination Address 6_1 Channel 1: 0000ccdd# MAC Destination Address 7_0 Channel 1: 99aabbcc# MAC Destination Address 7_1 Channel 1: 0000ddee# eCPRI Common Control Channel 1: 00000041# Enable interrupt eCPRI Common Control Channel 1: 00000241# eCPRI version Channel 1: 2# Disable Oran RX Window Enable Channel 1: 00000000# Disable Oran TX Window Enable Channel 1: 00000000# Enable Oran Static Functional Mode Channel 1: 00000000# Oran Static Static udCompHdr Channel 1: 00000083# MAC Source Address 0_0 Channel 2: 33445566# MAC Source Address 0_1 Channel 2: 00007788# MAC Destination Address 0_0 Channel 2: 33445566# MAC Destination Address 0_1 Channel 2: 00007788# MAC Destination Address 1_0 Channel 2: 11223344# MAC Destination Address 1_1 Channel 2: 00005566# MAC Destination Address 2_0 Channel 2: 22334455# MAC Destination Address 2_1 Channel 2: 00006677# MAC Destination Address 3_0 Channel 2: 44556677# MAC Destination Address 3_1 Channel 2: 00008899# MAC Destination Address 4_0 Channel 2: 66778899# MAC Destination Address 4_1 Channel 2: 0000aabb# MAC Destination Address 5_0 Channel 2: 778899aa# MAC Destination Address 5_1 Channel 2: 0000bbcc# MAC Destination Address 6_0 Channel 2: 8899aabb# MAC Destination Address 6_1 Channel 2: 0000ccdd# MAC Destination Address 7_0 Channel 2: 99aabbcc# MAC Destination Address 7_1 Channel 2: 0000ddee# eCPRI Common Control Channel 2: 00000041# Enable interrupt eCPRI Common Control Channel 2: 00000241# eCPRI version Channel 2: 2# Disable Oran RX Window Enable Channel 2: 00000000# Disable Oran TX Window Enable Channel 2: 00000000# Enable Oran Static Functional Mode Channel 2: 00000000# Oran Static Static udCompHdr Channel 2: 00000083# MAC Source Address 0_0 Channel 3: 33445566# MAC Source Address 0_1 Channel 3: 00007788# MAC Destination Address 0_0 Channel 3: 33445566# MAC Destination Address 0_1 Channel 3: 00007788# MAC Destination Address 1_0 Channel 3: 11223344# MAC Destination Address 1_1 Channel 3: 00005566# MAC Destination Address 2_0 Channel 3: 22334455# MAC Destination Address 2_1 Channel 3: 00006677# MAC Destination Address 3_0 Channel 3: 44556677# MAC Destination Address 3_1 Channel 3: 00008899# MAC Destination Address 4_0 Channel 3: 66778899# MAC Destination Address 4_1 Channel 3: 0000aabb# MAC Destination Address 5_0 Channel 3: 778899aa# MAC Destination Address 5_1 Channel 3: 0000bbcc# MAC Destination Address 6_0 Channel 3: 8899aabb# MAC Destination Address 6_1 Channel 3: 0000ccdd# MAC Destination Address 7_0 Channel 3: 99aabbcc# MAC Destination Address 7_1 Channel 3: 0000ddee# eCPRI Common Control Channel 3: 00000041# Enable interrupt eCPRI Common Control Channel 3: 00000241# eCPRI version Channel 3: 2# Disable Oran RX Window Enable Channel 3: 00000000# Disable Oran TX Window Enable Channel 3: 00000000# Enable Oran Static Functional Mode Channel 3: 00000000# Oran Static Static udCompHdr Channel 3: 00000083# __________________________________________________________# INFO: Out of reset status # __________________________________________________________# #
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
Send Feedback O-RAN Intel® FPGA IP Design Example User Guide
11
# Channel 0 Oran TX C SOPs count : 0# Channel 0 Oran TX C EOPs count : 0# Channel 0 Oran RX C SOPs count : 0# Channel 0 Oran RX C EOPs count : 0# Channel 0 Oran TX U SOPs count : 0# Channel 0 Oran TX U EOPs count : 0# Channel 0 Oran RX U SOPs count : 0# Channel 0 Oran RX U EOPs count : 0# Channel 0 External PTP TX SOPs count : 0# Channel 0 External PTP TX EOPs count : 0# Channel 0 External MISC TX SOPs count : 0# Channel 0 External MISC TX EOPs count : 0# Channel 0 External RX SOPs count : 0# Channel 0 External RX EOPs count : 0# Channel 1 Oran TX C SOPs count : 0# Channel 1 Oran TX C EOPs count : 0# Channel 1 Oran RX C SOPs count : 0# Channel 1 Oran RX C EOPs count : 0# Channel 1 Oran TX U SOPs count : 0# Channel 1 Oran TX U EOPs count : 0# Channel 1 Oran RX U SOPs count : 0# Channel 1 Oran RX U EOPs count : 0# Channel 1 External PTP TX SOPs count : 0# Channel 1 External PTP TX EOPs count : 0# Channel 1 External MISC TX SOPs count : 0# Channel 1 External MISC TX EOPs count : 0# Channel 1 External RX SOPs count : 0# Channel 1 External RX EOPs count : 0# Channel 2 Oran TX C SOPs count : 0# Channel 2 Oran TX C EOPs count : 0# Channel 2 Oran RX C SOPs count : 0# Channel 2 Oran RX C EOPs count : 0# Channel 2 Oran TX U SOPs count : 0# Channel 2 Oran TX U EOPs count : 0# Channel 2 Oran RX U SOPs count : 0# Channel 2 Oran RX U EOPs count : 0# Channel 2 External PTP TX SOPs count : 0# Channel 2 External PTP TX EOPs count : 0# Channel 2 External MISC TX SOPs count : 0# Channel 2 External MISC TX EOPs count : 0# Channel 2 External RX SOPs count : 0# Channel 2 External RX EOPs count : 0# Channel 3 Oran TX C SOPs count : 0# Channel 3 Oran TX C EOPs count : 0# Channel 3 Oran RX C SOPs count : 0# Channel 3 Oran RX C EOPs count : 0# Channel 3 Oran TX U SOPs count : 0# Channel 3 Oran TX U EOPs count : 0# Channel 3 Oran RX U SOPs count : 0# Channel 3 Oran RX U EOPs count : 0# Channel 3 External PTP TX SOPs count : 0# Channel 3 External PTP TX EOPs count : 0# Channel 3 External MISC TX SOPs count : 0# Channel 3 External MISC TX EOPs count : 0# Channel 3 External RX SOPs count : 0# Channel 3 External RX EOPs count : 0# __________________________________________________________# INFO: Start transmitting packets# __________________________________________________________# # # INFO: Waiting for the Channel 0 C-plane TX traffic transfer to complete# INFO: Channel 0 C-plane TX traffic transfer completed# INFO: Waiting for the Channel 0 U-plane TX traffic transfer to complete# INFO: Channel 0 U-plane TX traffic transfer completed# INFO: Waiting for the Channel 0 eCPRI External TX PTP traffic transfer to complete# INFO: Channel 0 eCPRI External TX PTP traffic transfer completed
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
12
# INFO: Waiting for the Channel 0 eCPRI External TX Misc traffic transfer to complete# INFO: Channel 0 eCPRI External TX Misc traffic transfer completed# INFO: Waiting for the Channel 1 C-plane TX traffic transfer to complete# INFO: Channel 1 C-plane TX traffic transfer completed# INFO: Waiting for the Channel 1 U-plane TX traffic transfer to complete# INFO: Channel 1 U-plane TX traffic transfer completed# INFO: Waiting for the Channel 1 eCPRI External TX PTP traffic transfer to complete# INFO: Channel 1 eCPRI External TX PTP traffic transfer completed# INFO: Waiting for the Channel 1 eCPRI External TX Misc traffic transfer to complete# INFO: Channel 1 eCPRI External TX Misc traffic transfer completed# INFO: Waiting for the Channel 2 C-plane TX traffic transfer to complete# INFO: Channel 2 C-plane TX traffic transfer completed# INFO: Waiting for the Channel 2 U-plane TX traffic transfer to complete# INFO: Channel 2 U-plane TX traffic transfer completed# INFO: Waiting for the Channel 2 eCPRI External TX PTP traffic transfer to complete# INFO: Channel 2 eCPRI External TX PTP traffic transfer completed# INFO: Waiting for the Channel 2 eCPRI External TX Misc traffic transfer to complete# INFO: Channel 2 eCPRI External TX Misc traffic transfer completed# INFO: Waiting for the Channel 3 C-plane TX traffic transfer to complete# INFO: Channel 3 C-plane TX traffic transfer completed# INFO: Waiting for the Channel 3 U-plane TX traffic transfer to complete# INFO: Channel 3 U-plane TX traffic transfer completed# INFO: Waiting for the Channel 3 eCPRI External TX PTP traffic transfer to complete# INFO: Channel 3 eCPRI External TX PTP traffic transfer completed# INFO: Waiting for the Channel 3 eCPRI External TX Misc traffic transfer to complete# INFO: Channel 3 eCPRI External TX Misc traffic transfer completed# __________________________________________________________# INFO: Stop transmitting packets# __________________________________________________________# # # __________________________________________________________# INFO: Checking packets statistics# __________________________________________________________# # # Channel 0 Oran C SOPs transmitted: 300# Channel 0 Oran C EOPs transmitted: 300# Channel 0 Oran C SOPs received: 300# Channel 0 Oran C EOPs received: 300# Channel 0 Oran C Error reported: 0# Channel 0 Oran U SOPs transmitted: 300# Channel 0 Oran U EOPs transmitted: 300# Channel 0 Oran U SOPs received: 300# Channel 0 Oran U EOPs received: 300# Channel 0 Oran U Error reported: 0# Channel 0 External PTP SOPs transmitted: 4# Channel 0 External PTP EOPs transmitted: 4# Channel 0 External MISC SOPs transmitted: 128# Channel 0 External MISC EOPs transmitted: 128# Channel 0 External SOPs received: 132
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
Send Feedback O-RAN Intel® FPGA IP Design Example User Guide
13
# Channel 0 External EOPs received: 132# Channel 0 External PTP SOPs received: 4# Channel 0 External PTP EOPs received: 4# Channel 0 External MISC SOPs received: 128# Channel 0 External MISC EOPs received: 128# Channel 0 External Error reported: 0# Channel 0 External Timestamp Fingerprint Error reported: 0# Channel 1 Oran C SOPs transmitted: 300# Channel 1 Oran C EOPs transmitted: 300# Channel 1 Oran C SOPs received: 300# Channel 1 Oran C EOPs received: 300# Channel 1 Oran C Error reported: 0# Channel 1 Oran U SOPs transmitted: 300# Channel 1 Oran U EOPs transmitted: 300# Channel 1 Oran U SOPs received: 300# Channel 1 Oran U EOPs received: 300# Channel 1 Oran U Error reported: 0# Channel 1 External PTP SOPs transmitted: 4# Channel 1 External PTP EOPs transmitted: 4# Channel 1 External MISC SOPs transmitted: 128# Channel 1 External MISC EOPs transmitted: 128# Channel 1 External SOPs received: 132# Channel 1 External EOPs received: 132# Channel 1 External PTP SOPs received: 4# Channel 1 External PTP EOPs received: 4# Channel 1 External MISC SOPs received: 128# Channel 1 External MISC EOPs received: 128# Channel 1 External Error reported: 0# Channel 1 External Timestamp Fingerprint Error reported: 0# Channel 2 Oran C SOPs transmitted: 300# Channel 2 Oran C EOPs transmitted: 300# Channel 2 Oran C SOPs received: 300# Channel 2 Oran C EOPs received: 300# Channel 2 Oran C Error reported: 0# Channel 2 Oran U SOPs transmitted: 300# Channel 2 Oran U EOPs transmitted: 300# Channel 2 Oran U SOPs received: 300# Channel 2 Oran U EOPs received: 300# Channel 2 Oran U Error reported: 0# Channel 2 External PTP SOPs transmitted: 4# Channel 2 External PTP EOPs transmitted: 4# Channel 2 External MISC SOPs transmitted: 128# Channel 2 External MISC EOPs transmitted: 128# Channel 2 External SOPs received: 132# Channel 2 External EOPs received: 132# Channel 2 External PTP SOPs received: 4# Channel 2 External PTP EOPs received: 4# Channel 2 External MISC SOPs received: 128# Channel 2 External MISC EOPs received: 128# Channel 2 External Error reported: 0# Channel 2 External Timestamp Fingerprint Error reported: 0# Channel 3 Oran C SOPs transmitted: 300# Channel 3 Oran C EOPs transmitted: 300# Channel 3 Oran C SOPs received: 300# Channel 3 Oran C EOPs received: 300# Channel 3 Oran C Error reported: 0# Channel 3 Oran U SOPs transmitted: 300# Channel 3 Oran U EOPs transmitted: 300# Channel 3 Oran U SOPs received: 300# Channel 3 Oran U EOPs received: 300# Channel 3 Oran U Error reported: 0# Channel 3 External PTP SOPs transmitted: 4# Channel 3 External PTP EOPs transmitted: 4# Channel 3 External MISC SOPs transmitted: 128# Channel 3 External MISC EOPs transmitted: 128# Channel 3 External SOPs received: 132# Channel 3 External EOPs received: 132# Channel 3 External PTP SOPs received: 4
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
14
# Channel 3 External PTP EOPs received: 4# Channel 3 External MISC SOPs received: 128# Channel 3 External MISC EOPs received: 128# Channel 3 External Error reported: 0# Channel 3 External Timestamp Fingerprint Error reported: 0# __________________________________________________________# INFO: Test PASSED # # __________________________________________________________
2.2.1. Simulating the O-RAN Design Example for Intel Agilex F-TileDevices
When targeting Intel Agilex F-tile devices, the design example supports VCSsimulations only.
1. Turn on Example Design ➤ Files Types Generated ➤ Simulation.
2. Change the directory to <simulation design example>/simulation/quartus.
3. Run these two commands:
quartus_ipgenerate --run_default_mode_op oran_ed -c oran_ed
quartus_tlg oran_ed..
4. Change the directory to <simulation design example>/simulation/setup_scripts.
5. Run this command: ip-setup-simulation --use-quartus-top-names --quartus-project=../quartus/oran_ed.qpf.
6. Change the directory to <simulation design example>/simulation/setup_scripts/synopsys/vcs.
7. Run this command: sh run_vcs.sh.
2.2.2. Enabling Dynamic Reconfiguation to the Ethernet IP
By default, the dynamic reconfiguration is disabled in the O-RAN IP design example.
1. Look for the following line in the test_wrapper.sv from the generated<design_example_path>/simulation/testbench directory:
parameter ETHERNET_DR_EN = 0,
2. Change the value from 0 to 1:
parameter ETHERNET_DR_EN = 1
3. Rerun the simulation using the same generated example design directory.
2.2.3. O-RAN IP Design Example Testbench
The generated simulation testbench is dynamic and has the same configuration as theIP.
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
Send Feedback O-RAN Intel® FPGA IP Design Example User Guide
15
Figure 8. Testbench Block Diagram
Test Wrapper Device Under Test
External TrafficGenerator
External TrafficChecker
O-RAN TrafficGenerator
eCPRI IP Ethernet IP
O-RAN TrafficChecker
O-RAN IP
2.3. Operating the O-RAN IP Design Example
After you download the design example .sof file to an FPGA:
1. For Intel Stratix 10 and Intel Agilex E-tile designs, program thenios_system.elf software into the FPGA. Refer to Generating and Downloadingthe Programming File.
2. Change the directory to <variation name>/synthesis/quartus/hardware_test/ and find the relevant system console script: .
• oran_agilex.tcl for Intel Agilex E-tile designs.
• oran_a10.tcl for Intel Arria 10 designs
• oran_s10.tcl for Intel Stratix 10 designs
3. For E-tile, you must perform either an internal or external loopback commandonce first after programming the SOF file for proper transceiver calibration.
4. Change the TEST_MODE variable value in flow.c for the testing condition:
• 0 - for simulation only, serial loopback enable
• 1 - serial loopback enable
• 2 - serial loopback + calibration
• 3 - calibration only
Whenever you change flow.c, recompile and regenerate the Nios II software,then reprogram the design into the FPGA before reprogramming the Nios IIsoftware application.
5. Test the design operation through the commands supported in the system consolescript. The system console script provides useful commands for reading statisticsand features enabling in the design.
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
16
Table 3. System Console Script Commands
Command Description
link_init_int_lpbk Enable transmitter to receiver internal serial loopback within the transceiver and performthe transceiver calibration flow. Ethernet Hard Intel FPGA IP (E-tile) only.
link_init_ext_lpbk Enable transmitter to receiver external loopback and perform the transceiver calibrationflow. Ethernet Hard Intel FPGA IP (E-tile) only.
loop_off Disable transmitter to receiver internal serial loopback. 25G Ethernet Intel Stratix 10 FPGAIP (H-tile) and Low Latency Ethernet 10G MAC IP (Intel Arria 10) only.
loop_on Enable transmitter to receiver internal serial loopback. 25G Ethernet Intel Stratix 10 FPGAIP (H-tile) and Low Latency Ethernet 10G MAC IP (Intel Arria 10) only.
dr_25g_to_10g_etile Switch the data rate of the Ethernet MAC from 25G to 10G. Use for E-tile devices.
dr_10g_to_25g_etile Switch the data rate of the Ethernet MAC from 10G to 25G. Use for E-tile devices.
traffic_gen_enable Resets the entire design system, enables the traffic generator and checker.
chkmac_stats Displays the statistics for Ethernet MAC.
ext_continuous_mode_en Resets the entire design system, enables the traffic generator to generate continuous trafficpackets.
dr_25g_to_10g_htile Switch the data rate of the Ethernet MAC from 25G to 10G. Use for H-tile device.
dr_10g_to_25g_htile Switch the data rate of the Ethernet MAC from 10G to 25G. Use for H-tile device.
traffic_gen_disable Disables the traffic generators and checkers, resets the entire design system.
read_test_statistics Displays the error statistics for traffic generators and checkers.
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
Send Feedback O-RAN Intel® FPGA IP Design Example User Guide
17
Figure 9. System Console Printout (Number of channels = 1)
Channel 0 EXT PTP TX SOP Count: 128Channel 0 EXT PTP TX EOP Count: 128Channel 0 EXT MISC TX SOP Count: 4678620Channel 0 EXT MISC TX EOP Count: 4692270Channel 0 EXT RX SOP Count: 4707383Channel 0 EXT RX EOP Count: 4721099Channel 0 EXT Checker Errors: 0Channel 0 EXT Checker Error Counts: 0Channel 0 EXT PTP Fingerprint Errors: 0Channel 0 EXT PTP Fingerprint Error Counts: 0Channel 0 TX C SOP Count: 31307046Channel 0 TX C EOP Count: 31393627Channel 0 RX C SOP Count: 31483538Channel 0 RX C EOP Count: 31612072Channel 0 C Checker Errors: 0Channel 0 C Checker Error Counts: 0Channel 0 TX U SOP Count: 17907031Channel 0 TX U EOP Count: 17956870Channel 0 RX U SOP Count: 18006336Channel 0 RX U EOP Count: 18055157Channel 0 U Checker Errors: 0Channel 0 U Checker Error Counts: 0
========================================================================================== ETHERNET MAC STATISTICS FOR Channel 0 (Rx) ==========================================================================================Fragmented Frames : 0 Jabbered Frames : 0 Right Size with FCS Err Frames : 0 Multicast data Err Frames : 0 Broadcast data Err Frames : 0 Unicast data Err Frames : 0 64 Byte Frames : 128 65 - 127 Byte Frames : 50812181 128 - 255 Byte Frames : 5081233 256 - 511 Byte Frames : 0 512 - 1023 Byte Frames : 0 1024 - 1518 Byte Frames : 0 1519 - MAX Byte Frames : 0 > MAX Byte Frames : 0 Multicast data OK Frame : 55893542 Broadcast data OK Frame : 0 Unicast data OK Frames : 0 Multicast Control Frames : 0 Broadcast Control Frames : 0 Unicast Control Frames : 0 Pause Control Frames : 0 Payload Octets OK : 3847414692 Frame Octets OK : 4873823428 Rx Maximum Frame Length : 1518 Any Size with FCS Err Frame : 0 Multicast control Err Frame : 0 Broadcast control Err Frame : 0 Unicast control Err Frames : 0 Pause control Err Frames : 0 Rx Frame Starts : 55893544
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
18
Figure 10. System Console (25G to 10G DR E-tile)
Initiate Dynamic Reconfiguration for Ethernet 25G -> 10G
DR Successful 25G -> 10G
RX PHY Register Access: Checking Clock Frequencies (KHz)
TXCLK :16114 (KHZ)RXCLK :16113 (KHZ) RX PHY Status Polling
Rx Frequency Lock Status 0x0000000f
Mac Clock in OK Condition? 0x00000001
Rx Frame Error ? 0x00000000
Rx PHY Fully Aligned? 0x00000001
Polling RX PHY Channel 0
RX PHY Channel 0 is up and running!
Figure 11. System Console Printout (25G to 10G DR H-tile)
Initiate Dynamic Reconfiguration for Ethernet 25G -> 10G
DR Successful 25G -> 10G
RX PHY Register Access: Checking Clock Frequencies (KHz)
TXCLK :15625 (KHZ)RXCLK :15625 (KHZ) RX PHY Status Polling
Rx Frequency Lock Status 0x00000001
Mac Clock in OK Condition? 0x00000007
Rx Frame Error ? 0x00000000
Rx PHY Fully Aligned? 0x00000001
Polling RX PHY Channel 0
RX PHY Channel 0 is up and running!
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
Send Feedback O-RAN Intel® FPGA IP Design Example User Guide
19
Figure 12. System Console Printout (10G to 25G DR E-tile)
Initiate Dynamic Reconfiguration for Ethernet 10G -> 25G
DR Successful 10G -> 25G
RX PHY Register Access: Checking Clock Frequencies (KHz)
TXCLK :40283 (KHZ)RXCLK :40283 (KHZ) RX PHY Status Polling
Rx Frequency Lock Status 0x0000000f
Mac Clock in OK Condition? 0x00000001
Rx Frame Error ? 0x00000000
Rx PHY Fully Aligned? 0x00000001
Polling RX PHY Channel 0
RX PHY Channel 0 is up and running!
Figure 13. System Console Printout (10G to 25G DR H-tile)
Initiate Dynamic Reconfiguration for Ethernet 10G -> 25G
DR Successful 10G -> 25G
RX PHY Register Access: Checking Clock Frequencies (KHz)
TXCLK :39061 (KHZ)RXCLK :39063 (KHZ) RX PHY Status Polling
Rx Frequency Lock Status 0x00000001
Mac Clock in OK Condition? 0x00000007
Rx Frame Error ? 0x00000000
Rx PHY Fully Aligned? 0x00000001
Polling RX PHY Channel 0
RX PHY Channel 0 is up and running!
2.3.1. Generating and Downloading the Programming .elf File
Generate and download the .elf file for the O-RAN IP design example to thedevelopment board. For Intel Stratix 10 designs and Intel Agilex E-tile only.
1. Change the directory to <design_example_dir>/synthesis/quartus.
2. In the Intel Quartus Prime Pro Edition software, click Open Project and open<design_example_dir>/synthesis/quartus/oran_ed.qpf.
3. Select Tools ➤ Nios II Software Build Tools for Eclipse.The Workspace Launcher window prompt appears.
4. In the workspace specify the path as <design_example_dir>/synthesis/quartus to store your Eclipse project. A new Nios II - Eclipse window appears.
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
20
5. In the Nios II - Eclipse window, right-click under Project Explorer tab, andselect New ➤ Nios II Board Support Package.
Figure 14. Project Explorer Window
6. In the Nios II Board Support Package window:
a. In the Project name parameter, specify your desired project name.
b. In the SOPC Information File name parameter, browse to the location of<design_example_dir>/synthesis/ip_components/nios_system/nios_system.sopcinfo file.
c. Click Finish.
Figure 15. Nios II Board Support Package Window
The newly created project appears under Project Explorer tab in Nios II -Eclipse window.
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
Send Feedback O-RAN Intel® FPGA IP Design Example User Guide
21
7. Right-click under Project Explorer tab and select Nios II ➤ Nios II CommandShell.
Figure 16. Project Explorer - Nios II Command Shell
8. In the Nios® II Command Shell, type the three following commands:
nios2-bsp hal bsp <design_example_dir>/synthesis/ip_components/nios_system/nios_system.sopcinfo
nios2-app-generate-makefile --app-dir app --bsp-dir bsp --elf-name nios_system.elf --src-dir <design_example_dir>/synthesis/compilation/ed_fw
make --directory=app
9. Type the following command in the Nios II Command Shell to download the .elfsoftware application to the board:
nios2-download -g -r -c 1 -d 2 --accept-bad-sysid app/nios_system.elf
2. Getting Started with the O-RAN Intel FPGA IP Design Example
UG-20317 | 2021.09.14
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
22
3. O-RAN Intel FPGA IP Design Example FunctionalDescription
Figure 17. Block Diagram
PTPIOPLL eCPRI
IOPLL
eCPRIMAC
Ethernet MAC
O-RANMAC
TestWrapper
Avalon MMAddress Decoder
Nios IISubsystem
SystemConsole
PIO IN: IP status signals check
PIO OUT: control, transmitter, receiver, and CSR reset
TOD
RSFEC ReconfigurationTransceiver Reconfiguration
Ethernet Reconfiguration
IOPLL Reconfiguration
Transmitter and receiver serial pins
clk100
Avalon memory-mapped interface
Avalon streaming interface
PIO_OUT: rate_switch_done, PIO_IN: rate_switch_en
Signal Direction Comments
clk100 Input Input clock for reconfiguration.For Intel Arria 10 designs, a 156.25 MHz oscillator on the board drives this clock.For Intel Agilex and Intel Stratix 10 designs, a 100 MHz oscillator on the boarddrives this clock.
mgmt_reset_n Input Input reset for the Nios II system.
clk_ref Input For Intel Arria 10 designs, a 322.265625 MHz clock input for the Transceiver ATXPLL and 1G/10GbE and 10GBase-KR PHY IP . Connect to pll_refclk0[0]in theTransceiver ATX PLL and rx_cdr_ref_clk_10g[0] in the 1G/10GbE and10GBase-KR PHY IP.For Intel Agilex F-tile, Intel AgilexE-tile, and Intel Stratix 10 E-tile designs,156.25 MHz clock input for the E-tile Ethernet Hard IP core. Connect toi_clk_ref[0] in the Ethernet Hard IP.
continued...
UG-20317 | 2021.09.14
Send Feedback
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of IntelCorporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Intel assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to inwriting by Intel. Intel customers are advised to obtain the latest version of device specifications before relyingon any published information and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
Signal Direction Comments
For Intel Stratix 10 H-tile designs, a 322.265625 MHz clock input for theTransceiver ATX PLL and 25G Ethernet IP. Connect to pll_refclk0[0]in theTransceiver ATX PLL and clk_ref[0] in 25G Ethernet IP.
tod_sync_sampling_clk Input For Intel Arria 10 designs, a 250 MHz clock input for TOD subsystem.
tx_serial Output Transmitter serial data. Supports up to four channels.
rx_serial Input Receiver serial data. Supports up to four channels.
O-RAN IP
The O-RAN IP receives and transmits data at the transmitter and receiver applicationinterfaces (the traffic components instantiated within the test wrapper).
eCPRI IP
The eCPRI IP receives and transmits data at the Avalon® streaming source and sinkinterfaces (from the O-RAN transmitter, and receiver transport interfaces) and theexternal source and sink interfaces (the external traffic components instantiated withinthe test wrapper). The eCPRI IP prioritizes the data for transmission to the EthernetIP.
eCPRI IOPLL
For design examples targetting Intel Stratix 10 and Intel Agilex devices only, theeCPRI IOPLL generates the clock output of 390.625 MHz to feed into the transmitterand receiver data path of the eCPRI IP, the O-RAN IP, and the traffic generator andchecker components.
PTP IOPLL
For Intel Arria 10 devices the PTP IOPLL generates the 312.5 MHz and 156.25 MHzclock inputs for the Low Latency Ethernet 10G MAC, eCPRI, O-RAN, 1G/10GbE and10GBase-KR PHY IPs.
For Intel Stratix 10 devices, the PTP IOPLL generates the latency measurement inputreference clock for the 25G Ethernet Intel FPGA IP and the sampling clock for TODsubsystem. For the 25G Ethernet Intel FPGA IP with the IEEE 1588v2 feature, Intelrecommends that you set the frequency of this clock to 156.25 MHz.
For more information, refer to the 25G Ethernet Intel Stratix 10 FPGA IP DesignExample User Guide and the Intel Stratix 10 H-Tile Transceiver PHY User Guide.
Nios II subsystem
The Nios II subsystem consists of the:
• Avalon memory-mapped bridge, which allows Avalon memory-mapped dataarbitration between traffic from the Nios II processor and the test wrapper
• A Nios II processor
• An Avalon memory-mapped address decoder
3. O-RAN Intel FPGA IP Design Example Functional Description
UG-20317 | 2021.09.14
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
24
For design examples targetting Intel Stratix 10 and Intel Agilex E-tile devices only, theNios II processor performs the data rate switching based on the output from the testwrapper's rate_switch register value. The Nios II processor programs the necessaryregister after the command from the test wrapper. Design examples targetting IntelArria 10 devices do not support data rate switching.
Ethernet IP
The design example instantiates one of the following Ethernet IP to interface with theeCPRI IP:
• Low Latency Ethernet 10G MAC IP and 1G/10GbE and 10GBase-KR PHY IP (IntelArria 10 designs)
• Ethernet Hard IP (Intel Stratix 10 E-tile and Intel Agilexdesigns)
• 25G Ethernet Stratix 10 IP (Intel Stratix 10 H-tile designs)
TOD Subsystem
The time of day (TOD) subsystem consists of two IEEE 1588 TOD modules for bothtransmitter and receiver, and one IEEE 1588 TOD synchronizer module.
System Console Access through JTAG Interface
The system console provides an interface for you to debug and monitor the status ofthe IP and the traffic generators and checkers.
Test Wrapper
The test wrapper consists of numerous traffic generators and checkers that generatedifferent types of data packets to the O-RAN IP and the eCPRI IP.
Test Wrapper O-RAN IP Data Packets
The traffic generator supports O-RAN packets to the Avalon streaming source and sinkinterfaces of the O-RAN IP with configurations for C-plane, C-plane extension, and U-plane.
Table 4. C-Plane Configurations
Parameter Description
rtcid
seqid
Transport header fixed parameter value.
dataDirection
Filterindex
Common Header fixed parameter value.
frameId Fixed initial value (configured with parameter).
subframeId Fixed initial value (configured with parameter).
slotId Fixed initial value (configured with parameter).
symbolId Fixed initial value (configured with parameter).
NumberofSections 6 for Sectiontype. 1, 2 for Sectiontype 3.
Sectiontype 1, 3.
Timeoffset Fixed parameter value.
continued...
3. O-RAN Intel FPGA IP Design Example Functional Description
UG-20317 | 2021.09.14
Send Feedback O-RAN Intel® FPGA IP Design Example User Guide
25
Parameter Description
frameStructure Fixed parameter value.
cpLength Fixed parameter value.
udCompHdr Applicable only when compression is enabled: udCompMeth = 0001 or 0011, and udIqWidth =1000 or 1100
sectionId Section header fixed parameter value.
Sectiontype Section extension.
ExtType 3 (DL precoding).
Rb Fixed parameter value.
StartPrb Fixed parameter value.
numPrb Fixed parameter value.
reMask Fixed parameter value.
numSymbol Fixed parameter value.
Ef 0 for Sectiontype 1, 1 for Sectiontype 3.
frequencyOffset Fixed parameter value.
Table 5. C-Plane Extension Configurations
Parameter Description
NumberofSections 2.
ExtType 3 (DL Precoding).
Payload Size 32 bytes (16 bytes for each section).
Table 6. U-Plane Configurations• Incremental pattern mode generation with some interpacket gaps.
• Configurable via CSR to run in either non-continuous or continuous mode.
• Transmitter and receiver packet statistic status available to access via CSR.
Parameter Description
dataDirection
Filterindex
Common header fixed parameter value.
frameId Fixed initial counter value (configured from parameter).
subframeId Fixed initial counter value (configured from parameter).
slotId Fixed initial counter value (configured from parameter).
symbolId Fixed initial counter value (configured from parameter).
udCompHdr Applicable only when compression is enabled. udCompMeth = 0001 or 0011 and udIqWidth = 1000 or1100
sectionId Section header fixed parameter value.
Rb Fixed parameter value.
StartPrb Fixed parameter value.
numPrb Fixed parameter value.
3. O-RAN Intel FPGA IP Design Example Functional Description
UG-20317 | 2021.09.14
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
26
Table 7. Supported C and U-plane Traffic Configurations
The table shows specific configuration settings supported in the design example. You may modify theseparameters in the generated oran_ed_top.sv and oran_tb.sv files to run the design example successfully.
ENABLE_COMPRESSION(1) (3)
ENABLE_CPLANE(2)
ENABLE_UPLANE udCompMeth(3)
udIqWidth(3) C_Sectiontype(4)
1 1 0 0,1,3 8,12,16 1,3
1 1 1 1,3 8,12 1,3
0 0 1 0 16 1,3
0 1 1 0 16 1,3
0 1 0 0 16 1,3
Test Wrapper ECPRI IP IP Data Packets
For PTP synchronization packets and non-PTP miscellaneous packets to the externalsource and sink interfaces:
• External PTP packets:
— Static Ethernet header generation with predefined parameters: EtherType =0x88F7, or Message Type = Opcode 0 (sync), or PTP version = 0
— Predefined pattern mode generation with interpacket gap of two cycles andpayload size of 57 bytes for each packet.
— 128 packets generate every second.
— CSR configurable to run either non-continuous or continuous.
— Transmitter or receiver packet statistic status available via CSR.
(1) This parameter setting must match Enable companding in the O-RAN IP GUI.
(2) These parameter settings are only applicable when you turn on Enable C-plane in the O-RANIP GUI. When you turn off Enable C-Plane, you must set the following configuration:• ENABLE_CPLANE = 0
(3) These parameter settings are only applicable when you turn on Enable companding in theO-RAN IP GUI. when you turn off Enable companding, you must set the followingconfigurations:• ENABLE_COMPRESSION = 0• udCompMeth = 0• udIqWidth = 16
(4) The design example ignores the C_Sectiontype parameter when yoiu turn off Enable C-plane in the O-RAN IP GUI• For C_Sectiontype = 1, the example design only supports C_NumberofSections = 6.• For C_Sectiontype = 3, the example design only supports C_NumberofSections = 2..
3. O-RAN Intel FPGA IP Design Example Functional Description
UG-20317 | 2021.09.14
Send Feedback O-RAN Intel® FPGA IP Design Example User Guide
27
• External non-PTP miscellaneous packets:
— Static Ethernet header generation with predefined parameters: EtherType =0x8100 (non-PTP)
— PRBS pattern mode generation with interpacket gap of two cycles and payloadsize of 128 bytes for each packet.
— CSR configurable to run either non-continuous or continuous.
— Transmitter or receiver packet statistic status available via CSR.
Design Example Address Mapping
Table 8. JTAG to Avalon Memory-mapped Bridge Address Mapping
Address Target
0x20100000 – 0x201fffff (5) IOPLL reconfiguration Avalon memory-mapped register.
0x20200000 – 0x203fffff Ethernet MAC Avalon memory-mapped register.
0x20400000 – 0x205fffff Ethernet MAC Native PHY Avalon memory-mapped register..
0x20600000 – 0x207fffff (5) Native PHY RSFEC Avalon memory-mapped register.
0x40000000 – 0x5fffffff eCPRI IP Avalon memory-mapped register.
0x80000000 – 0x9fffffff Design example test generator and verifier Avalon memory-mapped register.
Table 9. Address mapping when accessing through the Nios II processorOnly available for Intel Stratix 10 designs.
Address Target
0x00100000 – 0x001fffff IOPLL Re-configuration Avalon memory-mapped register
0x00200000 – 0x003fffff Ethernet MAC Avalon memory-mapped register
0x00400000 – 0x005fffff Ethernet MAC Native PHY Avalon memory-mapped register.
0x00600000 – 0x007fffff Native PHY Reed-Solomon FEC Avalon memory-mapped register.
Access the Ethernet MAC and the Ethernet MAC Native PHY Avalon memory-mappedregister using word offset instead of byte offset.
For more information on the Ethernet MAC, Ethernet MAC Native PHY Avalon memory-mapped, and eCPRI IP Avalon memory-mapped registers, refer to the respective userguides.
Table 10. Test generator and verifier Avalon memory-mapped register
Word Offset Description Default Attribute
0x0 Start send data• Bit 1: PTP, non-PTP type• Bit 0: O-RAN C-plane, U-plane, C-plane extension
0x0 RW
0x1 Continuous packet enable 0x0 RW
0x2 Clear error 0x0 RW
continued...
(5) Only available for Intel Stratix 10 and Intel Agilex E-tile designs.
3. O-RAN Intel FPGA IP Design Example Functional Description
UG-20317 | 2021.09.14
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
28
Word Offset Description Default Attribute
0x3 (6) Rate switch• Bit 7: tile
— 1’b0: H-Tile— 1’b1: E-Tile
• Bit 6:4: Ethernet rate— 3’b0: 25G to 10G— 3’b1: 10G to 25G
• Bit 0: switch rate enableYou must set bit 0 and poll until bit 0 is clear for rate switching
E-tile:0x80
Non E-tile:0x0
RW
0x4 (6) Rate switch done• Bit 1: rate switch done
0x0 RO
0x5 System configuration status• Bit 31: System ready• Bit 30-13: Reserved• Bit 12-5: UDCOMPPARAM• Bit 4: COMP_EN• Bit 3: EXT_PACKET_EN• Bit 2: CPLANE_EXT_EN• Bit 1: CPLANE_EN• Bit 0: UPLANE_EN
0x0 RO
0x6 - 0x1F Reserved 0x0 RO
0x20 eCPRI error interrupt 0x0 RO
0x21 External packets error 0x0 RO
0x22 External PTP packets transmitter SOP count 0x0 RO
0x23 External PTP packets transmitter EOP count 0x0 RO
0x24 External misc packets transmitter SOP count 0x0 RO
0x25 External misc packets transmitter EOP count 0x0 RO
0x26 External receiver packets SOP count 0x0 RO
0x27 External receiver packets EOP count 0x0 RO
0x28 External error count 0x0 RO
0x29 – 0x2C Reserved 0x0 RO
0x2D External PTP timestamp fingerprint error Count 0x0 RO
0x2E External PTP timestamp fingerprint error 0x0 RO
0x2F External receiver error status 0x0 RO
0x30 – 0x53 Reserved 0x0 RO
0x54 O-RAN error interrupt 0x0 RO
0x55 Avalon streaming receiver U-plane error status• Bit 0: Avalon streaming receiver U-plane error status
0x0 RO
0x56 Avalon streaming receiver C-plane error status• Bit 0: Avalon streaming receiver C-plane error status
0x0 RO
0x57 Avalon streaming receiver C-plane extension error status 0x0 RO
continued...
(6) Only available for Intel Stratix 10 and Intel Agilex E-tile designs.
3. O-RAN Intel FPGA IP Design Example Functional Description
UG-20317 | 2021.09.14
Send Feedback O-RAN Intel® FPGA IP Design Example User Guide
29
Word Offset Description Default Attribute
Bit 0: Avalon streaming receiverx C-plane extension error status
0x58 C-plane Checker Errors 0x0 RO
0x59 C-plane Checker Errors 0x0 RO
0x60 Transmitter C-plane SOP Count 0x0 RO
0x61 Transmitter C-plane EOP Count 0x0 RO
0x62 Receiver C-plane SOP Count 0x0 RO
0x63 Receiver C-plane EOP Count 0x0 RO
0x64 Total C-plane Error Count 0x0 RO
0x65 C-plane Extension Checker Errors 0x0 RO
0x66 Transmitter C-plane extension SOP count 0x0 RO
0x67 Transmitter C-plane extension EOP Count 0x0 RO
0x68 Receiver C-plane extension SOP Count 0x0 RO
0x69 Receiver C-plane extension EOP count 0x0 RO
0x70 Transmitter C-plane extension error count 0x0 RO
0x71 Transmitter U-plane SOP count 0x0 RO
0x72 Transmitter U-plane EOP count 0x0 RO
0x73 U-plane checker errors 0x0 RO
0x74 Receiver U-plane SOP count 0x0 RO
0x75 Receiver U-plane EOP count 0x0 RO
0x76 Total U-plane error count 0x0 RO
Related Information
• 25G Ethernet Intel Arria 10 FPGA IP User Guide
• 25G Ethernet Intel Stratix 10 FPGA IP User Guide
• eCPRI Intel FPGA IP User Guide
• IOPLL Intel FPGA IP Core User Guide
• L- and H-Tile Transceiver PHY User Guide
3. O-RAN Intel FPGA IP Design Example Functional Description
UG-20317 | 2021.09.14
O-RAN Intel® FPGA IP Design Example User Guide Send Feedback
30
4. O-RAN IP Design Example User Guide ArchivesIf the table does not list an IP version, the user guide for the previous IP versionapplies.
Table 11. O-RAN IP Intel FPGA IP Design Example User Guide Archive
Intel Quartus PrimeVersion
User Guide
21.1 O-RAN Intel FPGA IP Design Example User Guide
20.3 O-RAN Intel FPGA IP Design Example User Guide
UG-20317 | 2021.09.14
Send Feedback
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of IntelCorporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Intel assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to inwriting by Intel. Intel customers are advised to obtain the latest version of device specifications before relyingon any published information and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
5. Document Revision History for the O-RAN Intel FPGA IPDesign Example User Guide
Document Version Intel QuartusPrime Version
IP Version Changes
2021.09.14 21.2 1.5.1 • Added new Number of channels parameter.• Added new System Console Printout figures.• Changed block diagram• Changed clk_ref description• Replaced Test generator and verifier Avalon
memory-mapped register table
2021.06.30 21.1 1.4.0 Added support for Intel Agilex 10 devices.
2020.11.30 20.3 1.1.0 Initial release.
UG-20317 | 2021.09.14
Send Feedback
Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of IntelCorporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to currentspecifications in accordance with Intel's standard warranty, but reserves the right to make changes to anyproducts and services at any time without notice. Intel assumes no responsibility or liability arising out of theapplication or use of any information, product, or service described herein except as expressly agreed to inwriting by Intel. Intel customers are advised to obtain the latest version of device specifications before relyingon any published information and before placing orders for products or services.*Other names and brands may be claimed as the property of others.
ISO9001:2015Registered
