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8/10/2019 NuMicro Product Brief
1/32
NuMicro
M058/M0516 Product Brief
ARM Cortex
-M0
32-BIT MICROCONTROLLER
Publication Release Date: Mar. 19, 2012
- 1 - Revision V1.01
NuMicro
Family
M058/M0516BN Product Brief
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NuMicro
M058/M0516 Product Brief
Publication Release Date: Mar. 19, 2012
- 2 - Revision V1.01
TABLE OF CONTENTS
1 GENERAL DESCRIPTION 5
2 FEATURES 6
3 BLOCK DIAGRAM 11
4 SELECTION TABLE 12
5 PIN CONFIGURATION 13
5.1 QFN 33 pin 13
5.2 LQFP 48 pin 14
6 TYPICAL APPLICATION CIRCUIT 15
7 ELECTRICAL CHARACTERISTICS 16
7.1 Absolute Maximum Ratings 16
7.2 DC Electrical Characteristics 17
7.3 AC Electrical Characteristics 21
7.3.1 External Crystal 21
7.3.2 External Oscillator 21
7.3.3 Typical Crystal Application Circuits 22
7.3.4 Internal 22.1184 MHz RC Oscillator 23
7.3.5 Internal 10kHz RC Oscillator 23
7.4 Analog Characteristics 24
7.4.1 Specification of 12-bit SARADC 24
7.4.2 Specification of LDO & Power management 25
7.4.3 Specification of Low Voltage Reset 26
7.4.4 Specification of Brown-Out Detector 26
7.4.5 Specification of Power-On Reset (5V) 26
7.4.6 Specification of Temperature Sensor 27
7.4.7 Specification of Comparator 27
7.5 Flash DC Electrical Characteristics 28
8 PACKAGE DIMENSIONS 29
8.1 LQFP-48 (7x7x1.4mm2Footprint 2.0mm) 29
8.2 QFN-33 (5X5 mm2, Thickness 0.8mm, Pitch 0.5 mm) 30
9 REVISION HISTORY 31
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M058/M0516 Product Brief
Publication Release Date: Mar. 19, 2012
- 3 - Revision V1.01
LIST OF FIGURES
Figure 3-1 NuMicroM051 Series Block Diagram ........................................................................ 11
Figure 4-1 NuMicroNaming Rule ................................................................................................ 12
Figure 5-1 NuMicroM051 Series QFN33 Pin Diagram ............................................................... 13
Figure 5-2 NuMicroM051 Series LQFP-48 Pin Diagram ........................................................... 14
Figure 7-1 Typical Crystal Application Circuit ................................................................................ 22
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M058/M0516 Product Brief
Publication Release Date: Mar. 19, 2012
- 4 - Revision V1.01
LIST OF TABLES
Table 4-1 NuMicroM051 Series Product Selection Guide ......................................................... 12
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M058/M0516 Product Brief
Publication Release Date: Mar. 19, 2012
- 6 - Revision V1.01
2 FEATURES
Core
ARMCortex
-M0 core runs up to 50 MHz.
One 24-bit system timer.
Supports low power sleep-mode.
A single-cycle 32-bit hardware multiplier.
NVIC for the 32 interrupt inputs, each with 4-levels of priority.
Supports Serial Wire Debug (SWD) interface and 2 watchpoints/4 breakpoints.
Built-in LDO for Wide Operating Voltage Range: 2.5V to 5.5V
Memory
32KB/64KB Flash memory for program memory (APROM)
4KB Flash memory for data memory (DataFlash)
4KB Flash memory for loader (LDROM)
4KB SRAM for internal scratch-pad RAM (SRAM)
Clock Control
Programmable system clock source
4~24 MHz external crystal input
22.1184 MHz internal oscillator (trimmed to 3% accuracy)
10 kHz low-power oscillator for Watchdog Timer and wake-up in sleep mode
PLL allows CPU operation up to the maximum 50MHz
I/O Port
Up to 40 general-purpose I/O (GPIO) pins for LQFP-48 package
Four I/O modes:
Quasi bi-direction
Push-Pull output
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M058/M0516 Product Brief
Publication Release Date: Mar. 19, 2012
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Open-Drain output
Input only with high impendence
TTL/Schmitt trigger input selectable
I/O pin can be configured as interrupt source with edge/level setting
Supports high driver and high sink IO mode
Timer
Provides four channel 32-bit timers, one 8-bit pre-scale counter with 24-bit up-timer foreach timer.
Independent clock source for each timer.
24-bit timer value is readable through TDR (Timer Data Register)
Provides one-shot, periodic and toggle operation modes.
Provide event counter function.
Provide external capture/reset counter function equivalent to 8051 Timer2.
Watchdog Timer
Multiple clock sources
Supports wake up from power down or sleep mode
Interrupt or reset selectable on watchdog time-out
PWM
Built-in up to four 16-bit PWM generators; providing eight PWM outputs or fourcomplementary paired PWM outputs
Individual clock source, clock divider, 8-bit pre-scalar and dead-zone generator for eachPWM generator
PWM interrupt synchronized to PWM period
16-bit digital Capture timers (shared with PWM timers) with rising/falling capture inputs
Supports capture interrupt
UART
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Publication Release Date: Mar. 19, 2012
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Up to two sets of UART device
Programmable baud-rate generator
Buffered receiver and transmitter, each with 15 bytes FIFO
Optional flow control function (CTS and RTS)
Supports IrDA(SIR) function
Supports RS485 function
Supports LIN function
SPI
Up to two sets of SPI device.
Supports master/slave mode
Full duplex synchronous serial data transfer
Provide 3 wire function
Variable length of transfer data from 1 to 32 bits
MSB or LSB first data transfer
Rx latching data can be either at rising edge or at falling edge of serial clock
Tx sending data can be either at rising edge or at falling edge of serial clock
Supports Byte suspend mode in 32-bit transmission
I2C
Supports master/slave mode
Bidirectional data transfer between masters and slaves
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial dataon the bus
Serial clock synchronization allows devices with different bit rates to communicate viaone serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend andresume serial transfer.
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Publication Release Date: Mar. 19, 2012
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Programmable clocks allow versatile rate control.
Supports multiple address recognition (four slave address with mask option)
ADC
12-bit SAR ADC with 760k SPS
Up to 8-ch single-ended input or 4-ch differential input
Supports single mode/burst mode/single-cycle scan mode/continuous scan mode
Supports 2complement/un-signed format in differential mode conversion result
Each channel with an individual result register
Supports conversion value monitoring (or comparison) for threshold voltage detection
Conversion can be started either by software trigger or external pin trigger
Analog Comparator
Up to 2 comparator analog modules
External input or internal band gap voltage selectable at negative node
Interrupt when compare result change
Power down wake up
EBI (External Bus Interface) for external memory-mapped device access
Accessible space: 64KB in 8-bit mode or 128KB in 16-bit mode
Supports 8-bit/16-bit data width
Supports byte-write in 16-bit data width
In-System Programming (ISP) and In-Circuit Programming (ICP)
One built-in temperature sensor with 1resolution
Brown-Out Detector
With 4 levels: 4.3V/3.7V/2.7V/2.2V
Supports Brown-Out interrupt and reset option
96-bit unique ID
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Publication Release Date: Mar. 19, 2012
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LVR (Low Voltage Reset)
Threshold voltage levels: 2.0V
Operating Temperature: -40~85
Packages:
Green package (RoHS)
48-pin LQFP, 33-pin QFN
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Publication Release Date: Mar. 19, 2012
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3 BLOCK DIAGRAM
Cortex-M050 MHz
CLK_CTL
GPIOP0~P4
ADCWatch Dog Timer
I2C
SPI 0/1
UART 0/1
PWM 0~7
Timer 0/1
10K OSC
PLL
22M OSC
EXT. 4~24MXTAL
LDO2.5 ~ 5.5V
ADC8ch/12bitSARADC760K SPS
Timer 2/3EBI
AD[15:0]
nCS
nRD
nWR
mclk
ALE
PAD Control
POR
BOD
LVR
64KB(M0516)
32KB(M058)
APROM
LDROM ISP 4KB
CONFIG
DATAFLASH 4KB
SRAM4KB
AnalogComparator
nWRHnWRL
Figure 3-1 NuMicroM051 Series Block Diagram
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M058/M0516 Product Brief
Publication Release Date: Mar. 19, 2012
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4 SELECTION TABLENuMicro M051 Series Selection Guide
Part number APROM RAMDataFlash
LDROM I/O TimerConnectivity
COMP PWM ADC EBIISPICP
PackageUART SPI I2C
M058LBN 32KB 4KB 4KB 4KB 40 4x32-bit 2 2 1 2 8 8X12-bit v v LQFP48
M058ZBN 32KB 4KB 4KB 4KB 24 4x32-bit 2 1 1 2 5 8X12-bit v QFN33
M0516LBN 64KB 4KB 4KB 4KB 40 4x32-bit 2 2 1 2 8 8X12-bit v v LQFP48
M0516ZBN 64KB 4KB 4KB 4KB 24 4x32-bit 2 1 1 2 5 8X12-bit v QFN33
Table 4-1 NuMicroM051 Series Product Selection Guide
M05X - X X X
ARM Cortex M0
L : LQFP 48
Z : QFN 33
N : - 40 ~ +85
E : - 40 ~+105
C : - 40 ~+125
M0 - X X X
CPU core
58 : 32K Flash ROM
516 : 64K Flash ROM
N : - 40 ~ +85
E : - 40 ~+105
C : - 40 ~+125
Reserved
Part Number Temperature
Package
Figure 4-1 NuMicroNaming Rule
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5 PIN CONFIGURATION
5.1 QFN 33 pin
CPP0,AIN5,P1.5
AVSS
CPN1,RXD,P3.0
CPP1,TXD,P3.1
SDA,T0,P3.4
SCL,T1,P3.5
XTAL2
XTAL1
VSS
LDO_CAP
P2.2,PWM2
P2.3,PWM3
P2.4,PWM4
P3.6,CKO,CPO0
P0.7,SCLK1
P4.6,ICE_CLK
P0.6,MISO_1
P0.5,MOSI_1
P0.4,SPISS1
P2.5,PWM5
P2.6,PWM6,CPO1
P4.7,ICE_DAT
TXD1,AIN3,P1.3
RXD1,AIN2,P1.2
CPN0,AIN4,P1.4
AIN0,T2,P1.0
TXD1,CTS1,P0.0
AVDD
RXD1,RTS1,P0.1
VDD
33VSS
32
1 24
RST
QFN 33 Pin
31 30 29 28 27 26 25
23
22
21
20
19
18
17
109 11 12 13 14 15 16
2
3
4
5
6
7
8
Toptransparentview
T0EX,STADC,INT0,P3.2
Figure 5-1 NuMicroM051 Series QFN33 Pin Diagram
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M058/M0516 Product Brief
Publication Release Date: Mar. 19, 2012
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5.2 LQFP 48 pin
2
44
1
4
3
6
5
8
7
10
9
11
48
42
41
40
39
38
37
32
33
30
31
28
29
26
27
25
13
14
15
16
18
19
20
21
22
12
17
23
24
34
35
36
46
47
43
45
PWM3,P4.3
P4.0,PWM0,T2EX
48 pin LQFP
PWM2,P4.2
MISO_0,AIN6,P1.6
CPP0,MOSI_0,AIN5,P1.5
RST
SPICLK0,AIN7,P1.7
AVSS
CPN1,RXD,P3.0
CPP1,TXD,P3.1
SDA,T0,P3.4
SCL,T1,P3.5
T0EX,STADC,INT0,P3.2
T1EX,MCLK,INT1,P3.3
XTAL2
XTAL1
VSS
P2.1,AD9,PWM1
LDO_CAP
P2.2,AD10,PWM2
P2.3,AD11,PWM3
P2.4,AD12,PWM4
P2.0,AD8,PWM0
P3.7,RD
P3.6,WR,CKO,CPO0
P4.5,ALE
P0.7,AD7,SPICLK1
P4.6,ICE_CLK
P0.6,AD6,MISO_1
P0.5,AD5,MOSI_1
P0.4,AD4,SPISS1
P2.5,AD13,PWM5
P2.6,AD14,PWM6,CPO1
P2.7,AD15,PWM7
P4.4,/CS
P4.7,ICE_DAT
P4.1,PWM1,T3EX
TXD1,AIN3,P1.3
RXD1,AIN2,P1.2
CPN0,SPISS0,AIN4,P1.4
nWRH,T3,AIN1,P1.1
nWRL,T2,AIN0,P1.0
TXD1,CTS1,AD0,P0.0
AVDD
RXD1,RTS1,AD1,P0.1
TXD,CTS0,AD2,P0.2
RXD,RTS0,AD3,P0.3
VDD
Figure 5-2 NuMicroM051 Series LQFP-48 Pin Diagram
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6 TYPICAL APPLICATION CIRCUIT
AA12
RI2C14.7K
AD0
RI2C24.7K
AD1AD2
DVDD
RXD0
TXD0
DVDD
I2C-EEPROM
24LC64
UI2C1
SOIC8\1.27\5.6MM
GND4 A23 A12 A01
SDA5SCL6WP7VCC8
I2C
AD3
EEPROM
ADDRESS:0HCB90.1uF
DVDD
MET22MET23
DVDD
DVDD
MISO_1nSS1
P32
USPI1
W25X16VSSIG
SOIC-8P
CS#1
DO2
WP#3
GND4
DI5CLK6HOLD#7VCC8
SPI
DVDD
RSPI14.7K
RSPI24.7K
CB70.1uF
SCLK1MOSI_1
SDASCL
SDA
AD4
SCL
nWR
AD5
AD12
AD6
AD11AD10
AD13
AD7
AD14
nTICERST
AVDD
AD5AD6
P40
ALE
AD7
AD9AD8
AD3
UART_TXD
RXD0
TXD1RXD1TXD0
S1
SW DIP-4SWDIP8
1234
8765
UART_RXD
AD4
nRD
AD5
EBI
D12MO
AD6
L1 FB
AD7
CB30.1uF
CB40.1uF
nWR
AVDD
DVDD
D12MI
DVSS
CB80.1uF
DVSS
U4
M052_54LQFP 48
M052_LQFP_48
AIN1/T2/P1.1
44
AIN2/RXD1/P1.2
45
AIN3/TXD1/P1.3
46
AIN3/SS0/P1.4
47
P4.2
48
MOSI_0/AIN5/P1.51
MISO_0/AIN6/P1.62
SCLK0/AIN7/P1.73
VSS
17
LDO
_CAP
18
P2.0
/AD8/PWM0
19
P2.1
/AD9/PWM1
20
P2.2
/AD10/PWM2
21
P2.3
/AD11/PWM3
22
P2.4
/AD12/PWM4
23
P4.0
24
P2.6/AD14/PWM626
P4.6/ICE_CLK30P4.7/ICE_DAT31P0.7/AD7/SCLK132P0.6/AD6/MISO_133P0.5/AD5/MOSI_134P0.4/AD4/SS135P4.136
P0.3
/AD3/RT
S0
37
P0.2
/AD2/CT
S0
38
P0.1
/AD1/RT
S1
39
RST4
RXD/P3.05
AVSS6
MCLK/INT1/P3.39
TXD/P3.17
INT0/P3.28
SDA/T0/P3.410
SCL/T1/P3.511
P4.312
P3.6
/WR/CKO
13
P4.5/ALE29
P4.4/CS28
AIN0/T2/P1.0
43
AVDD
42
VDD
41
P0.0
/AD0/CT
S1
40
P3.7
/RD
14
XTAL1
16
XTAL2
15
P2.5/AD13/PWM525
P2.7/AD15/PWM727
MOSI_0
AA15
AVSS
MISO_0SCLK0
AA14
AVSS
nTICERST
AA13
DVSS
P33
P41
L2 FB
AA5
AD4
TICEDAT
ADC Input
TICECLKALE
AA6
nCS
CB50.1uFDVDDDVDDDVSSCB60.1uF DVSS
AD15
U3
BS616LV4017EG70(TSOP-44)
A41
A32
A23
A14
A05
CS6
I/O07
I/O18
I/O29
I/O310
VCC11
VSS12
I/O413
I/O514
I/O615
I/O716
WE17
A1718
A1619
A1520
A1421
A1322
NC28
A827
A1223A1124
A926
A1025
I/O829I/O930I/O1031I/O1132VCC33VSS34I/O1235I/O1336I/O1437I/O1538LB39UB40OE41
A544
A643
A742 AA7
AD3
CB10.1uF
AD2nRD
Title
Size Document Number Rev
Date: Sheet of
Application.dsn 1.0
M052_54 Application Circuit
1 1Thursday, August 19, 2010
C510uF
TANT-B
AD1AD0
DVDD
AD12AD11AD10AD9AD8
ALE
AD15AD14AD13
CB20.1 uF
AA10AA9AA8
P42
U274F373
D03
D14
D27
D38
D413
D514
D617
D718
OE1 LE
11
Q02
Q15
Q26
Q39
Q412
Q515
Q616
Q719
VCC
20
GND
10
AA13AA12AA11
AA15AA14
AD15
nSS0
AD14
TXD1
AD13
RXD1
AD12
P11AA4
AD11
AA0
AA3
P43
AA1
AD10
AA2
C3820pF
AA2
AD9
AA3
AA1
AA4
AD8
AA0
AA5
nCS
U174F373
D03
D14
D27
D38
D413
D514
D617
D718
OE1 LE
11
Q02
Q15
Q26
Q39
Q412
Q515
Q616
Q719
VCC
20
GND
10
AA6
ADC
AA8
AD0
AA7
AD1
ICE Interface
C1
10uF/10V
TANT-A
DVDD
AA9
R1
10K
Reset Circuit
AD2
X112MHz
XTAL3-1C420p
D12MO
C220p
D12MI
Crystal
AA10
CON1
1X2HEADER
11
22
UART_TXDUART_RXD
UARTDVDD
VDD NET4
NET5NET40
NET3
NET9NET8
NET6NET7
VSS
R4 33NET10
R6 33
NET12NET13NET11
U5MAX232A
SOP16/150
C1+1
V+2
C1-3
C2+4
C2-5
V-6
T2OUT7
R2IN8
R2OUT9T2IN10T1IN11R1OUT12R1IN13T1OUT14GND15VCC16
AA11
C71uFTANT-AC6
1uFTANT-A
C91uFTANT-A
C8 1uFTANT-A
P1
DB9-M()DB9L-HP
594837261
10
11
R333
R533
ICEJP1
HEADER 5X2HEADER5X2
1 23 45 67 89 10
nTICERSTTICECLKTICEDAT
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7 ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
SYMBOL PARAMETER MIN MAX UNIT
DC Power Supply VDDVSS -0.3 +7.0 V
Input Voltage VIN VSS-0.3 VDD+0.3 V
Oscillator Frequency 1/tCLCL 4 24 MHz
Operating Temperature TA -40 +85 C
Storage Temperature TST -55 +150 C
Maximum Current into VDD - 120 mA
Maximum Current out of VSS 120 mA
Maximum Current sunk by a I/O pin 35 mA
Maximum Current sourced by a I/Opin
35 mA
Maximum Current sunk by total I/Opins
100 mA
Maximum Current sourced by totalI/O pins
100 mA
Note:Exposure to conditions beyond those listed under absolute maximum ratings may adversely affects the lift and reliability of the device.
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7.2 DC Electrical Characteristics
(VDD-VSS=2.5~5.5V, TA = 25C, FOSC= 50 MHz unless otherwise specified.)
PARAMETER SYM.
SPECIFICATION
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Operation voltage VDD 2.5 5.5 V VDD=2.5V ~ 5.5V up to 50 MHz
LDO Output Voltage VLDO 1.7 1.8 1.9 V VDD2.5V
Band Gap Analog Input VBG -5% 1.20 +5% V VDD=2.5V ~ 5.5V
Analog OperatingVoltage
AVDD 0 VDD V
Analog ReferenceVoltage Vref 0 AVDD V
Operating Current
Normal Run Mode
@ 50 MHz
IDD1 20.6 mAVDD= 5.5V@50MHz,
enable all IP and PLL, XTAL=12MHz
IDD2 14.4 mA
VDD=5.5V@50MHz,
disable all IP and enable PLL,XTAL=12MHz
IDD3 18.9 mAVDD= 3.3V@50MHz,
enable all IP and PLL, XTAL=12MHz
IDD4 12.8 mA
VDD= 3.3V@50MHz,
disable all IP and enable PLL,XTAL=12MHz
Operating Current
Normal Run Mode
@ 22Mhz
IDD5 6.2 mA
VDD= 5.5V@22MHz,
enable all IP and IRC22M,disable PLL
IDD6 3.4 mA
VDD=5.5V@22MHz,
disable all IP and enable IRC22M,
disable PLL
IDD7 6.1 mA
VDD= 3.3V@22MHz,
enable all IP and IRC22M,
disable PLL
IDD8 3.4 mA
VDD= 3.3V@22MHz,
disable all IP and enable IRC22M,
disable PLL
Operating Current
Normal Run Mode
@ 12Mhz
IDD9 5.3 mA
VDD= 5.5V@12MHz,
enable all IP and disable PLL,XTAL=12MHz
IDD10 3.7 mA
VDD= 5.5V@12MHz,
disable all IP and disable PLL,XTAL=12MHz
IDD11 4.0 mA
VDD= 3.3V@12MHz,
enable all IP and disable PLL,XTAL=12MHz
IDD12 2.3 mA
VDD= 3.3V@12MHz,
disable all IP and disable PLL,XTAL=12MHz
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PARAMETER SYM.
SPECIFICATION
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Operating Current
Normal Run Mode
@ 4 MHz
IDD13 3.4 mA
VDD= 5.5V@4MHz,
enable all IP and disable PLL,XTAL=4MHz
IDD14 2.6 mA
VDD= 5.5V@4MHz,
disable all IP and disable PLL,XTAL=4MHz
IDD15 2.0 mA
VDD= 3.3V@4MHz,
enable all IP and disable PLL,XTAL=4MHz
IDD16 1.3 mA
VDD= 3.3V@4MHz,
disable all IP and disable PLL,XTAL=4MHz
Operating Current
Normal Run Mode
@10Khz
IDD17 98.7 uA
VDD= 5.5V@10KHz,
enable all IP and IRC10K,
disable PLL
IDD18 97.4 uA
VDD= 5.5V@10KHz,
disable all IP and enable IRC10K,
disable PLL
IDD19 86.4 uA
VDD= 3.3V@10KHz,
enable all IP and IRC10K,
disable PLL
IDD20 85.2 uA
VDD= 3.3V@10KHz,
disable all IP and enable IRC10K,
disable PLL
Operating Current
Idle Mode
@ 50 MHz
IIDLE1 16.2 mAVDD= 5.5V@50 MHz, enable all IP andPLL, XTAL=12 MHz
IIDLE2 10.0 mA VDD=5.5V@50 MHz, disable all IP andenable PLL, XTAL=12 MHz
IIDLE3 14.6 mAVDD= 3V@50 MHz, enable all IP and PLL,
XTAL=12 MHz
IIDLE4 8.5 mAVDD= 3V@50 MHz, disable all IP andenable PLL, XTAL=12 MHz
Operating Current
Idle Mode
@ 22Mhz
IIDLE5 4.3 mA
VDD= 5.5V@22MHz,
enable all IP and IRC22M,
disable PLL
IIDLE6 1.5 mA
VDD=5.5V@22MHz,
disable all IP and enable IRC22M,
disable PLL
IIDLE7 4.2 mA
VDD= 3.3V@22MHz,
enable all IP and IRC22M,
disable PLL
IIDLE8 1.4 mA
VDD= 3.3V@22MHz,
disable all IP and enable IRC22M,
disable PLL
Operating Current
Idle ModeIIDLE9 4.3 mA
VDD= 5.5V@12MHz,
enable all IP and disable PLL,XTAL=12MHz
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PARAMETER SYM.
SPECIFICATION
TEST CONDITIONSMIN. TYP. MAX. UNIT
@ 12 MHz
IIDLE10 2.6 mA
VDD= 5.5V@12MHz,
disable all IP and disable PLL,XTAL=12MHz
IIDLE11 2.9 mA
VDD= 3.3V@12MHz,
enable all IP and disable PLL,XTAL=12MHz
IIDLE12 1.3 mA
VDD= 3.3V@12MHz,
disable all IP and disable PLL,XTAL=12MHz
Operating Current
Idle Mode
@ 4 MHz
IIDLE13 3.0 mA
VDD= 5.5V@4MHz,
enable all IP and disable PLL,XTAL=4MHz
IIDLE14 2.3 mA
VDD= 5.5V@4MHz,
disable all IP and disable PLL,XTAL=4MHz
IIDLE15 1.7 mA
VDD= 3.3V@4MHz,
enable all IP and disable PLL,XTAL=4MHz
IIDLE16 1.0 mA
VDD= 3.3V@4MHz,
disable all IP and disable PLL,XTAL=4MHz
Operating Current
Idle Mode
@10Khz
IIDLE17 97.8 uA
VDD= 5.5V@10KHz,
enable all IP and IRC10K,
disable PLL
IIDLE18 96.5 uA
VDD= 5.5V@10KHz,
disable all IP and enable IRC10K,disable PLL
IIDLE19 85.5 uA
VDD= 3.3V@10KHz,
enable all IP and IRC10K,
disable PLL
IIDLE20 84.4 uA
VDD= 3.3V@10KHz,
disable all IP and enable IRC10K,
disable PLL
Standby Current
Power-down Mode
(Deep Sleep Mode)
IPWD1 10 AVDD= 5.5V, No load @ Disable BOVfunction
IPWD2 10 AVDD= 3.0V, No load @ Disable BOVfunction
Input Current P0/1/2/3/4(Quasi-bidirectional
mode)
IIN1 -75 - +15 A VDD= 5.5V, VIN = 0V or VIN= VDD
Input Leakage CurrentP0/1/2/3/4
ILK -1 - +1 A VDD= 5.5V, 0
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PARAMETER SYM.
SPECIFICATION
TEST CONDITIONS
MIN. TYP. MAX. UNIT
1.5 -VDD+0.2
VDD=3.0V
Input Low VoltageXT1[*2]
VIL30 - 0.8 V VDD= 4.5V
0 - 0.4 VDD= 2.5V
Input High VoltageXT1[*2]
VIH3
3.5 -VDD+0.2
V VDD= 5.5V
2.4 -VDD+0.2
VDD= 3.0V
Negative going threshold
(Schmitt input), /RSTVILS -0.5 - 0.2 VDD V
Positive going threshold
(Schmitt input), /RSTVIHS 0.7 VDD -
VDD
+0.5V
Internal /RST pin pull upresistor
RRST 40 150 K
Negative going threshold
(Schmitt input),P0/1/2/3/4
VILS -0.5 - 0.3 VDD V
Positive going threshold
(Schmitt input),P0/1/2/3/4
VIHS 0.7 VDD -VDD
+0.5V
Source CurrentP0/1/2/3/4 (Quasi-bidirectional Mode)
ISR11 -300 -370 -450 A VDD= 4.5V, VS = 2.4V
ISR12 -50 -70 -90 A VDD= 2.7V, VS = 2.2V
ISR13 -40 -60 -80 A VDD= 2.5V, VS = 2.0V
Source CurrentP0/1/2/3/4 (Push-pullMode)
ISR21 -20 -24 -28 mA VDD= 4.5V, VS = 2.4V
ISR22 -4 -6 -8 mA VDD= 2.7V, VS = 2.2V
ISR23 -3 -5 -7 mA VDD= 2.5V, VS = 2.0V
Sink Current P0/1/2/3/4(Quasi-bidirectional andPush-pull Mode)
ISK11 10 16 20 mA VDD= 4.5V, VS = 0.45V
ISK12 7 10 13 mA VDD= 2.7V, VS = 0.45V
ISK13 6 9 12 mA VDD= 2.5V, VS = 0.45V
Brown-Out voltage withBOV_VL [1:0] =00b
VBO2.2 2.0 2.2 2.4 V VDD=5.5V
Brown-Out voltage withBOV_VL [1:0] =01b
VBO2.7 2.5 2.7 2.9 V VDD=5.5V
Brown-Out voltage with
BOV_VL [1:0] =10b
VBO3.8 3.5 3.7 3.9 V VDD=5.5V
Brown-Out voltage withBOV_VL [1:0] =11b
VBO4.5 4.1 4.3 4.5 V VDD=5.5V
Hysteresis range of BODvoltage
VBH 30 - 150 mV VDD= 2.5V~5.5V
Notes:
1. /RST pin is a Schmitt trigger input.2. XTAL1 is a CMOS input.3. Pins of P0, P1, P2, P3 and P4 can source a transition current when they are being externally driven from 1 to 0. In the condition of VDD=5.5V, 5he transition currentreaches its maximum value when Vin approximates to 2V .
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7.3 AC Electrical Characteristics
7.3.1 External Crystal
tCLCL
tCLCX
tCHCX
tCLCH
tCHCL
Note:Duty cycle is 50%.
PARAMETER SYMBOL MIN. TYP. MAX. UNITS CONDITION
Clock High Time tCHCX 20 - - nS
Clock Low Time tCLCX 20 - - nS
Clock Rise Time tCLCH - - 10 nS
Clock Fall Time tCHCL - - 10 nS
7.3.2 External Oscillator
PARAMETER CONDITION MIN. TYP. MAX. UNIT
Input clock frequency External crystal 4 12 24 MHz
Temperature - -40 - 85
VDD - 2.5 5 5.5 V
Operating current 12 MHz@ VDD= 5V - 1 - mA
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7.3.3 Typical Crystal Application CircuitsCRYSTAL C1 C2
4 MHz ~ 24 MHzOptional
(Depend on crystal specification)
XTAL2
XTAL1
C1
C2
Figure 7-1 Typical Crystal Application Circuit
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7.4 Analog Characteristics
7.4.1 Specification of 12-bit SARADC
PARAMETER SYM. MIN. TYP. MAX. UNIT
Resolution - - - 12 Bit
Differential nonlinearity error DNL - 1.2 - LSB
Integral nonlinearity error INL - 1.2 - LSB
Offset error EO - +3 +5 LSB
Gain error (Transfer gain) EG - -4 -6 -
Monotonic - Guaranteed -
ADC clock frequency FADC - - 16 MHz
Conversion time TADC - 13 - Clock
Sample rate FS - - 760 K SPS
Supply voltage
VLDO - 1.8 - V
VADD 3 - 5.5 V
Supply current (Avg.)
IDD - 0.5 - mA
IDDA - 1.5 - mA
Input voltage range VIN 0 - AVDD V
Capacitance CIN - 5 - pF
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7.4.2 Specification of LDO & Power management
RAMETER MIN TYP MAX UNIT NOTE
Input Voltage 2.5 5 5.5 V VDDinput voltage
Output Voltage -10% 1.8 +10% V LDO output voltage
Temperature -40 25 85
C - 1u - F Resr=1ohm
Note:
1. It is recommended a 100nF bypass capacitor is connected between VDDand the closest VSSpin of the device.
2. For ensuring power stability, a 1uF or higher capacitor must be connected between LDO pinand the closest VSSpin of the device.
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7.4.6 Specification of Temperature Sensor
PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supply voltage[1]
1.62 1.8 1.98 V
Temperature -40 - 85
Gain -1.72 -1.76 -1.80 mV/
Offset Temp=0 717 725 733 mV
Note[1]: Internal operation voltage comes from LDO.
7.4.7 Specification of Comparator
PARAMETER CONDITION MIN. TYP. MAX. UNIT
Temperature - -40 25 85
VDD - 2.4 3 5.5 V
VDDcurrent - - 40 80 uA
Input offset voltage - 10 20 mV
Output swing - 0.1 - VDD-0.1 V
Input common mode range - 0.1 - VDD-0.1 V
DC gain - - 70 - dB
Propagation delay@VCM=1.2 V and
VDIFF=0.1 V- 200 - ns
Hysteresis @VCM=0.2 V ~ VDD-0.2V - 10 - mV
Stable time@CINP=1.3 V
CINN=1.2 V- - 2 us
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7.5 Flash DC Electrical Characteristics
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Nendu Endurance 100000 cycles[1]
Tret Retention time Temp=85 10 year
Terase Page erase time 19 20 21 ms
Tmess Mess erase time 30 40 50 ms
Tprog Program time 38 40 42 us
VDD Supply voltage 1.62 1.8 1.98 V[2]
Idd1 Read current 0.25 mA
Idd2 Program/Erase current 7 mA
Ipd Power down current 1 20 uA
1. Number of program/erase cycles.2. VDDis source from chip LDO output voltage.3. Guaranteed by design, not test in production.
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8.2 QFN-33 (5X5 mm2, Thickness 0.8mm, Pitch 0.5 mm)
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9 REVISION HISTORYVERSION DATE PAGE DESCRIPTION
V1.0 Oct 20, 2011 - Initial issued
V1.01 Mar. 19, 2012 7.3.4 Updated the Center Frequency of 22Mhz RC spec
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Important Notice
Nuvoton Products are neither intended nor warranted for usage in systems or equipment, any
malfunction or failure of which may cause loss of human life, bodily injury or severe propertydamage. Such applications are deemed, Insecure Usage.
Insecure usage includes, but is not limited to: equipment for surgical implementation, atomicenergy control instruments, airplane or spaceship instruments, the control or operation ofdynamic, brake or safety systems designed for vehicular use, traffic signal instruments, alltypes of safety devices, and other applications intended to support or sustain life.
All Insecure Usage shall be made at customers risk, and in the event that third parties layclaims to Nuvoton as a result of customers Insecure Usage, customer shall indemnify thedamages and liabilities thus incurred by Nuvoton.