NUMERICAL TECHNOLOGIES, INC. Sub-wavelength Lithography: An Impact of Photo Mask Errors on Circuit Performance L. Karklin, S. Mazor, D.Joshi 1, A. Balasinski

NUMERICAL TECHNOLOGIES, INC.

Sub-wavelength Sub-wavelength Lithography: An Impact of Lithography: An Impact of Photo Mask Errors on Photo Mask Errors on Circuit PerformanceCircuit Performance

Sub-wavelength Sub-wavelength Lithography: An Impact of Lithography: An Impact of Photo Mask Errors on Photo Mask Errors on Circuit PerformanceCircuit Performance

L. Karklin, S. Mazor,

D.Joshi1, A. Balasinski2,

and V. Axelrad3

L. Karklin, S. Mazor,

D.Joshi1, A. Balasinski2,

and V. Axelrad3 1Numerical Technologies, Inc., USA, 2Cypress Semiconductor, USA, and 3Sequoia Design Systems, USA

SPIE’02 ml4691-24

2

NUMERICAL TECHNOLOGIES, INC.Lnk 2001

AgendaAgenda

Introduction Experimental conditions

Simulation flow Sensitivity analysis Monte Carlo simulation of mask CD errors

Results and discussion Lithography data Device and circuit simulation Summary

Introduction Experimental conditions

Simulation flow Sensitivity analysis Monte Carlo simulation of mask CD errors

Results and discussion Lithography data Device and circuit simulation Summary

3


The sub-wavelength era impacts the full design-to-manufacturing flow

The sub-wavelength era impacts the full design-to-manufacturing flow

MASK

SILICONWAFER

LAYOUT

MASK

SILICONWAFER

Above Wavelength What is drawn in design is printed on Silicon - “WYSIWYG”

LAYOUT MASK SILICON WAFER= =

SubWavelength

4


MASKMASK

We need new design software and infrastructure to account for process effects and distortions from design through final device

We need new design software and infrastructure to account for process effects and distortions from design through final device

DESIGN

LAYOUT

SILICON

DEVICEThe photomask is the most critical link in that flow

ITRS 2001, SEMATECH

5


Simulation flowSimulation flow

MASKMASK

DESIGN

LAYOUT

SILICON

DEVICE

MASKMASKLAYOUT

SILICON

DEVICE

6


Experimental flowExperimental flow

Litho data

Sensitivity analysis

Device and circuit simulation

7


Experimental flowExperimental flow

ICWB

NA, , RET

Photo Mask CD Distribution

Wafer CD Distribution

Wafer CD Distribution

SDD•Device Parametric Yield

•Circuit (Ring Oscillator) C:\Circuit.ppt

0

200

400

600

800

1000

1200

0

200

400

600

800

1000

1200

1400

1600

1800

2000

72.4

74.1

75.8

77.5

79.2

80.8

82.5

84.2

85.9

87.6

0

200

400

600

800

1000

1200

Device Parameters

8


Lithography optionsLithography options

Design Rules: Design: An Isolated line CD=80 nm , Dense lines pitch=220nm Target CD =70 nm (in resist, all dimensions are on wafer scale)

=248 nm (KrF) and = 193 nm (ArF); 4x Reduction mask; NA=0.75; Conventional (circular) Illumination: =0.75; RET used:

Annular Illumination: in= 0.60; out= 0.80; Scatter Bars: 40 nm, optimized placement (based on min. MEF) PSM: EAPSM, Phase=180°, T=10%

Design Rules: Design: An Isolated line CD=80 nm , Dense lines pitch=220nm Target CD =70 nm (in resist, all dimensions are on wafer scale)

=248 nm (KrF) and = 193 nm (ArF); 4x Reduction mask; NA=0.75; Conventional (circular) Illumination: =0.75; RET used:

Annular Illumination: in= 0.60; out= 0.80; Scatter Bars: 40 nm, optimized placement (based on min. MEF) PSM: EAPSM, Phase=180°, T=10%

10


Sensitivity analysisSensitivity analysis

• SEQUOIA Design Systems’ Sensitivity

Analysis estimates device variability for a

given level of manufacturing control

70 nm

MOSFET

Lpoly

• For a 70nm device

we obtain:

Vth=340mV13mV

Idsat=1mA0.09mA

11


Variability sourcesVariability sources

Main source of variability is CD Control (Lpoly) Lpoly responsible for 71% of Vth variability Lpoly responsible for 84% of Idsat variability

Main source of variability is CD Control (Lpoly) Lpoly responsible for 71% of Vth variability Lpoly responsible for 84% of Idsat variability

Vth Idsat

12


Lpoly (Gate) CD variationsLpoly (Gate) CD variations

Gaussian Distribution

10,000 Samples

3 = 20 nm, 40 nm;

Lpoly

0

200

400

600

800

1000

1200

1400

1600

1800

2000

72.4

74.1

75.8

77.5

79.2

80.8

82.5

84.2

85.9

87.6-3s +3

s

13


Mask Yield Projections - Historical Base

CD 3-Sigma Mask Yields

0

10

20

30

40

50

60

70

80

90

100

0 5 10 15 20 25 30 35 40 45 50 55CD Tolerance (nm)

% Y

ield

Year 0-1

Year 1-2

Year 2-3

Slide courtesy of Brian Grenon, Grenon Consulting, Inc.

14


Mask CD uniformityMask CD uniformity

Data courtesy of Anja Rosenbusch, Etec Systems Inc., an Applied Materials Company

5 nm on wafer

10 nm on wafer

16


Lithography dataLithography data

17


Mask CD distribution mapped to the wafer CD distribution

Mask CD distribution mapped to the wafer CD distribution

Wafer CD distribution depends on the lithography options used

18


Mask linearity dataMask linearity data

40

45

50

55

60

65

70

75

80

85

90

72 74 76 78 80 82 84 86 88

DENSE-193_bin_C

DENSE-193_bin_Ann

DENSE-193_att_Ann

ISO-193_bin_C

ISO-193_bin_Ann

ISO-193_att_Ann

Design [nm]

Wafer [nm]

19


0.0

1.0

2.0

3.0

4.0

5.0

6.0

Iso_b

in_c

Iso_b

in_c_

SB_opt

Iso_b

in_c_

SB_nop

t

Iso_b

in_an

n_SB_n

opt

Iso_b

in_an

n_SB_o

pt

Dense

_bin_

c

Dense

_bin_

ann

Dense

_att_

ann

MEF

MEF data for 248 nm lithographyMEF data for 248 nm lithography

MEF

20


MEF data for 193 nm lithographyMEF data for 193 nm lithography

0.0

0.5

1.0

1.5

2.0

2.5

3.0

Dense

_bin

Dense

_bin_a

nn

Dense

_att

Dense

_att_

ann

Iso_

bin

Iso-

att

Iso-

ann

Iso_

c_SB

Iso_

ann_SB

MEF

MEF

21


Simulated wafer CD distributionSimulated wafer CD distribution

0

500

1000

1500

2000

2500

56.6

59.8

63.0

66.0

68.9

71.9

74.8

77.5

80.1

82.7

Gaussian193_ann

0

500

1000

1500

2000

2500

46.1

52.0

57.8

62.5

67.2

72.0

76.7

80.4

84.0

87.5

Gaussian248_ann

0

500

1000

1500

2000

2500

50.3

55.5

60.6

65.1

69.6

74.0

78.5

82.4

86.1

89.9

Gaussian193_c

0

500

1000

1500

2000

2500

19.3

32.5

45.2

53.9

62.6

71.3

79.9

84.6

88.7

92.9

Gaussian248_c

193 nm

Annular

248 nm

Annular

193 nm

Circular

248 nm

Circular

+/- 3 +/- 3

+/- 3 +/- 3

22


Device and circuit simulationDevice and circuit simulation

23


Wafer CD (Lpoly) distribution translated to MOSFET Vth distribution

Wafer CD (Lpoly) distribution translated to MOSFET Vth distribution

24


Wafer CD (Lpoly) distribution translated to ring oscillator speed

Wafer CD (Lpoly) distribution translated to ring oscillator speed

25


Statistical analysis of the simulated dataStatistical analysis of the simulated data

Using SDD one can calculate a fractional yield based on custom specifications

26


Ring oscillator frequency distributionRing oscillator frequency distribution

0200

400600

80010001200

14001600

18002000

19.8

18.5

17.6

16.9

16.3

15.8

15.2

14.7

14.4

14.2

1.7ISO_CA3

0

200

400

600

800

1000

1200

19.8

18.5

17.6

16.9

16.3

15.8

15.2

14.7

14.4

14.2

3.3ISO_CA3

0200400

600800

100012001400

160018002000

18.0

17.6

17.2

16.8

16.3

16.1

15.7

15.3

15.1

14.8

1.7DENSE_Ann_PSMA3

0

200

400

600

800

1000

1200

18.0

17.6

17.2

16.8

16.3

16.1

15.7

15.3

15.1

14.8

3.3DENSE_Ann_PSMA3

3=20 nm* 3s=40 nm*

* On the 4x Mask

27


SummarySummary

We presented a comprehensive method by which to evaluate the layout/mask dependent device and circuit performance for different lithography options.

We simulated large numbers of random mask errors and propagated these data through the virtual MOSFET manufacturing pipeline by using fast lithography and device simulators linked together.

Using statistical analysis we estimated the impact of mask CD errors (3) and lithography options (RET) on the printed wafer data and final circuit (RO) performance.

Proposed methodology can be applied either to simulated data or to experimental data.

We presented a comprehensive method by which to evaluate the layout/mask dependent device and circuit performance for different lithography options.

We simulated large numbers of random mask errors and propagated these data through the virtual MOSFET manufacturing pipeline by using fast lithography and device simulators linked together.

Using statistical analysis we estimated the impact of mask CD errors (3) and lithography options (RET) on the printed wafer data and final circuit (RO) performance.

Proposed methodology can be applied either to simulated data or to experimental data.

Documents

NUMERICAL TECHNOLOGIES, INC. Sub-wavelength Lithography: An Impact of Photo Mask Errors on Circuit Performance L. Karklin, S. Mazor, D.Joshi 1, A. Balasinski