NTU/EE&CS/GIEE NTU/EE&CS/GIEE HW/SW Co-designHW/SW Co-designAdvisor:Advisor: Dr. Sao-Jie ChenDr. Sao-Jie ChenPresenter:Presenter: B89902052 Lindet PengB89902052 Lindet Peng

P91943009 Tso-Tsai ChenP91943009 Tso-Tsai Chen

June 1June 1stst 2004 2004

[[ RISC-CPU in SystemC RISC-CPU in SystemC ]]

HW/SW Co-design term projectHW/SW Co-design term project

OutlineOutline Architecture Instructions selected Modeling in SystemC – source coding

Verification in SystemC Data comparison Analysis Conclusion for the current step

Future work Reference

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ArchitectureArchitectureHW/SW Co-design architecture

Hardware sideSoftware sidemachine code

SystemC

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ArchitectureArchitecture >> >> HardwareHardware

Instruction Fetch

Instruction Cache

Instruction Decoder

Data Cache Floating Execution

Integer Execution

Instruction fromSoftware ALU

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ArchitectureArchitecture >> >> SoftwareSoftware

Hardwaresimulation

machinecode

Assembly code

add R1, R2, R3addi R2, R3, 14sub R4, R5, R6subi R4, R5, 28mul R1, R2, R4

Machine code0x01010203 /* add R1, R2, R3 */0x0202030e /* addi R2, R3, 14 */0x04040506 /* sub R4, R5, R6 */0x0504051c /* subi R4, R5, 28 */0x07010204 /* mul R1, R2, R4 */

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associate filesassociate files Instruction Fetch (code file “fetch.cpp”)

Input: Instruction Data (code file “icache”)Output: Fetched InstructionFunction: Fetch Instruction from the file “icache”

Instruction Decode and Control (code file “decode.cpp”)Input: The instruction which has been splitOutput: The Control Lines of execution stageFunction: Decode the instruction & set the Control Lines

Data Management (code file “paging.cpp”)Input: Write & Control LinesOutput: Read LinesFunction: As a Memory Controller

Instruction Execution (code files “exec.cpp” & “floating.cpp”)

Input: Control & Data LinesOutput: Data LinesFunction: Perform the execution

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Modeling in SystemCModeling in SystemCsource codingsource coding

Performance Functionality Register transfer level (RTL) Gate level

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Verification in SystemCVerification in SystemC >> >> inputinput

The results we predict –R3 = R1(=10) + R2(=20)R6 = R5(=40) - R4(=30)R9 = R7(=50) * R8(=60)R12 = R10(=242) / R11(=11)

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Verification in SystemCVerification in SystemC >> >> outputoutput

The results we predict –R3 = R1(=10) + R2(=20)R6 = R5(=40) - R4(=30)R9 = R7(=50) * R8(=60)R12 = R10(=242) / R11(=11)

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ComparisonComparison Verification Predict

DecimalRaw Data

HexadecimalResult

R3 = R1(=10) + R2(=20) R3 = 30 R3 = 1e Correct

R6 = R5(=40) - R4(=30) R6 = 10 R6 = a Correct

R9 = R7(=50) * R8(=60) R9 = 3000 R9 = bb8 Correct

R12 = R10(=242) / R11(=11) R12 = 22 R12 = 16 Correct

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Conclusion Conclusion for the current for the current stepstep

Some of the fundamental instructions of the selected RISC CPU have been simulated and verified in SystemC without error, which is encouraging us towards an efficient HW-SW Co-design through the architecture and logic behind the approach.

With a thorough frame work, task like designing the selected RISC CPU can be divided into several layers, which can be properly verified one-by-one, in hierarchy, before we submit the RTL work.

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Future workFuture work Advanced instructions Advanced technique like multi-cpu or

superscale may enhance the system performance

A more complicate architecture

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ReferenceReference Simple RISC on SystemC written by Martin Wang at

SYNOPSYS Inc. SystemC version 2.0 User’s Guide with update for

SystemC 2.0.1 SystemC v2.0.1 Functional Spec SystemC v2.0.1 White Paper