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NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
1
Semiconductor Manufacturing Technology:
Semiconductor Manufacturing Processes
Conrad T. Sorenson
Praxair, Inc.
1999 Arizona Board of Regents for The University of Arizona
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor Manufacturing
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Semiconductor Manufacturing Processes
• Design• Wafer Preparation• Front-end Processes• Photolithography• Etch• Cleaning• Thin Films• Ion Implantation• Planarization• Test and Assembly
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIon
Implantation
Planarization
Test &Assembly
DesignWafer
Preparation
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Design
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
• Establish Design Rules• Circuit Element Design• Interconnect Routing• Device Simulation• Pattern Preparation
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Pattern PreparationReticle
Chrome Pattern
Quartz Substrate
Pellicle
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Wafer Preparation
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
• Polysilicon Refining• Crystal Pulling• Wafer Slicing & Polishing• Epitaxial Silicon Deposition
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Polysilicon Refining
Chemical Reactions Silicon Refining: SiO2 + 2 C Si + 2 CO Silicon Purification: Si + 3 HCl HSiCl3 + H2
Silicon Deposition: HSiCl3 + H2 Si + 3 HCl
Reactants H2 Silicon Intermediates H2SiCl2
HSiCl3
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Crystal PullingQuartz Tube
Rotating Chuck
Seed Crystal
Growing Crystal (boule)
RF or ResistanceHeating Coils
Molten Silicon(Melt)
Crucible
Materials Polysilicon Nodules * Ar * H2
* High proportion of the total product use
Process Conditions Flow Rate: 20 to 50 liters/min Time: 18 to 24 hours Temperature: >1,300 degrees C Pressure: 20 Torr
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
83/15/98 PRAX01C.PPT Rev. 1.0
Wafer Slicing & Polishing
The silicon ingot is grown and individual wafers are sliced.
The silicon ingot is sliced into individual wafers, polished, and cleaned.
silicon wafer
p+ silicon substrate
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Epitaxial Silicon Deposition
GasInput Lamp
Module
QuartzLamps
Wafers
Susceptor
Exhaust
* High proportion of the total product use
Chemical Reactions Silicon Deposition: HSiCl3 + H2 Si + 3 HClProcess Conditions Flow Rates: 5 to 50 liters/min Temperature: 900 to 1,100 degrees C. Pressure: 100 Torr to Atmospheric
silicon wafer
p- silicon epi layer
p+ silicon substrate
Dopants AsH3
B2H6
PH3
Etchant HClCarriers Ar H2 * N2
Silicon Sources SiH4
H2SiCl2
HSiCl3 * SiCl4 *
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIon
Implantation
Planarization
Test &Assembly
DesignWaferPreparation• Thermal Oxidation
• Silicon Nitride Deposition- Low Pressure Chemical Vapor
Deposition (LPCVD)• Polysilicon Deposition
- Low Pressure Chemical Vapor Deposition (LPCVD)
• Annealing
Front-End Processes
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Front-End Processes
* High proportion of the total product use
Polysilicon H2
N2
SiH4 * AsH3 B2H6 PH3
Exhaust ViaVacuum Pumpsand Scrubber
3 ZoneTemperatureControl
Gas Inlet
Vertical LPCVD Furnace
Quartz TubeChemical Reactions Thermal Oxidation: Si + O2 SiO2 Nitride Deposition: 3 SiH4 + 4 NH3 Si3N4 + 12 H2
Polysilicon Deposition: SiH4 Si + 2 H2
Process Conditions (Silicon Nitride LPCVD) Flow Rates: 10 - 300 sccm Temperature: 600 degrees C. Pressure: 100 mTorr
silicon dioxide (oxide)
p- silicon epi layer
p+ silicon substrate
Nitride NH3 * H2SiCl2 * N2
SiH4 * SiCl4
Oxidation Ar N2
H2O Cl2
H2
HCl * O2 * Dichloroethene *
Annealing Ar He H2
N2
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Photolithography
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
• Photoresist Coating Processes• Exposure Processes
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Photoresist Coating Processes
p- epi
p+ substrate
field oxidephotoresist
Photoresists Negative Photoresist * Positive Photoresist *Other Ancillary Materials (Liquids) Edge Bead Removers * Anti-Reflective Coatings * Adhesion Promoters/Primers (HMDS) * Rinsers/Thinners/Corrosion Inhibitors * Contrast Enhancement Materials *Developers TMAH * Specialty Developers *Inert Gases Ar N2
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Exposure Processes
p- epi
p+ substrate
field oxidephotoresist
Expose Kr + F2 (gas) *
Inert Gases N2
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Ion Implantation
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
• Well Implants• Channel Implants• Source/Drain Implants
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Ion Implantation
180 kV
ResolvingAperture
Ion Source
Equipment Ground
Acceleration Tube
90° Analyzing Magnet
Terminal Ground
20 kV
Focus Neutral beam and beam path gated
Beam trap andgate plate
Wafer in waferprocess chamber
X - axisscanner
Y - axisscanner
Neutral beam trap and beam gate
Gases Ar AsH3
B11F3 * He N2
PH3
SiH4
SiF4
GeH4
Solids Ga In SbLiquids Al(CH3)3
* High proportion of the total product use
junction depth
p- epi
p+ substrate
field oxide
photoresist mask
n-w ellp-channel transistor
phosphorus (-) ions
Process Conditions Flow Rate: 5 sccm Pressure: 10-5 Torr Accelerating Voltage: 5 to 200 keV
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Etch
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
• Conductor Etch- Poly Etch and Silicon Trench
Etch- Metal Etch
• Dielectric Etch
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Conductor Etch
* High proportion of the total product use
EtchChambers
Cluster ToolConfiguration
TransferChamber
Loadlock
Wafers
RIE Chamber
TransferChamber
Gas Inlet
Exhaust
RF Power
Wafer
p+ substrate
p-w elln-channel transistor
n-w ellp-channel transistor
source-drain areas
gate linew idth
gate oxide
Polysilicon Etches HBr * C2F6 SF6 * NF3 * O2
Aluminum Etches BCl3 * Cl2
Diluents Ar He N2
Chemical Reactions Silicon Etch: Si + 4 HBr SiBr4 + 2 H2 Aluminum Etch: Al + 2 Cl2 AlCl4
Process Conditions Flow Rates: 100 to 300 sccm Pressure: 10 to 500 mTorr RF Power: 50 to 100 Watts
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Dielectric Etch
* High proportion of the total product use
EtchChambers
Cluster ToolConfiguration
TransferChamber
Loadlock
Wafers
RIE Chamber
TransferChamber
Gas Inlet
Exhaust
RF Power
Wafer
Contact locations
n-w ellp-channel transistor
p-w elln-channel transistor
p+ substrate
Chemical Reactions Oxide Etch: SiO2 + C2F6 SiF4 + CO2 + CF4 + 2 COProcess Conditions Flow Rates: 10 to 300 sccm Pressure: 5 to 10 mTorr RF Power: 100 to 200 Watts
Plasma Dielectric Etches CHF3 * CF4
C2F6
C3F8
CO *
Diluents Ar He N2
CO2
O2
SF6
SiF4
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Cleaning
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
• Critical Cleaning• Photoresist Strips• Pre-Deposition Cleans
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Critical Cleaning
11 22 33 44 55
1 O r g a n i c s 2 O x i d e s 3 P a r t i c l e s 4 M e t a l s 5 D r yH 2 S O 4 + H F + N H 4 O H + H C l + H 2 O o r I P A +H 2 O 2 H 2 O H 2 O 2 + H 2 O H 2 O 2 + H 2 O N 2
H 2 O R i n s e H 2 O R i n s e H 2 O R i n s e H 2 O R i n s e
Contact locations
n-w ellp-channel transistor
p-w elln-channel transistor
p+ substrate
RCA Clean SC1 Clean (H2O + NH4OH + H2O2) * * SC2 Clean (H2O + HCl + H2O2) *
Piranha Strip * H2SO4 + H2O2 *
Nitride Strip H3PO4 *
Oxide Strip HF + H2O *
Solvent Cleans NMP Proprietary Amines (liquid)Dry Cleans HF O2 Plasma Alcohol + O3
Dry Strip N2O O2
CF4 + O2
O3
Process Conditions Temperature: Piranha Strip is 180 degrees C.
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Thin Films
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation• Chemical Vapor Deposition
(CVD) Dielectric • CVD Tungsten• Physical Vapor Deposition
(PVD)• Chamber Cleaning
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Chemical Vapor Deposition (CVD) Dielectric
* High proportion of the total product use
CVD Dielectric O2
O3
TEOS * TMP *
TEOSSource
LPCVDChamber
TransferChamber
Gas Inlet
Exhaust
RF Power
Wafer
MeteringPump
Inert MixingGas
Process Gas
Vaporizer
DirectLiquid
Injection
n-w ellp-channel transistor
p-w elln-channel transistor
p+ substrate
Metal 1insulator layer 2
Chemical Reactions Si(OC2H5)4 + 9 O3 SiO2 + 5 CO + 3 CO2 + 10 H2OProcess Conditions (ILD) Flow Rate: 100 to 300 sccm Pressure: 50 Torr to Atmospheric
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Chemical Vapor Deposition (CVD) Tungsten
* High proportion of the total product use
CVD Dielectric WF6 * Ar H2
N2
OutputCassette
InputCassette
WaferHander
Wafers
Water-cooledShowerheads
Multistation SequentialDeposition Chamber
ResistivelyHeated Pedestal
n-w ellp-channel transistor
p-w elln-channel transistor
p+ substrate
titanium tungsten
Chemical Reactions WF6 + 3 H2 W + 6 HFProcess Conditions Flow Rate: 100 to 300 sccm Pressure: 100 mTorr Temperature: 400 degrees C.
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Physical Vapor Deposition (PVD)
Barrier Metals SiH4
Ar N2
N2
Ti PVD Targets *
PhysicalVaporDepositionChambers
Cluster ToolConfiguration
TransferChamber
Loadlock
Wafers
PVD Chamber
TransferChamber
Cryo Pump
Wafer
N S N
+
e -
BacksideHe Cooling
Argon &Nitrogen
ReactiveGases
DC PowerSupply (+)
* High proportion of the total product use
n-w ellp-channel transistor
p-w elln-channel transistor
p+ substrate
Process Conditions Pressure: < 5 mTorr Temperature: 200 degrees C. RF Power:
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Chamber Cleaning
* High proportion of the total product use
Chamber Cleaning C2F6 * NF3
ClF3
Water-cooledShowerheads
Multistation SequentialDeposition Chamber
ResistivelyHeated Pedestal
Chemical Reactions Oxide Etch: SiO2 + C2F6 SiF4 + CO2 + CF4 + 2 COProcess Conditions Flow Rates: 10 to 300 sccm Pressure: 10 to 100 mTorr RF Power: 100 to 200 Watts
Aluminum
Surface Coating
Process Material Residue
Chamber Wall Cross-Section
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Planarization
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
• Oxide Planarization• Metal Planarization
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Chemical Mechanical Planarization (CMP)
* High proportion of the total product use.
Platen
PolishingHead
PadConditioner
Carousel
HeadSweep Slide
Load/UnloadStation
Wafer HandlingRobot & I/O
Polishing PadSlurryDelivery
Platen
WaferCarrier
Wafer
n-w ellp-channel transistor
p-w elln-channel transistor
p+ substrate
Backing (Carrier) Film PolyurethanePad PolyurethanePad Conditioner Abrasive
CMP (Oxide) Silica Slurry KOH * NH4OH H2O
CMP (Metal) Alumina * FeNO3
Process Conditions (Oxide) Flow: 250 to 1000 ml/min Particle Size: 100 to 250 nm Concentration: 10 to 15%, 10.5 to 11.3 pHProcess Conditions (Metal) Flow: 50 to 100 ml/min Particle Size: 180 to 280 nm Concentration: 3 to 7%, 4.1 - 4.4 pH
*
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Test and Assembly
Thin Films
Photo-lithography
Cleaning
Front-EndProcesses
EtchIonImplantation
Planarization
Test &Assembly
DesignWaferPreparation
• Electrical Test Probe• Die Cut and Assembly• Die Attach and Wire Bonding• Final Test
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Electrical Test Probe
Defective IC
Individual integrated circuits are tested to distinguish good
die from bad ones.
n-wellp-channel transistor
p-welln-channel transistor
p+ substrate
bonding padnitride
Metal 2
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Die Cut and Assembly
Good chips are attached to a lead frame package.
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Die Attach and Wire Bonding
lead frame gold wire
bonding pad
connecting pin
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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Final Test
Chips are electrically tested under varying environmental conditions.
NSF/SRC Engineering Research Center for Environmentally Benign Semiconductor ManufacturingSorenson
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References
1. CMOS Process Flow in Wafer Fab, Semiconductor Manufacturing Technology, DRAFT, Austin Community College, January 2, 1997.
2. Semiconductor Processing with MKS Instruments, Inc.
3. Worthington, Eric. “New CMP architecture addresses key process issues,” Solid State Technology, January 1996.
4. Leskonic, Sharon. “Overview of CMP Processing,” SEMATECH Presentation, 1996.
5. Gwozdz, Peter. “Semiconductor Processing Technology” SEMI, 1997.
6. CVD Tungsten, Novellus Sales Brochure, 7/96.
7. Fullman Company website. “Fullman Company - The Semiconductor Manufacturing Process,” http://www.fullman.com/semiconductors/index.html, 1997.
8. Barrett, Craig R. “From Sand to Silicon: Manufacturing an Integrated Circuit,” Scientific American Special Issue: The Solid State Century, January 22, 1998.