nRF52840 Product Specification - Nordic Semiconductor · 2016-12-06 · 0 a lrck sck 5

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2016-12-05

nRF52840 Objective Product Specification v0.5Key features• Bluetooth 5 ready multiprotocol radio

• 32-bit ARM® Cortex®-M4F @ 64 MHz

104 dB link budget for Bluetooth low energy•

•

•

••

••••

•

•

•

• High speed SPI interface 32 MHz

• RAM mapped FIFO using EasyDMA• 12 bit /200K SPS ADC• I28 bit AES/ECB/CCM/AAR co-processor

• Single-ended antenna output (on-chip balun)

• Programmable peripheral interconnect (PPI)

• Quad SPI interface 32 MHz

• EasyDMA for all digital interfaces

• On-chip DC-DC buck converter

• Quadrature demodulator• Individual power management for all peripherals

• Internet of Things (IoT)

• Smart home sensors and controllers• Industrial IoT sensors and controllers

• Advanced wearables

• Connected watches• Advanced personal fitness devices

• Interactive entertainment devices

• Advanced Remote controls• Gaming controllers

Applications

• Bluetooth 5 data rate support: 2 Mbs, 1Mbs, 500 kbs, 125 kbs

• High speed 2 Mbs data rate

Full-speed 12 Mbs USB controller

NFC-A tag on-chip

Software stacks available as downloads

Application development independent of protocol stacks

Programmable output power from +8 dBm to -20 dBm-96 dBm Sensitivity for Bluetooth low energy

On-air compatible with nRF52, nRF51, nRF24L, and nRF24AP Series

ARM® TrustZone® Cryptocell 310 cryptographic accelerator

RSSI

Wide supply voltage range +5.5 v to 1.7 v

Full selection of interfaces SPI/UART/PWM

• Regulated supply for external components up to 25 mA

• Wearables with wireless payment• Connected health

• Virtual/Augmented Reality applications

Contents

Page 2

Contents

1 Revision history................................................................................... 92 About this document............................................................................................ 10

2.1 Peripheral naming and abbreviations................................................................................... 102.2 Register tables...................................................................................................................... 102.3 Registers............................................................................................................................... 11

3 Block diagram........................................................................................................124 Pin assignments.................................................................................................... 13

4.1 QIAA pin assignments.......................................................................................................... 135 Absolute maximum ratings.................................................................................. 166 Recommended operating conditions.................................................................. 177 CPU......................................................................................................................... 18

7.1 Floating point interrupt.......................................................................................................... 187.2 Electrical specification...........................................................................................................187.3 CPU and support module configuration................................................................................19

8 Memory................................................................................................................... 208.1 RAM - Random access memory...........................................................................................208.2 Flash - Non-volatile memory.................................................................................................208.3 Memory map......................................................................................................................... 218.4 Instantiation........................................................................................................................... 23

9 AHB multilayer.......................................................................................................2510 EasyDMA.............................................................................................................. 26

10.1 EasyDMA array list............................................................................................................. 2711 NVMC — Non-volatile memory controller......................................................... 28

11.1 Writing to flash.................................................................................................................... 2811.2 Erasing a page in flash.......................................................................................................2811.3 Writing to user information configuration registers (UICR)................................................. 2811.4 Erasing user information configuration registers (UICR).................................................... 2811.5 Erase all.............................................................................................................................. 2911.6 Cache.................................................................................................................................. 2911.7 Registers............................................................................................................................. 2911.8 Electrical specification.........................................................................................................32

12 FICR — Factory information configuration registers.......................................3312.1 Registers............................................................................................................................. 33

13 UICR — User information configuration registers........................................... 4413.1 Registers............................................................................................................................. 44

14 Peripheral interface............................................................................................. 5814.1 Peripheral ID....................................................................................................................... 5814.2 Peripherals with shared ID..................................................................................................5814.3 Peripheral registers............................................................................................................. 5914.4 Bit set and clear..................................................................................................................5914.5 Tasks................................................................................................................................... 5914.6 Events..................................................................................................................................6014.7 Shortcuts............................................................................................................................. 6014.8 Interrupts............................................................................................................................. 60

15 Debug and trace.................................................................................................. 6215.1 DAP - Debug Access Port..................................................................................................6215.2 CTRL-AP - Control Access Port......................................................................................... 6315.3 Debug interface mode.........................................................................................................6515.4 Real-time debug..................................................................................................................65

Contents

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15.5 Trace................................................................................................................................... 6516 POWER — Power supply....................................................................................67

16.1 Main supply......................................................................................................................... 6716.2 USB supply......................................................................................................................... 7216.3 System OFF mode..............................................................................................................7316.4 System ON mode............................................................................................................... 7416.5 RAM power control............................................................................................................. 7416.6 Reset................................................................................................................................... 7416.7 Retained registers............................................................................................................... 7516.8 Reset behavior.................................................................................................................... 7516.9 Registers............................................................................................................................. 7616.10 Electrical specification..................................................................................................... 139

17 CLOCK — Clock control...................................................................................14217.1 HFCLK clock controller..................................................................................................... 14217.2 LFCLK clock controller......................................................................................................14417.3 Registers........................................................................................................................... 14617.4 Electrical specification.......................................................................................................150

18 Power and clock management.........................................................................15318.1 Current consumption scenarios........................................................................................ 153

19 GPIO — General purpose input/output........................................................... 15519.1 Pin configuration............................................................................................................... 15519.2 GPIO located near the RADIO......................................................................................... 15719.3 Registers........................................................................................................................... 15719.4 Electrical specification.......................................................................................................198

20 GPIOTE — GPIO tasks and events..................................................................20120.1 Pin events and tasks........................................................................................................ 20120.2 Port event..........................................................................................................................20220.3 Tasks and events pin configuration.................................................................................. 20220.4 Registers........................................................................................................................... 20220.5 Electrical specification.......................................................................................................211

21 PPI — Programmable peripheral interconnect............................................... 21221.1 Pre-programmed channels................................................................................................21321.2 Registers........................................................................................................................... 213

22 RADIO — 2.4 GHz Radio.................................................................................. 24922.1 Packet configuration..........................................................................................................24922.2 Address configuration........................................................................................................25022.3 Data whitening.................................................................................................................. 25122.4 CRC...................................................................................................................................25122.5 Radio states...................................................................................................................... 25222.6 Transmit sequence............................................................................................................25222.7 Receive sequence.............................................................................................................25422.8 Received Signal Strength Indicator (RSSI).......................................................................25522.9 Interframe spacing.............................................................................................................25522.10 Device address match.................................................................................................... 25622.11 Bit counter....................................................................................................................... 25622.12 IEEE 802.15.4 Operation................................................................................................ 25722.13 EasyDMA.........................................................................................................................26422.14 Registers......................................................................................................................... 26522.15 Electrical specification..................................................................................................... 286

23 TIMER — Timer/counter....................................................................................29023.1 Capture..............................................................................................................................29123.2 Compare............................................................................................................................29123.3 Task delays....................................................................................................................... 29123.4 Task priority.......................................................................................................................29123.5 Registers........................................................................................................................... 29123.6 Electrical specification.......................................................................................................297

24 RTC — Real-time counter.................................................................................298

Contents

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24.1 Clock source..................................................................................................................... 29824.2 Resolution versus overflow and the PRESCALER........................................................... 29824.3 COUNTER register............................................................................................................29924.4 Overflow features.............................................................................................................. 29924.5 TICK event........................................................................................................................ 29924.6 Event control feature.........................................................................................................30024.7 Compare feature............................................................................................................... 30024.8 TASK and EVENT jitter/delay........................................................................................... 30224.9 Reading the COUNTER register.......................................................................................30424.10 Registers......................................................................................................................... 30424.11 Electrical specification..................................................................................................... 310

25 RNG — Random number generator................................................................ 31125.1 Bias correction.................................................................................................................. 31125.2 Speed................................................................................................................................ 31125.3 Registers........................................................................................................................... 31125.4 Electrical specification.......................................................................................................313

26 TEMP — Temperature sensor.......................................................................... 31426.1 Registers........................................................................................................................... 31426.2 Electrical specification.......................................................................................................319

27 ECB — AES electronic codebook mode encryption......................................32027.1 Shared resources..............................................................................................................32027.2 EasyDMA...........................................................................................................................32027.3 ECB data structure............................................................................................................32027.4 Registers........................................................................................................................... 32127.5 Electrical specification.......................................................................................................322

28 CCM — AES CCM mode encryption................................................................32328.1 Shared resources..............................................................................................................32328.2 Key-steam generatioin...................................................................................................... 32328.3 Encryption..........................................................................................................................32428.4 Decryption......................................................................................................................... 32428.5 AES CCM and RADIO concurrent operation....................................................................32528.6 Encrypting packets on-the-fly in radio transmit mode.......................................................32528.7 Decrypting packets on-the-fly in radio receive mode........................................................32628.8 CCM data structure...........................................................................................................32728.9 EasyDMA and ERROR event........................................................................................... 32828.10 Registers......................................................................................................................... 32828.11 Electrical specification..................................................................................................... 332

29 AAR — Accelerated address resolver.............................................................33329.1 Shared resources..............................................................................................................33329.2 EasyDMA...........................................................................................................................33329.3 Resolving a resolvable address........................................................................................33329.4 Use case example for chaining RADIO packet reception with address resolution using

AAR.......................................................................................................................................33429.5 IRK data structure.............................................................................................................33429.6 Registers........................................................................................................................... 33529.7 Electrical specification.......................................................................................................337

30 SPIM — Serial peripheral interface master with EasyDMA............................33830.1 SPI master transaction sequence.....................................................................................33830.2 Pin configuration............................................................................................................... 33930.3 Shared resources..............................................................................................................34030.4 EasyDMA...........................................................................................................................34030.5 Low power.........................................................................................................................34130.6 Registers........................................................................................................................... 34130.7 Electrical specification.......................................................................................................349

31 SPIS — Serial peripheral interface slave with EasyDMA...............................35131.1 Shared resources..............................................................................................................35131.2 EasyDMA...........................................................................................................................351

Contents

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31.3 SPI slave operation...........................................................................................................35231.4 Pin configuration............................................................................................................... 35331.5 Registers........................................................................................................................... 35431.6 Electrical specification.......................................................................................................362

32 TWIM — I2C compatible two-wire interface master with EasyDMA...............36432.1 Shared resources..............................................................................................................36532.2 EasyDMA...........................................................................................................................36532.3 Master write sequence......................................................................................................36532.4 Master read sequence...................................................................................................... 36632.5 Master repeated start sequence....................................................................................... 36732.6 Low power.........................................................................................................................36832.7 Master mode pin configuration......................................................................................... 36832.8 Registers........................................................................................................................... 36832.9 Electrical specification.......................................................................................................37532.10 Pullup resistor................................................................................................................. 376

33 TWIS — I2C compatible two-wire interface slave with EasyDMA..................37733.1 Shared resources..............................................................................................................37933.2 EasyDMA...........................................................................................................................37933.3 TWI slave responding to a read command.......................................................................37933.4 TWI slave responding to a write command...................................................................... 38033.5 Master repeated start sequence....................................................................................... 38133.6 Terminating an ongoing TWI transaction..........................................................................38233.7 Low power.........................................................................................................................38233.8 Slave mode pin configuration........................................................................................... 38233.9 Registers........................................................................................................................... 38333.10 Electrical specification..................................................................................................... 389

34 UARTE — Universal asynchronous receiver/transmitter with EasyDMA.... 39134.1 Shared resources..............................................................................................................39134.2 EasyDMA...........................................................................................................................39134.3 Transmission..................................................................................................................... 39234.4 Reception.......................................................................................................................... 39234.5 Error conditions................................................................................................................. 39434.6 Using the UARTE without flow control............................................................................. 39434.7 Parity and stop bit configuration....................................................................................... 39434.8 Low power.........................................................................................................................39534.9 Pin configuration............................................................................................................... 39534.10 Registers......................................................................................................................... 39534.11 Electrical specification..................................................................................................... 404

35 QDEC — Quadrature decoder..........................................................................40535.1 Sampling and decoding.................................................................................................... 40535.2 LED output........................................................................................................................ 40635.3 Debounce filters................................................................................................................ 40635.4 Accumulators.....................................................................................................................40735.5 Output/input pins............................................................................................................... 40735.6 Pin configuration............................................................................................................... 40735.7 Registers........................................................................................................................... 40835.8 Electrical specification.......................................................................................................414

36 SAADC — Successive approximation analog-to-digital converter............... 41536.1 Shared resources..............................................................................................................41536.2 Overview............................................................................................................................41536.3 Digital output..................................................................................................................... 41636.4 Analog inputs and channels..............................................................................................41736.5 Operation modes...............................................................................................................41736.6 EasyDMA...........................................................................................................................41936.7 Resistor ladder.................................................................................................................. 42036.8 Reference.......................................................................................................................... 42136.9 Acquisition time................................................................................................................. 42136.10 Limits event monitoring................................................................................................... 422

Contents

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36.11 Registers......................................................................................................................... 42336.12 Electrical specification..................................................................................................... 44736.13 Performance factors........................................................................................................449

37 COMP — Comparator........................................................................................45037.1 Shared resources..............................................................................................................45137.2 Differential mode............................................................................................................... 45137.3 Single-ended mode........................................................................................................... 45237.4 Pin configuration............................................................................................................... 45437.5 Registers........................................................................................................................... 45437.6 Electrical specification.......................................................................................................459

38 LPCOMP — Low power comparator................................................................46138.1 Shared resources..............................................................................................................46238.2 Pin configuration............................................................................................................... 46238.3 Registers........................................................................................................................... 46338.4 Electrical specification.......................................................................................................467

39 WDT — Watchdog timer................................................................................... 46839.1 Reload criteria................................................................................................................... 46839.2 Temporarily pausing the watchdog...................................................................................46839.3 Watchdog reset................................................................................................................. 46839.4 Registers........................................................................................................................... 46939.5 Electrical specification.......................................................................................................473

40 SWI — Software interrupts...............................................................................47440.1 Registers........................................................................................................................... 474

41 NFCT — Near field communication tag...........................................................47541.1 Overview............................................................................................................................47541.2 Operating states................................................................................................................47741.3 Pin configuration............................................................................................................... 47841.4 EasyDMA...........................................................................................................................47841.5 Frame assembler.............................................................................................................. 47941.6 Frame disassembler..........................................................................................................48041.7 Frame timing controller..................................................................................................... 48141.8 Collision resolution............................................................................................................ 48241.9 Antenna interface.............................................................................................................. 48341.10 NFCT antenna recommendations................................................................................... 48341.11 Battery protection............................................................................................................ 48441.12 References...................................................................................................................... 48441.13 Registers......................................................................................................................... 48441.14 Electrical specification..................................................................................................... 496

42 PDM — Pulse density modulation interface................................................... 49742.1 Master clock generator..................................................................................................... 49742.2 Module operation.............................................................................................................. 49742.3 Decimation filter................................................................................................................ 49842.4 EasyDMA...........................................................................................................................49842.5 Hardware example............................................................................................................ 49942.6 Pin configuration............................................................................................................... 49942.7 Registers........................................................................................................................... 50042.8 Electrical specification.......................................................................................................505

43 I2S — Inter-IC sound interface......................................................................... 50643.1 Mode..................................................................................................................................50643.2 Transmitting and receiving................................................................................................50643.3 Left right clock (LRCK)..................................................................................................... 50743.4 Serial clock (SCK).............................................................................................................50743.5 Master clock (MCK).......................................................................................................... 50843.6 Width, alignment and format.............................................................................................50843.7 EasyDMA...........................................................................................................................51043.8 Module operation.............................................................................................................. 51243.9 Pin configuration............................................................................................................... 513

Contents

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43.10 Registers......................................................................................................................... 51443.11 Electrical specification..................................................................................................... 521

44 MWU — Memory watch unit.............................................................................52244.1 Registers........................................................................................................................... 522

45 EGU — Event generator unit............................................................................54945.1 Registers........................................................................................................................... 54945.2 Electrical specification.......................................................................................................555

46 PWM — Pulse width modulation..................................................................... 55646.1 Wave counter.................................................................................................................... 55646.2 Decoder with EasyDMA.................................................................................................... 55946.3 Limitations......................................................................................................................... 56446.4 Pin configuration............................................................................................................... 56446.5 Registers........................................................................................................................... 56546.6 Electrical specification.......................................................................................................573

47 SPI — Serial peripheral interface master........................................................57447.1 Functional description....................................................................................................... 57447.2 Registers........................................................................................................................... 57747.3 Electrical specification.......................................................................................................580

48 TWI — I2C compatible two-wire interface....................................................... 58148.1 Functional description....................................................................................................... 58148.2 Master mode pin configuration......................................................................................... 58148.3 Shared resources..............................................................................................................58248.4 Master write sequence......................................................................................................58248.5 Master read sequence...................................................................................................... 58348.6 Master repeated start sequence....................................................................................... 58448.7 Low power.........................................................................................................................58548.8 Registers........................................................................................................................... 58548.9 Electrical specification.......................................................................................................589

49 UART — Universal asynchronous receiver/transmitter.................................59149.1 Functional description....................................................................................................... 59149.2 Pin configuration............................................................................................................... 59149.3 Shared resources..............................................................................................................59249.4 Transmission..................................................................................................................... 59249.5 Reception.......................................................................................................................... 59249.6 Suspending the UART...................................................................................................... 59349.7 Error conditions................................................................................................................. 59349.8 Using the UART without flow control................................................................................59449.9 Parity configuration............................................................................................................59449.10 Registers......................................................................................................................... 59449.11 Electrical specification..................................................................................................... 599

50 ACL — Access control lists............................................................................. 60050.1 Registers........................................................................................................................... 601

51 USBD — Universal serial bus device.............................................................. 60951.1 USB device states.............................................................................................................60951.2 USB terminology............................................................................................................... 61051.3 USB pins........................................................................................................................... 61151.4 USBD start-up sequence.................................................................................................. 61151.5 USB pull-up....................................................................................................................... 61251.6 USB reset..........................................................................................................................61251.7 USB suspend and resume................................................................................................61351.8 EasyDMA...........................................................................................................................61451.9 Control transfers................................................................................................................61551.10 Bulk and interrupt transactions....................................................................................... 61851.11 Isochronous transactions................................................................................................ 62051.12 USB register access limitations...................................................................................... 62251.13 Registers......................................................................................................................... 62351.14 Electrical specification..................................................................................................... 659

Contents

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52 QSPI — Quad serial peripheral interface........................................................ 66152.1 Configuring peripheral.......................................................................................................66152.2 Write operation..................................................................................................................66252.3 Read operation..................................................................................................................66252.4 Erase operation.................................................................................................................66252.5 Execute in place............................................................................................................... 66252.6 Sending custom instructions............................................................................................. 66352.7 Deep power-down mode...................................................................................................66452.8 Instruction set....................................................................................................................66452.9 Interface description..........................................................................................................66452.10 Registers......................................................................................................................... 66952.11 Electrical specification..................................................................................................... 677

53 CRYPTOCELL — ARM TrustZone CryptoCell 310..........................................67953.1 Standards.......................................................................................................................... 68053.2 Control interface................................................................................................................680

54 Mechanical specifications................................................................................ 68254.1 AQFN73 7 x 7 mm package.............................................................................................682

55 Ordering information.........................................................................................68355.1 Package marking.............................................................................................................. 68355.2 Box labels..........................................................................................................................68355.3 Order code........................................................................................................................ 68455.4 Code ranges and values...................................................................................................68455.5 Product options................................................................................................................. 685

56 Reference circuitry............................................................................................ 68656.1 Circuit configuration no. 1.................................................................................................68656.2 Circuit configuration no. 2.................................................................................................68756.3 Circuit configuration no. 3.................................................................................................68856.4 Circuit configuration no. 4.................................................................................................68956.5 Circuit configuration no. 5.................................................................................................69056.6 Circuit configuration no. 6.................................................................................................69156.7 PCB guidelines..................................................................................................................69256.8 PCB layout example......................................................................................................... 693

57 Liability disclaimer............................................................................................ 69657.1 RoHS and REACH statement...........................................................................................69657.2 Life support applications................................................................................................... 696

1 Revision history

Page 9

1 Revision history

Date Version DescriptionDecember 2016 0.5 First release

2 About this document

Page 10


This product specification is organized into chapters based on the modules and peripherals that are availablein this IC.

The peripheral descriptions are broken into separate sections that include the following information:

• A detailed functional description of the peripheral.• Register configuration for the peripheral.• Electrical specification tables providing the specified limits of the chip when tested under the conditions

defined in the Recommended operating conditions on page 17.

2.1 Peripheral naming and abbreviationsEvery peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used foridentification and reference. This name is used in chapter headings and references, and it will appear in theARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer to identifythe peripheral.

The peripheral instance name, which is different from the peripheral name, is constructed using theperipheral name followed by a numbered postfix starting with 0, for example TIMER0. A postfix is normallyonly used if a peripheral can be instantiated more than once. The peripheral instance name is also used inthe CMSIS to identify the peripheral instance.

2.2 Register tablesIndividual registers are described using register tables. These tables are built up of two sections. The firstthree colored rows describe the position and size of the different fields in the register. The following rowsdescribe the fields in more details.

2.2.1 Fields and valuesThe Id (Field Id) row specifies the bits that belong to the different fields in the register.

A blank space means that the field is reserved and read as undefined, and it must be written as 0 to secureforward compatibility. If a register is divided into more than one field, a unique field name is specified foreach field in the Field column.

If a field has enumerated values, then every value will be identified with a unique value id in the Value Idcolumn. Single-bit bit fields may, however, omit the Value Id when values can be substituted with a Booleantype enumerator range, for example, True/False, Disable/Enable, On/Off, and so on.

Values are usually provided as decimal or hexadecimal. Hex values have a '0x' prefix, decimal values haveno prefix.

The Value column can be populated in the following ways:

• Individual enumerated values, for example, 1, 3, 9.• Range of values, e.g. [0..4], indicating all values between and including 0 and 4.• Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or

alternatively the field’s translation and limitations are described in the text instead.

If two or more fields are closely related, the columns Value Id, Value, and Description may be omitted forall but the first field. Subsequent fields will indicate inheritance with '..'.

A feature marked Deprecated should not be used for new designs.


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2.3 Registers

Table 1: Register Overview

Register Offset Description

DUMMY 0x514 Example of a register controlling a dummy feature

2.3.1 DUMMY

Address offset: 0x514

Example of a register controlling a dummy feature

Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Id D D D D C C C B A A

Reset 0x00050002 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0

Id RW Field Value Id Value Description

A RW FIELD_A Example of a field with several enumerated values

Disabled 0 The example feature is disabled

NormalMode 1 The example feature is enabled in normal mode

ExtendedMode 2 The example feature is enabled along with extra functionality

B RW FIELD_B Example of a deprecated field Deprecated

Disabled 0 The override feature is disabled

Enabled 1 The override feature is enabled

C RW FIELD_C Example of a field with a valid range of values

ValidRange [2..7] Example of allowed values for this field

D RW FIELD_D Example of a field with no restriction on the values

3 Block diagram

Page 12

3 Block diagram

This block diagram illustrates the overall system. Arrows with white heads indicate signals that sharephysical pins with other signals.

nRF52840

AP

B0

AHB TO APB BRIDGE

RADIO

AHB Multi-Layer

CPU

ARM CORTEX-M4

AHB-AP

RNG

TEMPWDT

NVMC

ANT

POWERnRESETRTC [0..2]

PPI

TIMER [0..4]

NVIC

UICRFICR

SW-DP

CODE

EasyDMA master

QDEC

SAADC

GPIOTE

P0 (P0.0 – P0.31)

AIN0 – AIN7

LEDAB

UARTE [0]

SPIS [0..2]MOSIMISOCSN

COMP

EasyDMA

RXDTXD

CTSRTS

ETM

SysTick

TPIUTP

EasyDMA

LPCOMP

EasyDMAmaster

master

NFCTNFC1

NFC2

EasyDMA master

master

SWDIO

SWCLK

CTRL-AP

PWM[0..3]OUT0 – OUT3

I2S

MCKLRCKSCL

SDOUTSDIN

PDMCLKDIN

SCK

EasyDMA master

EasyDMA master

EasyDMA master

I-Cache

slav

e

slav

e

slav

e

slav

e

slav

e

mas

ter

CLOCK

XL2

XL1

XC2

XC1

USBD

D-

D+

EasyDMA master

VBUS

SPIM [0.2]

SCK

MISO

EasyDMA

MOSI

master

TWIM [0..1]SCL

SDA

EasyDMAmaster

QSPIIO3IO2IO1IO0

EasyDMAmasterCSNSCK

ECB

EasyDMAmaster

CCM

EasyDMAmaster

AAR

EasyDMAmaster

CryptoCell

DMAmaster

TWIS [0.1n]SCL

SDA

EasyDMAmaster

RAM0

slav

e

RAM1

slav

e

RAM2

slav

e

RAM3

slav

e

RAM4

slav

e

RAM5

slav

e

RAM6

slav

e

RAM7

slav

e

GPIO

slav

e

RAM8

slav

e

Figure 1: Block diagram

4 Pin assignments

Page 13

4 Pin assignments

This section describes the pin assignment and the pin functions.

This device provides flexibility when it comes to routing and configuration of the GPIO pins. However, somepins have recommendations for how the pin should be configured or what it should be used for. See Table 2:QIAA pin assignments on page 13 for more information about this.

4.1 QIAA pin assignmentsThis section describes the pin assignment and the pin functions.

Figure 2: QIAA pin assignments, top view

Table 2: QIAA pin assignments

Pin Name Function Description Recommended usage

A8 P0.31

AIN7

Digital I/O

Analog input

General purpose I/O

Analog input

Standard drive, low frequency I/O

only.

A10 P0.29

AIN5

Digital I/O

Analog input

General purpose I/O

Analog input


only.

A12 P0.02

AIN0

Digital I/O

Analog input

General purpose I/O

Analog input


only.

A14 P1.15 Digital I/O General purpose I/O Standard drive, low frequency I/O

only.


only.

A18 DEC2 Power 1.3 V regulator supply decoupling (Radio supply)


only.

A22 VDD Power Power supply

A23 XC2 Analog input Connection for 32 MHz crystal.

B1 VDD Power Power supply

B3 DCC Power DC/DC converter output

4 Pin assignments

Page 14


B5 DEC4 Power 1.3 V regulator supply decoupling

B7 VSS Power Ground

B9 P0.30

AIN6

Digital I/O

Analog input

General purpose I/O

Analog input


only.

B11 P0.28

AIN4

Digital I/O

Analog input

General purpose I/O

Analog input


only.

B13 P0.03

AIN1

Digital I/O

Analog input

General purpose I/O

Analog input


only.

B15 P1.14 Digital I/O General purpose I/O Standard drive, low frequency I/O

only.


only.


only.

B24 XC1 Analog input Connection for 32 MHz crystal

C1 DEC1 Power 1.1 V regulator supply decoupling

D2 P0.00

XL1

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal

D23 DEC3 Power Power supply, decoupling

E24 DEC2 Power 1.3 V regulator supply decoupling (Radio supply)

F2 P0.01

XL2

Digital I/O

Analog input

General purpose I/O

Connection for 32.768 kHz crystal

F23 VSS_PA Power Ground (Radio supply)

G1 P0.26 Digital I/O General purpose I/O

H2 P0.27 Digital I/O General purpose I/O

H23 ANT RF Single-ended radio antenna connection

J1 P0.04

AIN2

Digital I/O

Analog input

General purpose I/O

Analog input

J24 P0.10

NFC2

Digital I/O

NFC input

General purpose I/O

NFC antenna connection


only.

K2 P0.05

AIN3

Digital I/O

Analog input

General purpose I/O

Analog input

L1 P0.06 Digital I/O General purpose I/O

L24 P0.09

NFC1

Digital I/O

NFC input

General purpose I/O

NFC antenna connection


only.

M2 P0.07 Digital I/O General purpose I/O

N1 P0.08 Digital I/O General purpose I/O

N24 DEC5 Power 1.3 V regulator supply decoupling (flash supply)

P2 P1.08 Digital I/O General purpose I/O

P23 P1.07 Digital I/O General purpose I/O Standard drive, low frequency I/O

only.

R1 P1.09 Digital I/O General purpose I/O

R24 P1.06 Digital I/O General purpose I/O Standard drive, low frequency I/O

only.

T2 P0.11 Digital I/O General purpose I/O

T23 P1.05 Digital I/O General purpose I/O Standard drive, low frequency I/O

only.

U1 P0.12 Digital I/O General purpose I/O

U24 P1.04 Digital I/O General purpose I/O Standard drive, low frequency I/O

only.

V23 P1.03 Digital I/O General purpose I/O Standard drive, low frequency I/O

only.

W1 VDD Power Power supply

4 Pin assignments

Page 15


W24 P1.02 Digital I/O General purpose I/O Standard drive, low frequency I/O

only.

Y2 VDDH Power High voltage power supply

Y23 P1.01 Digital I/O General purpose I/O Standard drive, low frequency I/O

only.

AA24 SWDCLK Debug Serial wire debug clock input for debug and

programming.

AB2 DCCH Power DC/DC converter output

AC5 DECUSB Power Decoupling for USB 3.3 V

AC9 P0.14 Digital I/O General purpose I/O


AC13 P0.18

nRESET

Digital I/O General purpose I/O

Configurable as system RESET

QSPI/CSN

AC15 P0.19 Digital I/O General purpose I/O QSPI/SCK

AC17 P0.21 Digital I/O General purpose I/O QSPI

AC19 P0.23 Digital I/O General purpose I/O QSPI


AC24 SWDIO Debug Debug serial data

AD2 VBUS Power 5 V input for USB 3.3 V regulator

AD4 D- Digital I/O USB D- USB

AD6 D+ Digital I/O USB D+ USB

AD8 P0.13 Digital I/O General purpose I/O



AD14 VDD Power Power supply


AD18 P0.22 Digital I/O General purpose I/O QSPI


AD22 P1.00 Digital I/O General purpose I/O QSPI

AD23 VDD Power Flash supply pad

Bottom of chip

Die pad VSS Power Ground pad. Exposed die pad must be connected to

ground (VSS) for proper device operation.

Important: For more information on Standard drive, see GPIO — General purpose input/output onpage 155. Low frequency I/O is signals with a frequency up to 10 kHz.

5 Absolute maximum ratings

Page 16

5 Absolute maximum ratings

Maximum ratings are the extreme limits to which the chip can be exposed for a limited amount of timewithout permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time mayaffect the reliability of the device.

Table 3: Absolute maximum ratings

Note Min. Max. UnitSupply voltagesVDD -0.3 +3.9 VVDDH -0.3 +5.8 VVBUS -0.3 +5.8 VVSS 0 VI/O pin voltageVI/O, VDD ≤3.6 V -0.3 VDD + 0.3 V VVI/O, VDD >3.6 V -0.3 3.9 V VNFC antenna pin currentINFC1/2 80 mARadioRF input level 10 dBmEnvironmental (AQFN package)Storage temperature -40 +125 °CMSL Moisture Sensitivity Level 2ESD HBM Human Body Model 4 kVESD CDMQF Charged Device Model

(AQFN73, 7×7 mm package)

750 V

Flash memoryEndurance 10 000 Write/erase cyclesRetention 10 years at 40°C

6 Recommended operating conditions

Page 17

6 Recommended operating conditions

The operating conditions are the physical parameters that the chip can operate within.

Table 4: Recommended operating conditions

Symbol Parameter Notes Min. Nom. Max. UnitsVDD VDD supply voltage, independent of DCDC enable 1.7 3.0 3.6 VVDDH VDDH supply voltage, independent of DCDC

enable2.5 3.7 5.5 V

VBUS VBUS USB supply voltage 4.35 5 5.5 VtR_VDD Supply rise time (0 V to 1.7 V) 60 mstR_VDDH Supply rise time (0 V to 3.7 V) 100 msTA Operating temperature -40 25 85 °C

Important: The on-chip power-on reset circuitry may not function properly for rise times longer thanthe specified maximum.

7 CPU

Page 18

7 CPU

The ARM® Cortex®-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb®-2technology) that implements a superset of 16 and 32-bit instructions to maximize code density andperformance.

This processor implements several features that enable energy-efficient arithmetic and high-performancesignal processing, including:

• Digital signal processing (DSP) instructions• Single-cycle multiply and accumulate (MAC) instructions• Hardware divide• 8- and 16-bit single instruction multiple data (SIMD) instructions• Single-precision floating-point unit (FPU)

The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for theARM Cortex processor series is implemented and available for the M4 CPU.

Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handlingevents at configurable priority levels via the nested vectored interrupt controller (NVIC).

Executing code from flash will have a wait state penalty on the nRF52 series. An instruction cache can beenabled to minimize flash wait states when fetching instructions. For more information on cache, see Cacheon page 29. The section Electrical specification on page 18 shows CPU performance parametersincluding wait states in different modes, CPU current and efficiency, and processing power and efficiencybased on the CoreMark® benchmark.

7.1 Floating point interruptThe floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow, which inturn will trigger the FPU interrupt.

See Instantiation on page 23 for more information about the exceptions triggering the FPU interrupt.

To clear the IRQ (interrupt request) line when an exception has occurred, the relevant exception bit withinthe floating-point status and control register (FPSCR) needs to be cleared. For more information about theFPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide.

7.2 Electrical specification

7.2.1 CPU performance

The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU isexecuting the CoreMark™ benchmark. It includes power regulator and clock base currents. All other blocksare IDLE.

Symbol Description Min. Typ. Max. Units

WFLASH CPU wait states, running CoreMark from flash, cache disabled 2

WFLASHCACHE CPU wait states, running CoreMark from flash, cache enabled 3

WRAM CPU wait states, running CoreMark from RAM 0

IDDFLASHCACHE CPU current, running CoreMark from flash, cache enabled, LDO 6.5 mA

IDDFLASHCACHEDCDC CPU current, running CoreMark from flash, cache enabled,

DCDC 3V

3.6 mA

IDDFLASH CPU current, running CoreMark from flash, cache disabled, LDO mA

IDDFLASHDCDC CPU current, running CoreMark from flash, cache disabled,

DCDC 3V

mA

IDDRAM CPU current, running CoreMark from RAM, LDO mA

7 CPU

Page 19

Symbol Description Min. Typ. Max. Units

IDDRAMDCDC CPU current, running CoreMark from RAM, DCDC 3V mA

IDDFLASH/MHz CPU efficiency, running CoreMark from flash, cache enabled,

LDO

102 µA/

MHz

IDDFLASHDCDC/MHz CPU efficiency, running CoreMark from flash, cache enabled,

DCDC 3V

56 µA/

MHz

CMFLASH CoreMark, running CoreMark from flash, cache enabled 212 CoreMark

CMFLASH/MHz CoreMark per MHz, running CoreMark from flash, cache

enabled

3.3 CoreMark/

MHz

CMFLASH/mA CoreMark per mA, running CoreMark from flash, cache enabled,

DCDC 3V

59 CoreMark/

mA

7.3 CPU and support module configurationThe ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on thedevice.Option / Module Description ImplementedCore optionsNVIC Nested vector interrupt controller 37 vectorsPRIORITIES Priority bits 3WIC Wakeup interrupt controller NOEndianness Memory system endianness Little endianBit-banding Bit banded memory NODWT Data watchpoint and trace YESSysTick System tick timer YESModulesMPU Memory protection unit YESFPU Floating-point unit YESDAP Debug access port YESETM Embedded trace macrocell YESITM Instrumentation trace macrocell YESTPIU Trace port interface unit YESETB Embedded trace buffer NOFPB Flash patch and breakpoint unit YESHTM AMBA™ AHB trace macrocell NO

8 Memory

Page 20

8 Memory

The nRF52840 contains 1 MB of flash and 256 kB of RAM that can be used for code and data storage.

The CPU and the peripherals having EasyDMA can access memory via the AHB multilayer interconnect.

The CPU is also able to access peripherals via the AHB multilayer interconnect, as illustrated in Figure 3:Memory layout on page 20.

RAM3AHB slave

RAM2AHB slave

RAM1AHB slave

RAM0AHB slave

RAM7AHB slave

RAM6AHB slave

RAM5AHB slave

RAM4AHB slave

AHB multilayer interconnect

AH

B

slav

e

Page 0

Page 1

Page 2

Page 3..254

Page 255

0x0000 0000

0x0000 2000

0x0000 3000

0x000F F000

FlashICODE/DCODE

AH

B

slav

e

NV

MC

ICODE

DCODE

Peripheral

EasyDMA

DM

A b

us

Peripheral

EasyDMA

DM

A b

us

CPU

ARM Cortex-M4S

yste

m b

us

ICO

DE

DC

OD

E

AHB2APB

AHB

APB

Block 0

Block 1

Block 2..6

Block 7

0x0000 0200

0x0000 0400

0x0000 1000

0x0000 0E00

I-Cac

he

0x2000 0000

0x2100 1000

0x2000 2000

0x2000 3000

0x2000 4000

0x2000 5000

0x2000 6000

0x2000 7000Section 0

Section 1

Section 0

Section 1

Section 0

Section 1

Section 0

Section 1

0x2000 8000

0x2000 9000

0x2000 A000

0x2000 B000

0x2000 C000

0x2000 D000

0x2000 E000

0x2000 F000Section 0

Section 1

Section 0

Section 1

Section 0

Section 1

Section 0

Section 1

Data RAMSystem

0x0080 0000

0x0080 1000

0x0080 2000

0x0080 3000

0x0080 4000

0x0080 5000

0x0080 6000

0x0080 7000

0x0080 8000

0x0080 9000

0x0080 A000

0x0080 B000

0x0080 C000

0x0080 D000

0x0080 E000

0x0080 F000

Code RAMICODE / DCODE

Section 0

Section 1

Section 2

Section 3

Section 4

Section 5

0x2001 0000 0x0081 0000

0x2001 8000 0x0081 8000

0x2002 0000 0x0082 0000

0x2002 8000 0x0082 8000

0x2003 0000 0x0083 0000

0x2003 8000 0x0083 8000

RAM8AHB slave

Figure 3: Memory layout

See AHB multilayer on page 25 and EasyDMA on page 26 for more information about the AHBmultilayer interconnect and the EasyDMA.

The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to theapplication to partition the RAM within these regions so that one does not corrupt the other.

8.1 RAM - Random access memoryThe RAM interface is divided into 9 RAM AHB slaves.

RAM AHB slave 0-7 is connected to 2x4 kB RAM sections each and RAM AHB slave 8 is connected to 6x32kB sections, as shown in Figure 3: Memory layout on page 20.

Each of the RAM sections have separate power control for System ON and System OFF mode operation,which is configured via RAM register (see the POWER — Power supply on page 67).

8.2 Flash - Non-volatile memoryThe flash can be read an unlimited number of times by the CPU, but it has restrictions on the number oftimes it can be written and erased and also on how it can be written.

8 Memory

Page 21

Writing to flash is managed by the non-volatile memory controller (NVMC), see NVMC — Non-volatilememory controller on page 28.

The flash is divided into 256x4 kB pages that can be accessed by the CPU via both the ICODE and DCODEbuses as shown in Figure 3: Memory layout on page 20. Each page is divided into 8 blocks.

8.3 Memory mapThe complete memory map is shown in Figure 4: Memory map on page 22. As described in Memory onpage 20, Code RAM and the Data RAM are the same physical RAM.

8 Memory

Page 22

Device

Device

Device

RAM

RAM

Peripheral

SRAM

Code

Private peripheral bus

AHB peripherals

APB peripherals

UICRFICR

Data RAM

Code RAMFlash

0xFFFFFFFF

0x00000000

0x20000000

0x40000000

0x60000000

0x80000000

0xA0000000

0xC0000000

0xE0000000

0x00000000

0x10000000

0x40000000

0x50000000

0xE0000000

0x00800000

0x10001000

0x20000000

XIP0x120000000x19FFFFFF

System address map Address map

Figure 4: Memory map

8 Memory

Page 23

8.4 Instantiation

Table 5: Instantiation table

ID Base Address Peripheral Instance Description

0 0x40000000 CLOCK CLOCK Clock control

0 0x40000000 POWER POWER Power control

1 0x40001000 RADIO RADIO 2.4 GHz radio

2 0x40002000 UART UART0 Universal asynchronous receiver/transmitter Deprecated

2 0x40002000 UARTE UARTE0 Universal asynchronous receiver/transmitter with EasyDMA, unit 0

3 0x40003000 TWIM TWIM0 Two-wire interface master 0

3 0x40003000 TWIS TWIS0 Two-wire interface slave 0

3 0x40003000 SPIS SPIS0 SPI slave 0

3 0x40003000 SPI SPI0 SPI master 0 Deprecated

3 0x40003000 SPIM SPIM0 SPI master 0

3 0x40003000 TWI TWI0 Two-wire interface master 0 Deprecated

4 0x40004000 TWI TWI1 Two-wire interface master 1 Deprecated



4 0x40004000 TWIM TWIM1 Two-wire interface master 1

4 0x40004000 TWIS TWIS1 Two-wire interface slave 1


5 0x40005000 NFCT NFCT Near field communication tag

6 0x40006000 GPIOTE GPIOTE GPIO tasks and events

7 0x40007000 SAADC SAADC Analog to digital converter

8 0x40008000 TIMER TIMER0 Timer 0

9 0x40009000 TIMER TIMER1 Timer 1

10 0x4000A000 TIMER TIMER2 Timer 2

11 0x4000B000 RTC RTC0 Real-time counter 0

12 0x4000C000 TEMP TEMP Temperature sensor

13 0x4000D000 RNG RNG Random number generator

14 0x4000E000 ECB ECB AES electronic code book (ECB) mode block encryption

15 0x4000F000 CCM CCM AES counter with CBC-MAC (CCM) mode block encryption

15 0x4000F000 AAR AAR Accelerated address resolver

16 0x40010000 WDT WDT Watchdog timer

17 0x40011000 RTC RTC1 Real-time counter 1

18 0x40012000 QDEC QDEC Quadrature decoder

19 0x40013000 COMP COMP General purpose comparator

19 0x40013000 LPCOMP LPCOMP Low power comparator

20 0x40014000 SWI SWI0 Software interrupt 0

20 0x40014000 EGU EGU0 Event generator unit 0











26 0x4001A000 TIMER TIMER3 Timer 3

27 0x4001B000 TIMER TIMER4 Timer 4

28 0x4001C000 PWM PWM0 Pulse width modulation unit 0

29 0x4001D000 PDM PDM Pulse Density modulation (digital microphone) interface

30 0x4001E000 ACL ACL Access control lists

30 0x4001E000 NVMC NVMC Non-volatile memory controller

8 Memory

Page 24

ID Base Address Peripheral Instance Description

31 0x4001F000 PPI PPI Programmable peripheral interconnect

32 0x40020000 MWU MWU Memory watch unit

33 0x40021000 PWM PWM1 Pulse width modulation unit 1

34 0x40022000 PWM PWM2 Pulse width modulation unit 2




36 0x40024000 RTC RTC2 Real-time counter 2

37 0x40025000 I2S I2S Inter-IC sound interface

38 0x40026000 FPU FPU FPU interrupt

39 0x40027000 USBD USBD Universal serial bus device

40 0x40028000 UARTE UARTE1 Universal asynchronous receiver/transmitter with EasyDMA, unit 1

41 0x40029000 QSPI QSPI External memory interface

43 0x4002B000 SPIM SPIM3 SPI master 3

45 0x4002D000 PWM PWM3 Pulse width modulation unit 3

0 0x50000000 GPIO GPIO General purpose input and output Deprecated

0 0x50000000 GPIO P0 General purpose input and output, port 0

0 0x50000300 GPIO P1 General purpose input and output, port 1

42 0x5002A000 CRYPTOCELL CRYPTOCELL CryptoCell subsystem control interface

N/A 0x10000000 FICR FICR Factory information configuration

N/A 0x10001000 UICR UICR User information configuration

9 AHB multilayer

Page 25

9 AHB multilayer

AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access isresolved using priorities.

Each bus master is connected to the slave devices using an interconnection matrix. The bus masters areassigned priorities. Priorities are used to resolve access when two (or more) bus masters request access tothe same slave device. The following applies:

• If two (or more) bus masters request access to the same slave device, the master with the highest priorityis granted the access first.

• Bus masters with lower priority are stalled until the higher priority master has completed its transaction.• If the higher priority master pauses at any point during its transaction, the lower priority master in queue is

temporarily granted access to the slave device until the higher priority master resumes its activity.• Bus masters that have the same priority are mutually exclusive, thus cannot be used concurrently.

Below is a list of bus masters in the system and their priorities.

Table 6: AHB bus masters (listed in priority order, highest to lowest)

Bus master name DescriptionCPUCTRL-APUSBCRYPTOCELLSPIM1/SPIS1/TWIM1/TWIS1 Same priority and mutually exclusiveRADIOCCM/ECB/AAR Same priority and mutually exclusiveSAADCUARTE0SPIM0/SPIS0/TWIM0/TWIS0 Same priority and mutually exclusiveSPIM2/SPIS2 Same priority and mutually exclusiveNFCTI2SPDMPWM0PWM1PWM2QSPIPWM3UARTE1

Defined bus masters are the CPU and the peripherals with implemented EasyDMA, and the available slavesare RAM AHB slaves. How the bus masters and slaves are connected using the interconnection matrix isillustrated in Memory on page 20.

10 EasyDMA

Page 26

10 EasyDMA

EasyDMA is an easy-to-use direct memory access module that some peripherals implement to gain directaccess to Data RAM.

The EasyDMA is an AHB bus master similar to the CPU and it is connected to the AHB multilayerinterconnect for direct access to the Data RAM. The EasyDMA is not able to access the flash.

A peripheral can implement multiple EasyDMA instances, for example to provide a dedicated channel forreading data from RAM into the peripheral at the same time as a second channel is dedicated for writing datato the RAM from the peripheral. This concept is illustrated in Figure 5: EasyDMA example on page 26

Peripheral

READER

PeripheralCore

AHB Multilayer

AHB

WRITER

AHB

RAM

RAM

RAM

EasyDMA

EasyDMA

Figure 5: EasyDMA example

An EasyDMA channel is usually exposed to the user in the form illustrated below, but some variations mayoccur:

READERBUFFER_SIZE 5 WRITERBUFFER_SIZE 6

uint8_t readerBuffer[READERBUFFER_SIZE] __at__ 0x20000000; uint8_t writerBuffer[WRITERBUFFER_SIZE] __at__ 0x20000005;

// Configuring the READER channel MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE; MYPERIPHERAL->READER.PTR = &readerBuffer;

// Configure the WRITER channel MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE; MYPERIPHERAL->WRITER.PTR = &writerBuffer;

This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels, onefor reading, called READER, and one for writing, called WRITER. When the peripheral is started, it is hereassumed that the peripheral will read 5 bytes from the readerBuffer located in RAM at address 0x20000000,process the data and then write no more than 6 bytes back to the writerBuffer located in RAM at address0x20000005. The memory layout of these buffers is illustrated in Figure 6: EasyDMA memory layout on page27.

10 EasyDMA

Page 27

readerBuffer[0] readerBuffer[1] readerBuffer[2] readerBuffer[3]

readerBuffer[4] writerBuffer[0] writerBuffer[1] writerBuffer[2]

writerBuffer[3] writerBuffer[4] writerBuffer[5]

0x20000000

0x20000004

0x20000008

Figure 6: EasyDMA memory layout

The EasyDMA channel's MAXCNT register cannot be specified larger than the actual size of the buffer. If,for example, the WRITER.MAXCNT register is specified larger than the size of the writerBuffer, the WRITEREasyDMA channel may overflow the writerBuffer.

After the peripheral has completed the EasyDMA transfer, the CPU can read the EasyDMA channel'sAMOUNT register to see how many bytes that were transferred, e.g. it is possible for the CPU to read theMYPERIPHERAL->WRITER.AMOUNT register to see how many bytes the WRITER wrote to RAM.

10.1 EasyDMA array listThe EasyDMA is able to operate in a mode called array list.

The EasyDMA array list can be represented by the data structure ArrayList_type illustrated in the codeexample below.

This data structure includes only a buffer with size equal to READER.MAXCNT. EasyDMA will use theREADER.MAXCNT register to determine when the buffer is full.

This array list does not provide a mechanism to explicitly specify where the next item in the list is located.Instead, it assumes that the list is organized as a linear array where items are located one after the other inRAM.

#define BUFFER_SIZE 4

typedef struct ArrayList { uint8_t buffer[BUFFER_SIZE]; } ArrayList_type;

ArrayList_type ReaderList[3];

READER.MAXCNT = BUFFER_SIZE; READER.PTR = &ReaderList;

buffer[0] buffer[1]0x20000000 : ReaderList[0]

0x20000004 : ReaderList[1]

0x20000008 : ReaderList[2]

buffer[2] buffer[3]

READER.PTR = &ReaderList

buffer[0] buffer[1] buffer[2] buffer[3]

buffer[0] buffer[1] buffer[2] buffer[3]

Figure 7: EasyDMA array list

11 NVMC — Non-volatile memory controller

Page 28


The non-volatile memory controller (NVMC) is used for writing and erasing the internal flash memory and theUICR.

Before a write can be performed, the NVMC must be enabled for writing in CONFIG.WEN. Similarly, beforean erase can be performed, the NVMC must be enabled for erasing in CONFIG.EEN, see CONFIG on page30. The user must make sure that writing and erasing are not enabled at the same time. Failing to do somay result in unpredictable behavior.

11.1 Writing to flashWhen writing is enabled, the flash is written by writing a full 32-bit word to a word-aligned address in theflash.

The NVMC is only able to write '0' to bits in the flash that are erased, that is, set to '1'. It cannot write back abit to '1'.

As illustrated in Memory on page 20, the flash is divided into multiple pages that are further divided intomultiple blocks. The same block in the flash can only be written nWRITE number of times before an erasemust be performed using ERASEPAGE or ERASEALL. See the memory size and organization in Memory onpage 20 for block size.

Only full 32-bit words can be written to flash using the NVMC interface. To write less than 32 bits to flash,write the data as a word, and set all the bits that should remain unchanged in the word to '1'. Note that therestriction about the number of writes (see above) still applies in this case.

The time it takes to write a word to the flash is specified by tWRITE. The CPU is halted if the CPU executescode from the flash while the NVMC is writing to the flash.

Only word-aligned writes are allowed. Byte or half-word-aligned writes will result in a hard fault.

11.2 Erasing a page in flashWhen erase is enabled, the flash can be erased page by page using the ERASEPAGE register.

After erasing a flash page, all bits in the page are set to '1'. The time it takes to erase a page is specified bytERASEPAGE. The CPU is halted if the CPU executes code from the flash while the NVMC performs the eraseoperation.

11.3 Writing to user information configuration registers (UICR)User information configuration registers (UICR) are written in the same way as flash. After UICR has beenwritten, the new UICR configuration will only take effect after a reset.

UICR can only be written nWRITE number of times before an erase must be performed using ERASEUICR orERASEALL.

The time it takes to write a word to the UICR is specified by tWRITE. The CPU is halted if the CPU executescode from the flash while the NVMC is writing to the UICR.

11.4 Erasing user information configuration registers (UICR)When erase is enabled, UICR can be erased using the ERASEUICR register.

After erasing UICR all bits in UICR are set to '1'. The time it takes to erase UICR is specified by tERASEPAGE.The CPU is halted if the CPU executes code from the flash while the NVMC performs the erase operation.


Page 29

11.5 Erase allWhen erase is enabled, the whole flash and UICR can be erased in one operation by using the ERASEALLregister. ERASEALL will not erase the factory information configuration registers (FICR).

The time it takes to perform an ERASEALL command is specified by tERASEALL The CPU is halted if the CPUexecutes code from the flash while the NVMC performs the erase operation.

11.6 CacheAn instruction cache (I-Cache) can be enabled for the ICODE bus in the NVMC.

See the Memory map in Memory map on page 21 for the location of flash.

A cache hit is an instruction fetch from the cache, and it has a 0 wait-state delay. The number of wait-statesfor a cache miss, where the instruction is not available in the cache and needs to be fetched from flash,depends on the processor frequency and is shown in CPU on page 18

Enabling the cache can increase CPU performance and reduce power consumption by reducing the numberof wait cycles and the number of flash accesses. This will depend on the cache hit rate. Cache will use somecurrent when enabled. If the reduction in average current due to reduced flash accesses is larger than thecache power requirement, the average current to execute the program code will reduce.

When disabled, the cache does not use current and does not retain its content.

It is possible to enable cache profiling to analyze the performance of the cache for your program using theICACHECNF register. When profiling is enabled, the IHIT and IMISS registers are incremented for everyinstruction cache hit or miss respectively. The hit and miss profiling registers do not wrap around afterreaching the maximum value. If the maximum value is reached, consider profiling for a shorter duration to getcorrect numbers.

11.7 Registers

Table 7: Instances

Base address Peripheral Instance Description Configura

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nRF52840 Product Specification - Nordic Semiconductor · 2016-12-06 · 0 a lrck sck 5