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All rights reserved.Reproduction in whole or in part is prohibited without the prior written permission of the copyright holder.
201 -07-06
nRF52 40 Product Specification 1
5 1 Mbps (BLE)
+8 dBm TX power (down to -20 dBm in 4 dB steps)On-air compatible with nRF52, nRF51, nRF24L and nRF24AP SeriesSupported data rates:
ended output (on-chip balun)98
21256Watchpoint and trace debug modules (DWT, ETM and ITM)
On-chip DC/DC and LDO regulators with automated low current modes
A ed peripheral power management
and with support for concurrent multi-protocol
4x sAudio peripherals: I2S, d5Up to 4x SPI masters/3x s sUp to 2x w s s2x
3 s
A 73 7 7
Advanced c
ulti-touch trackpad
Health/fitness sensor and monitor devicesWireless payment enabled devices
Interactive entertainment devices Remote controls Gaming controllers
Bluetooth 5: 2 Mbps, 1 Mbps, 500 kbps, 125 kbpsIEEE 802.15.4-2006: 250 kbpsProprietary 2.4 GHz: 2 Mbps, 1 Mbps
• ARM® Cortex®-M4 32-bit processor with FPU, 64 MHz
Regulated s for external components from 8 to 3
to 5.5
4
Advanced on-chip interfacesUSB 2.0 full speed (12 Mbps) controllerQSPI 32 MHz interfaceHigh speed 32 MHz SPIType 2 near field communication (NFC-A) tag with wake-on field
Touch-to-pair support
Key features Applications
Programmable peripheral interconnect (PPI)48 general purpose I/O pinsEasyDMA automated data transfer without CPU processing on peripherals
15 low-power with wake-up from System OFF mode
Advanced wearables
Internet of things (IoT) Smart home sensors and controllers Industrial IoT sensors and controllers
103 125 kbps BLE (long range)
HW accelerated securityARM® TrustZone® Cryptocell 310 cryptographic accelerator128 bit AES/ECB/CCM/AAR co-processor (on-the-fly packet encryption)
5, IEEE 802.15.4-2006, 2.4 GHz transceiver
1 MB flash/256 kB RAM
Contents
Page 2
Contents
1 Revision history................................................................................... 92 About this document............................................................................................ 10
2.1 Document naming and status...............................................................................................102.2 Peripheral naming and abbreviations................................................................................... 102.3 Register tables...................................................................................................................... 102.4 Registers............................................................................................................................... 11
3 Block diagram........................................................................................................124 Pin assignments.................................................................................................... 13
4.1 QIAA pin assignments.......................................................................................................... 135 Absolute maximum ratings.................................................................................. 166 Recommended operating conditions.................................................................. 177 CPU......................................................................................................................... 18
7.1 Floating point interrupt.......................................................................................................... 187.2 Electrical specification...........................................................................................................187.3 CPU and support module configuration................................................................................19
8 Memory................................................................................................................... 208.1 RAM - Random access memory...........................................................................................208.2 Flash - Non-volatile memory.................................................................................................208.3 Memory map......................................................................................................................... 218.4 Instantiation........................................................................................................................... 23
9 AHB multilayer.......................................................................................................2510 EasyDMA.............................................................................................................. 26
10.1 EasyDMA array list............................................................................................................. 2711 NVMC — Non-volatile memory controller......................................................... 28
11.1 Writing to flash.................................................................................................................... 2811.2 Erasing a page in flash.......................................................................................................2811.3 Writing to user information configuration registers (UICR)................................................. 2811.4 Erasing user information configuration registers (UICR).................................................... 2811.5 Erase all.............................................................................................................................. 2911.6 Cache.................................................................................................................................. 2911.7 Registers............................................................................................................................. 2911.8 Electrical specification.........................................................................................................32
12 FICR — Factory information configuration registers.......................................3312.1 Registers............................................................................................................................. 33
13 UICR — User information configuration registers........................................... 4413.1 Registers............................................................................................................................. 44
14 Peripheral interface............................................................................................. 5914.1 Peripheral ID....................................................................................................................... 5914.2 Peripherals with shared ID..................................................................................................5914.3 Peripheral registers............................................................................................................. 6014.4 Bit set and clear..................................................................................................................6014.5 Tasks................................................................................................................................... 6014.6 Events..................................................................................................................................6014.7 Shortcuts............................................................................................................................. 6114.8 Interrupts............................................................................................................................. 61
15 Debug and trace.................................................................................................. 6215.1 DAP - Debug access port...................................................................................................6215.2 CTRL-AP - Control access port..........................................................................................6315.3 Debug interface mode.........................................................................................................64
Contents
Page 3
15.4 Real-time debug..................................................................................................................6515.5 Trace................................................................................................................................... 65
16 POWER — Power supply....................................................................................6616.1 Main supply......................................................................................................................... 6616.2 USB supply......................................................................................................................... 7116.3 System OFF mode..............................................................................................................7216.4 System ON mode............................................................................................................... 7316.5 RAM power control............................................................................................................. 7316.6 Reset................................................................................................................................... 7316.7 Retained registers............................................................................................................... 7416.8 Reset behavior.................................................................................................................... 7416.9 Registers............................................................................................................................. 7516.10 Electrical specification..................................................................................................... 138
17 CLOCK — Clock control...................................................................................14117.1 HFCLK clock controller..................................................................................................... 14117.2 LFCLK clock controller......................................................................................................14317.3 Registers........................................................................................................................... 14517.4 Electrical specification.......................................................................................................150
18 Power and clock management.........................................................................15218.1 Current consumption scenarios........................................................................................ 152
19 GPIO — General purpose input/output........................................................... 15419.1 Pin configuration............................................................................................................... 15419.2 GPIO located near the RADIO......................................................................................... 15619.3 Registers........................................................................................................................... 15619.4 Electrical specification.......................................................................................................197
20 GPIOTE — GPIO tasks and events..................................................................20020.1 Pin events and tasks........................................................................................................ 20020.2 Port event..........................................................................................................................20120.3 Tasks and events pin configuration.................................................................................. 20120.4 Registers........................................................................................................................... 20120.5 Electrical specification.......................................................................................................211
21 PPI — Programmable peripheral interconnect............................................... 21221.1 Pre-programmed channels................................................................................................21321.2 Registers........................................................................................................................... 213
22 RADIO — 2.4 GHz Radio.................................................................................. 24922.1 Packet configuration..........................................................................................................24922.2 Address configuration........................................................................................................25022.3 Data whitening.................................................................................................................. 25122.4 CRC...................................................................................................................................25122.5 Radio states...................................................................................................................... 25222.6 Transmit sequence............................................................................................................25322.7 Receive sequence.............................................................................................................25422.8 Received Signal Strength Indicator (RSSI).......................................................................25622.9 Interframe spacing.............................................................................................................25622.10 Device address match.................................................................................................... 25722.11 Bit counter....................................................................................................................... 25722.12 IEEE 802.15.4 Operation................................................................................................ 25822.13 EasyDMA.........................................................................................................................26522.14 Registers......................................................................................................................... 26622.15 Electrical specification..................................................................................................... 287
23 TIMER — Timer/counter....................................................................................29223.1 Capture..............................................................................................................................29323.2 Compare............................................................................................................................29323.3 Task delays....................................................................................................................... 29323.4 Task priority.......................................................................................................................29323.5 Registers........................................................................................................................... 29323.6 Electrical specification.......................................................................................................299
Contents
Page 4
24 RTC — Real-time counter.................................................................................30024.1 Clock source..................................................................................................................... 30024.2 Resolution versus overflow and the PRESCALER........................................................... 30024.3 COUNTER register............................................................................................................30124.4 Overflow features.............................................................................................................. 30124.5 TICK event........................................................................................................................ 30124.6 Event control feature.........................................................................................................30224.7 Compare feature............................................................................................................... 30224.8 TASK and EVENT jitter/delay........................................................................................... 30424.9 Reading the COUNTER register.......................................................................................30624.10 Registers......................................................................................................................... 30624.11 Electrical specification..................................................................................................... 312
25 RNG — Random number generator................................................................ 31325.1 Bias correction.................................................................................................................. 31325.2 Speed................................................................................................................................ 31325.3 Registers........................................................................................................................... 31325.4 Electrical specification.......................................................................................................315
26 TEMP — Temperature sensor.......................................................................... 31626.1 Registers........................................................................................................................... 31626.2 Electrical specification.......................................................................................................321
27 ECB — AES electronic codebook mode encryption......................................32227.1 Shared resources..............................................................................................................32227.2 EasyDMA...........................................................................................................................32227.3 ECB data structure............................................................................................................32227.4 Registers........................................................................................................................... 32327.5 Electrical specification.......................................................................................................324
28 CCM — AES CCM mode encryption................................................................32528.1 Shared resources..............................................................................................................32528.2 Key-steam generation....................................................................................................... 32528.3 Encryption..........................................................................................................................32628.4 Decryption......................................................................................................................... 32628.5 AES CCM and RADIO concurrent operation....................................................................32728.6 Encrypting packets on-the-fly in radio transmit mode.......................................................32728.7 Decrypting packets on-the-fly in radio receive mode........................................................32828.8 CCM data structure...........................................................................................................32928.9 EasyDMA and ERROR event........................................................................................... 33028.10 Registers......................................................................................................................... 33028.11 Electrical specification..................................................................................................... 334
29 AAR — Accelerated address resolver.............................................................33529.1 Shared resources..............................................................................................................33529.2 EasyDMA...........................................................................................................................33529.3 Resolving a resolvable address........................................................................................33529.4 Use case example for chaining RADIO packet reception with address resolution using
AAR.......................................................................................................................................33629.5 IRK data structure.............................................................................................................33629.6 Registers........................................................................................................................... 33729.7 Electrical specification.......................................................................................................339
30 SPIM — Serial peripheral interface master with EasyDMA............................34030.1 SPI master transaction sequence.....................................................................................34030.2 D/CX functionality..............................................................................................................34130.3 Pin configuration............................................................................................................... 34230.4 Shared resources..............................................................................................................34230.5 EasyDMA...........................................................................................................................34230.6 Low power.........................................................................................................................34430.7 Registers........................................................................................................................... 34430.8 Electrical specification.......................................................................................................352
31 SPIS — Serial peripheral interface slave with EasyDMA...............................354
Contents
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31.1 Shared resources..............................................................................................................35431.2 EasyDMA...........................................................................................................................35431.3 SPI slave operation...........................................................................................................35531.4 Pin configuration............................................................................................................... 35631.5 Registers........................................................................................................................... 35731.6 Electrical specification.......................................................................................................365
32 TWIM — I2C compatible two-wire interface master with EasyDMA...............36732.1 Shared resources..............................................................................................................36832.2 EasyDMA...........................................................................................................................36832.3 Master write sequence......................................................................................................36832.4 Master read sequence...................................................................................................... 36932.5 Master repeated start sequence....................................................................................... 37032.6 Low power.........................................................................................................................37132.7 Master mode pin configuration......................................................................................... 37132.8 Registers........................................................................................................................... 37132.9 Electrical specification.......................................................................................................37832.10 Pullup resistor................................................................................................................. 379
33 TWIS — I2C compatible two-wire interface slave with EasyDMA..................38033.1 Shared resources..............................................................................................................38233.2 EasyDMA...........................................................................................................................38233.3 TWI slave responding to a read command.......................................................................38233.4 TWI slave responding to a write command...................................................................... 38333.5 Master repeated start sequence....................................................................................... 38433.6 Terminating an ongoing TWI transaction..........................................................................38533.7 Low power.........................................................................................................................38533.8 Slave mode pin configuration........................................................................................... 38533.9 Registers........................................................................................................................... 38633.10 Electrical specification..................................................................................................... 392
34 UARTE — Universal asynchronous receiver/transmitter with EasyDMA.... 39434.1 Shared resources..............................................................................................................39434.2 EasyDMA...........................................................................................................................39434.3 Transmission..................................................................................................................... 39534.4 Reception.......................................................................................................................... 39534.5 Error conditions................................................................................................................. 39734.6 Using the UARTE without flow control............................................................................. 39734.7 Parity and stop bit configuration....................................................................................... 39734.8 Low power.........................................................................................................................39834.9 Pin configuration............................................................................................................... 39834.10 Registers......................................................................................................................... 39834.11 Electrical specification..................................................................................................... 407
35 QDEC — Quadrature decoder..........................................................................40835.1 Sampling and decoding.................................................................................................... 40835.2 LED output........................................................................................................................ 40935.3 Debounce filters................................................................................................................ 40935.4 Accumulators.....................................................................................................................41035.5 Output/input pins............................................................................................................... 41035.6 Pin configuration............................................................................................................... 41035.7 Registers........................................................................................................................... 41135.8 Electrical specification.......................................................................................................417
36 SAADC — Successive approximation analog-to-digital converter............... 41836.1 Shared resources..............................................................................................................41836.2 Overview............................................................................................................................41836.3 Digital output..................................................................................................................... 41936.4 Analog inputs and channels..............................................................................................42036.5 Operation modes...............................................................................................................42036.6 EasyDMA...........................................................................................................................42236.7 Resistor ladder.................................................................................................................. 42336.8 Reference.......................................................................................................................... 424
Contents
Page 6
36.9 Acquisition time................................................................................................................. 42436.10 Limits event monitoring................................................................................................... 42536.11 Registers......................................................................................................................... 42636.12 Electrical specification..................................................................................................... 45036.13 Performance factors........................................................................................................452
37 COMP — Comparator........................................................................................45337.1 Differential mode............................................................................................................... 45437.2 Single-ended mode........................................................................................................... 45537.3 Registers........................................................................................................................... 45737.4 Electrical specification.......................................................................................................462
38 LPCOMP — Low power comparator................................................................46338.1 Shared resources..............................................................................................................46438.2 Pin configuration............................................................................................................... 46438.3 Registers........................................................................................................................... 46538.4 Electrical specification.......................................................................................................469
39 WDT — Watchdog timer................................................................................... 47039.1 Reload criteria................................................................................................................... 47039.2 Temporarily pausing the watchdog...................................................................................47039.3 Watchdog reset................................................................................................................. 47039.4 Registers........................................................................................................................... 47139.5 Electrical specification.......................................................................................................475
40 SWI — Software interrupts...............................................................................47640.1 Registers........................................................................................................................... 476
41 NFCT — Near field communication tag...........................................................47741.1 Overview............................................................................................................................47741.2 Operating states................................................................................................................47941.3 Pin configuration............................................................................................................... 48041.4 EasyDMA...........................................................................................................................48041.5 Frame assembler.............................................................................................................. 48141.6 Frame disassembler..........................................................................................................48241.7 Frame timing controller..................................................................................................... 48341.8 Collision resolution............................................................................................................ 48441.9 Antenna interface.............................................................................................................. 48541.10 NFCT antenna recommendations................................................................................... 48541.11 Battery protection............................................................................................................ 48641.12 References...................................................................................................................... 48641.13 Registers......................................................................................................................... 48641.14 Electrical specification..................................................................................................... 498
42 PDM — Pulse density modulation interface................................................... 49942.1 Master clock generator..................................................................................................... 49942.2 Module operation.............................................................................................................. 49942.3 Decimation filter................................................................................................................ 50042.4 EasyDMA...........................................................................................................................50042.5 Hardware example............................................................................................................ 50142.6 Pin configuration............................................................................................................... 50142.7 Registers........................................................................................................................... 50242.8 Electrical specification.......................................................................................................507
43 I2S — Inter-IC sound interface......................................................50843.1 Mode..................................................................................................................................50843.2 Transmitting and receiving................................................................................................50843.3 Left right clock (LRCK)..................................................................................................... 50943.4 Serial clock (SCK).............................................................................................................50943.5 Master clock (MCK).......................................................................................................... 51043.6 Width, alignment and format.............................................................................................51043.7 EasyDMA...........................................................................................................................512
Contents
Page 7
43.8 Module operation.............................................................................................................. 51443.9 Pin configuration............................................................................................................... 51543.10 Registers......................................................................................................................... 51643.11 Electrical specification..................................................................................................... 523
44 MWU — Memory watch unit.............................................................................52444.1 Registers........................................................................................................................... 524
45 EGU — Event generator unit............................................................................55145.1 Registers........................................................................................................................... 55145.2 Electrical specification.......................................................................................................557
46 PWM — Pulse width modulation..................................................................... 55846.1 Wave counter.................................................................................................................... 55846.2 Decoder with EasyDMA.................................................................................................... 56146.3 Limitations......................................................................................................................... 56646.4 Pin configuration............................................................................................................... 56646.5 Registers........................................................................................................................... 56746.6 Electrical specification.......................................................................................................575
47 SPI — Serial peripheral interface master........................................................57647.1 Functional description....................................................................................................... 57647.2 Registers........................................................................................................................... 57947.3 Electrical specification.......................................................................................................582
48 TWI — I2C compatible two-wire interface....................................................... 58348.1 Functional description....................................................................................................... 58348.2 Master mode pin configuration......................................................................................... 58348.3 Shared resources..............................................................................................................58448.4 Master write sequence......................................................................................................58448.5 Master read sequence...................................................................................................... 58548.6 Master repeated start sequence....................................................................................... 58648.7 Low power.........................................................................................................................58748.8 Registers........................................................................................................................... 58748.9 Electrical specification.......................................................................................................591
49 UART — Universal asynchronous receiver/transmitter.................................59349.1 Functional description....................................................................................................... 59349.2 Pin configuration............................................................................................................... 59349.3 Shared resources..............................................................................................................59449.4 Transmission..................................................................................................................... 59449.5 Reception.......................................................................................................................... 59449.6 Suspending the UART...................................................................................................... 59549.7 Error conditions................................................................................................................. 59549.8 Using the UART without flow control................................................................................59649.9 Parity configuration............................................................................................................59649.10 Registers......................................................................................................................... 59649.11 Electrical specification..................................................................................................... 601
50 ACL — Access control lists............................................................................. 60250.1 Registers........................................................................................................................... 603
51 USBD — Universal serial bus device.............................................................. 61151.1 USB device states.............................................................................................................61151.2 USB terminology............................................................................................................... 61251.3 USB pins........................................................................................................................... 61351.4 USBD start-up sequence.................................................................................................. 61351.5 USB pull-up....................................................................................................................... 61451.6 USB reset..........................................................................................................................61451.7 USB suspend and resume................................................................................................61551.8 EasyDMA...........................................................................................................................61651.9 Control transfers................................................................................................................61751.10 Bulk and interrupt transactions....................................................................................... 62051.11 Isochronous transactions................................................................................................ 62251.12 USB register access limitations...................................................................................... 624
Contents
Page 8
51.13 Registers......................................................................................................................... 62551.14 Electrical specification..................................................................................................... 662
52 QSPI — Quad serial peripheral interface........................................................ 66352.1 Configuring peripheral.......................................................................................................66352.2 Write operation..................................................................................................................66452.3 Read operation..................................................................................................................66452.4 Erase operation.................................................................................................................66452.5 Execute in place............................................................................................................... 66452.6 Sending custom instructions............................................................................................. 66552.7 Deep power-down mode...................................................................................................66652.8 Instruction set....................................................................................................................66652.9 Interface description..........................................................................................................66752.10 Registers......................................................................................................................... 67152.11 Electrical specification..................................................................................................... 680
53 CRYPTOCELL — ARM TrustZone CryptoCell 310..........................................68153.1 Standards.......................................................................................................................... 68253.2 Control interface................................................................................................................682
54 Mechanical specifications................................................................................ 68454.1 AQFN73 7 x 7 mm package.............................................................................................684
55 Ordering information.........................................................................................68555.1 Package marking.............................................................................................................. 68555.2 Box labels..........................................................................................................................68555.3 Order code........................................................................................................................ 68655.4 Code ranges and values...................................................................................................68655.5 Product options................................................................................................................. 687
56 Reference circuitry............................................................................................ 68856.1 Circuit configuration no. 1.................................................................................................68856.2 Circuit configuration no. 2.................................................................................................68956.3 Circuit configuration no. 3.................................................................................................69056.4 Circuit configuration no. 4.................................................................................................69256.5 Circuit configuration no. 5.................................................................................................69356.6 Circuit configuration no. 6.................................................................................................69456.7 PCB guidelines..................................................................................................................69556.8 PCB layout example......................................................................................................... 695
57 Liability disclaimer............................................................................................ 69857.1 RoHS and REACH statement...........................................................................................69857.2 Life support applications................................................................................................... 698
1 Revision history
Page 9
1 Revision history
Date Version DescriptionJuly 2017 0.5.1 The following content is changed in this version:
• Pin assignments on page 13: Added description for trace pins• CPU on page 18: Improved SysTick timer description• Memory on page 20: Memory map figure updated• AHB multilayer on page 25: Added SPIM3 and updated RAMPRI registers• EasyDMA on page 26: Miscellaneous documentation improvements• UICR — User information configuration registers on page 44: Improved
APPROTECT description and added DEBUGCTRL register• SPIM — Serial peripheral interface master with EasyDMA on page 340:
Fixed error in mode table and changed the base address of SPIM3• Debug and trace on page 62: Added r_pull parameter for CTRL-AP, in
addition to miscellaneous documentation improvements• POWER — Power supply on page 66:
• Added clarifications for supplying external circuitry• Improved register descriptions• Removed deprecated RAMON and RAMONB registers• Removed pin reset from CTRL-AP feature• Improved description of POFCON
• CLOCK — Clock control on page 141:
• Added HFXO debounce functionality• Changed LFRC accuracy to +- 500 ppm• Improved description in TRACECONFIG register
• RADIO — 2.4 GHz Radio on page 249:
• Removed 9 dBm output power option• Updated TX sequence figure• Improved TIFS description• Added PHYEND event• Added PDUSTAT register• Removed 250 kbit/s Nordic proprietary mode• Changed to using term bps instead of sps for data rate in electrical
specifications• SAADC — Successive approximation analog-to-digital converter on page
418: Updated VDD/5 input specification• COMP — Comparator on page 453: REFSEL AREF value changed• PWM — Pulse width modulation on page 558: Changed width of
DECODER.LOAD field• PDM — Pulse density modulation interface on page 499: Fixed error in
electrical specification units• I2S — Inter-IC sound interface on page 508: PSEL registers PORT field
updated• Reference circuitry on page 688: Reference schematics updated and
erroneous sentence for VDD/VDDH connection removed• Block diagram on page 12: Miscellaneous improvements
December 2016 0.5 First release
2 About this document
Page 10
2 About this document
This product specification is organized into chapters based on the modules and peripherals that are availablein this IC.
The peripheral descriptions are divided into separate sections that include the following information:
• A detailed functional description of the peripheral• Register configuration for the peripheral• Electrical specification tables, containing performance data which apply for the operating conditions
described in Recommended operating conditions on page 17.
2.1 Document naming and statusNordic uses three distinct names for this document, which are reflecting the maturity and the status of thedocument and its content.
Table 1: Defined document names
Document name DescriptionObjective Product Specification (OPS) Applies to document versions up to 0.7.
This product specification contains target specifications for product development.Preliminary Product Specification (PPS) Applies to document versions 0.7 and up to 1.0.
This product specification contains preliminary data. Supplementary data may bepublished from Nordic Semiconductor ASA later.
Product Specification (PS) Applies to document versions 1.0 and higher.
This product specification contains final product specifications. NordicSemiconductor ASA reserves the right to make changes at any time without noticein order to improve design and supply the best possible product.
2.2 Peripheral naming and abbreviationsEvery peripheral has a unique capitalized name or an abbreviation of its name, e.g. TIMER, used foridentification and reference. This name is used in chapter headings and references, and it will appear in theARM® Cortex® Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer to identifythe peripheral.
The peripheral instance name, which is different from the peripheral name, is constructed using theperipheral name followed by a numbered postfix, starting with 0, for example, TIMER0. A postfix is normallyonly used if a peripheral can be instantiated more than once. The peripheral instance name is also used inthe CMSIS to identify the peripheral instance.
2.3 Register tablesIndividual registers are described using register tables. These tables are built up of two sections. The firstthree colored rows describe the position and size of the different fields in the register. The following rowsdescribe the fields in more detail.
2.3.1 Fields and valuesThe Id (Field Id) row specifies the bits that belong to the different fields in the register. If a field hasenumerated values, then every value will be identified with a unique value id in the Value Id column.
A blank space means that the field is reserved and read as undefined, and it also must be written as 0 tosecure forward compatibility. If a register is divided into more than one field, a unique field name is specifiedfor each field in the Field column. The Value Id may be omitted in the single-bit bit fields when values can besubstituted with a Boolean type enumerator range, e.g. true/false, disable(d)/enable(d), on/off, and so on.
2 About this document
Page 11
Values are usually provided as decimal or hexadecimal. Hexadecimal values have a 0x prefix, decimalvalues have no prefix.
The Value column can be populated in the following ways:
• Individual enumerated values, for example 1, 3, 9.• Range of values, e.g. [0..4], indicating all values from and including 0 and 4.• Implicit values. If no values are indicated in the Value column, all bit combinations are supported, or
alternatively the field's translation and limitations are described in the text instead.
If two or more fields are closely related, the Value Id, Value, and Description may be omitted for all but thefirst field. Subsequent fields will indicate inheritance with '..'.
A feature marked Deprecated should not be used for new designs.
2.4 Registers
Table 2: Register Overview
Register Offset Description
DUMMY 0x514 Example of a register controlling a dummy feature
2.4.1 DUMMY
Address offset: 0x514
Example of a register controlling a dummy feature
Bit number 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Id D D D D C C C B A A
Reset 0x00050002 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0
Id RW Field Value Id Value Description
A RW FIELD_A Example of a field with several enumerated values
Disabled 0 The example feature is disabled
NormalMode 1 The example feature is enabled in normal mode
ExtendedMode 2 The example feature is enabled along with extra functionality
B RW FIELD_B Example of a deprecated field Deprecated
Disabled 0 The override feature is disabled
Enabled 1 The override feature is enabled
C RW FIELD_C Example of a field with a valid range of values
ValidRange [2..7] Example of allowed values for this field
D RW FIELD_D Example of a field with no restriction on the values
3 Block diagram
Page 12
3 Block diagram
This block diagram illustrates the overall system. Arrows with white heads indicate signals that sharephysical pins with other signals.
nRF52840
APB0
AHB TO APB BRIDGE
RADIO
CPU
ARM CORTEX-M4
AHB-AP
RNG
TEMPWDT
NVMC
ANT
POWERnRESETRTC [0..2]
PPI
TIMER [0..4]
NVIC
UICRFICR
SW-DP
CODE
EasyDMA master
QDEC
SAADC
GPIOTE
P0 (P0.0 – P0.31)
AIN0 – AIN7
LEDAB
UARTE [0..1]
SPIS [0..2] MOSIMISOCSN
COMP
EasyDMA
RXDTXDCTSRTS
ETM
SysTick
TPIUTP
EasyDMA
LPCOMP
EasyDMAmaster
master
NFCTNFC1NFC2
EasyDMA master
master
SWDIOSWCLK
CTRL-AP
PWM [0..3]OUT0 – OUT3
I2S
MCKLRCK
SCLSDOUT
SDIN
PDMCLKDIN
SCK
EasyDMA master
EasyDMA master
EasyDMA master
I-Cache
slave
slave
slave
slave
slave
mas
ter
CLOCK
XL2XL1XC2XC1
USBDD-D+
EasyDMA master
VBUS
SPIM [0..3]SCK
MISOEasyDMA
MOSI
master
TWIM [0..1]SCLSDA
EasyDMAmaster
QSPI IO3IO2IO1IO0
EasyDMAmasterCSNSCK
ECB
EasyDMAmaster
CCM
EasyDMAmaster
AAR
EasyDMAmaster
CryptoCell
DMAmaster
TWIS [0..1]SCLSDA
EasyDMAmaster
RAM0
slave
RAM1
slave
RAM2
slave
RAM3
slave
RAM4
slave
RAM5
slave
RAM6
slave
RAM7
slave
GPIO
slave
RAM8
slave
AHB multilayer
Figure 1: Block diagram
4 Pin assignments
Page 13
4 Pin assignments
This section describes the pin assignment and the pin functions.
This device provides flexibility when it comes to routing and configuration of the GPIO pins. However, somepins have recommendations for how the pin should be configured or what it should be used for. See Table 3:QIAA pin assignments on page 13 for more information about this.
4.1 QIAA pin assignmentsThis section describes the pin assignment and the pin functions.
Figure 2: QIAA pin assignments, top view
Table 3: QIAA pin assignments
Pin Name Function Description Recommended usage
A8 P0.31
AIN7
Digital I/O
Analog input
General purpose I/O
Analog input
Standard drive, low frequency I/O
only.
A10 P0.29
AIN5
Digital I/O
Analog input
General purpose I/O
Analog input
Standard drive, low frequency I/O
only.
A12 P0.02
AIN0
Digital I/O
Analog input
General purpose I/O
Analog input
Standard drive, low frequency I/O
only.
A14 P1.15 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
A16 P1.13 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
A18 DEC2 Power 1.3 V regulator supply decoupling (Radio supply)
A20 P1.10 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
A22 VDD Power Power supply
A23 XC2 Analog input Connection for 32 MHz crystal.
B1 VDD Power Power supply
B3 DCC Power DC/DC converter output
4 Pin assignments
Page 14
Pin Name Function Description Recommended usage
B5 DEC4 Power 1.3 V regulator supply decoupling
B7 VSS Power Ground
B9 P0.30
AIN6
Digital I/O
Analog input
General purpose I/O
Analog input
Standard drive, low frequency I/O
only.
B11 P0.28
AIN4
Digital I/O
Analog input
General purpose I/O
Analog input
Standard drive, low frequency I/O
only.
B13 P0.03
AIN1
Digital I/O
Analog input
General purpose I/O
Analog input
Standard drive, low frequency I/O
only.
B15 P1.14 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
B17 P1.12 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
B19 P0.11
TRACEDATA2
Digital I/O
Trace data
General purpose I/O pin.
Trace buffer TRACEDATA[2].
Standard drive, low frequency I/O
only.
B24 XC1 Analog input Connection for 32 MHz crystal
C1 DEC1 Power 1.1 V regulator supply decoupling
D2 P0.00
XL1
Digital I/O
Analog input
General purpose I/O
Connection for 32.768 kHz crystal
D23 DEC3 Power Power supply, decoupling
E24 DEC6 Power 1.3 V regulator supply decoupling (Radio supply)
F2 P0.01
XL2
Digital I/O
Analog input
General purpose I/O
Connection for 32.768 kHz crystal
F23 VSS_PA Power Ground (Radio supply)
G1 P0.26 Digital I/O General purpose I/O
H2 P0.27 Digital I/O General purpose I/O
H23 ANT RF Single-ended radio antenna connection See Reference circuitry on page
688 for guidelines on how to
ensure good RF performance.
J1 P0.04
AIN2
Digital I/O
Analog input
General purpose I/O
Analog input
J24 P0.10
NFC2
Digital I/O
NFC input
General purpose I/O
NFC antenna connection
Standard drive, low frequency I/O
only.
K2 P0.05
AIN3
Digital I/O
Analog input
General purpose I/O
Analog input
L1 P0.06 Digital I/O General purpose I/O
L24 P0.09
NFC1
Digital I/O
NFC input
General purpose I/O
NFC antenna connection
Standard drive, low frequency I/O
only.
M2 P0.07
TRACECLK
Digital I/O
Trace clock
General purpose I/O pin
Trace buffer clock
N1 P0.08 Digital I/O General purpose I/O
N24 DEC5 Power 1.3 V regulator supply decoupling (flash supply)
P2 P1.08 Digital I/O General purpose I/O
P23 P1.07 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
R1 P1.09
TRACEDATA3
Digital I/O
Trace data
General purpose I/O pin.
Trace buffer TRACEDATA[3].
R24 P1.06 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
T2 P0.11 Digital I/O General purpose I/O
T23 P1.05 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
U1 P0.12
TRACEDATA1
Digital I/O
Trace data
General purpose I/O pin.
Trace buffer TRACEDATA[1].
4 Pin assignments
Page 15
Pin Name Function Description Recommended usage
U24 P1.04 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
V23 P1.03 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
W1 VDD Power Power supply
W24 P1.02 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
Y2 VDDH Power High voltage power supply
Y23 P1.01 Digital I/O General purpose I/O Standard drive, low frequency I/O
only.
AA24 SWDCLK Debug Serial wire debug clock input for debug and
programming
AB2 DCCH Power DC/DC converter output
AC5 DECUSB Power Decoupling for USB 3.3 V
AC9 P0.14 Digital I/O General purpose I/O
AC11 P0.16 Digital I/O General purpose I/O
AC13 P0.18
nRESET
Digital I/O General purpose I/O
Configurable as system RESET
QSPI/CSN
AC15 P0.19 Digital I/O General purpose I/O QSPI/SCK
AC17 P0.21 Digital I/O General purpose I/O QSPI
AC19 P0.23 Digital I/O General purpose I/O QSPI
AC21 P0.25 Digital I/O General purpose I/O
AC24 SWDIO Debug Debug serial data
AD2 VBUS Power 5 V input for USB 3.3 V regulator
AD4 D- Digital I/O USB D- USB
AD6 D+ Digital I/O USB D+ USB
AD8 P0.13 Digital I/O General purpose I/O
AD10 P0.15 Digital I/O General purpose I/O
AD12 P0.17 Digital I/O General purpose I/O
AD14 VDD Power Power supply
AD16 P0.20 Digital I/O General purpose I/O
AD18 P0.22 Digital I/O General purpose I/O QSPI
AD20 P0.24 Digital I/O General purpose I/O
AD22 P1.00
TRACEDATA0
Digital I/O
Trace data
General purpose I/O pin.
Trace buffer TRACEDATA[0].
Serial wire output (SWO).
QSPI
AD23 VDD Power Flash supply pad
Bottom of chip
Die pad VSS Power Ground pad. Exposed die pad must be connected to
ground (VSS) for proper device operation.
Important: For more information on Standard drive, see GPIO — General purpose input/output onpage 154. Low frequency I/O is signals with a frequency up to 10 kHz.
5 Absolute maximum ratings
Page 16
5 Absolute maximum ratings
Maximum ratings are the extreme limits to which the chip can be exposed for a limited amount of timewithout permanently damaging it. Exposure to absolute maximum ratings for prolonged periods of time mayaffect the reliability of the device.
Table 4: Absolute maximum ratings
Note Min. Max. UnitSupply voltagesVDD -0.3 +3.9 VVDDH -0.3 +5.8 VVBUS -0.3 +5.8 VVSS 0 VI/O pin voltageVI/O, VDD ≤3.6 V -0.3 VDD + 0.3 V VVI/O, VDD >3.6 V -0.3 3.9 V VNFC antenna pin currentINFC1/2 80 mARadioRF input level 10 dBmEnvironmental (AQFN package)Storage temperature -40 +125 °CMSL Moisture Sensitivity Level 2ESD HBM Human Body Model 4 kVESD CDMQF Charged Device Model
(AQFN73, 7×7 mm package)
750 V
Flash memoryEndurance 10 000 Write/erase cyclesRetention 10 years at 40°C
6 Recommended operating conditions
Page 17
6 Recommended operating conditions
The operating conditions are the physical parameters that the chip can operate within.
Table 5: Recommended operating conditions
Symbol Parameter Notes Min. Nom. Max. UnitsVDD VDD supply voltage, independent of DCDC enable 1.7 3.0 3.6 VVDDPOR VDD supply voltage needed during power-on
reset1.75 V
VDDH VDDH supply voltage, independent of DCDCenable
2.5 3.7 5.5 V
VBUS VBUS USB supply voltage 4.35 5 5.5 VtR_VDD Supply rise time (0 V to 1.7 V) 60 mstR_VDDH Supply rise time (0 V to 3.7 V) 100 msTA Operating temperature -40 25 85 °C
Important: The on-chip power-on reset circuitry may not function properly for rise times longer thanthe specified maximum.
7 CPU
Page 18
7 CPU
The ARM® Cortex®-M4 processor with floating-point unit (FPU) has a 32-bit instruction set (Thumb®-2technology) that implements a superset of 16 and 32-bit instructions to maximize code density andperformance.
This processor implements several features that enable energy-efficient arithmetic and high-performancesignal processing, including:
• Digital signal processing (DSP) instructions• Single-cycle multiply and accumulate (MAC) instructions• Hardware divide• 8- and 16-bit single instruction multiple data (SIMD) instructions• Single-precision floating-point unit (FPU)
The ARM Cortex Microcontroller Software Interface Standard (CMSIS) hardware abstraction layer for theARM Cortex processor series is implemented and available for the M4 CPU.
Real-time execution is highly deterministic in thread mode, to and from sleep modes, and when handlingevents at configurable priority levels via the nested vectored interrupt controller (NVIC).
Executing code from flash will have a wait state penalty on the nRF52 series. An instruction cache can beenabled to minimize flash wait states when fetching instructions. For more information on cache, see Cacheon page 29. The section Electrical specification on page 18 shows CPU performance parametersincluding wait states in different modes, CPU current and efficiency, and processing power and efficiencybased on the CoreMark® benchmark.
The ARM System Timer (SysTick) is present on nRF52840. The SysTick's clock will only tick when the CPUis running or when the system is in debug interface mode.
7.1 Floating point interruptThe floating point unit (FPU) may generate exceptions when used due to e.g. overflow or underflow, which inturn will trigger the FPU interrupt.
See Instantiation on page 23 for more information about the exceptions triggering the FPU interrupt.
To clear the IRQ (interrupt request) line when an exception has occurred, the relevant exception bit withinthe floating-point status and control register (FPSCR) needs to be cleared. For more information about theFPSCR or other FPU registers, see Cortex-M4 Devices Generic User Guide.
7.2 Electrical specification
7.2.1 CPU performance
The CPU clock speed is 64 MHz. Current and efficiency data is taken when in System ON and the CPU isexecuting the CoreMark™ benchmark. It includes power regulator and clock base currents. All other blocksare IDLE.
Symbol Description Min. Typ. Max. Units
WFLASH CPU wait states, running CoreMark from flash, cache disabled 2
WFLASHCACHE CPU wait states, running CoreMark from flash, cache enabled 3
WRAM CPU wait states, running CoreMark from RAM 0
IDDFLASHCACHE CPU current, running CoreMark from flash, cache enabled, LDO 6.5 mA
IDDFLASHCACHEDCDC CPU current, running CoreMark from flash, cache enabled,
DCDC 3V
3.6 mA
IDDFLASH CPU current, running CoreMark from flash, cache disabled, LDO mA
7 CPU
Page 19
Symbol Description Min. Typ. Max. Units
IDDFLASHDCDC CPU current, running CoreMark from flash, cache disabled,
DCDC 3V
mA
IDDRAM CPU current, running CoreMark from RAM, LDO mA
IDDRAMDCDC CPU current, running CoreMark from RAM, DCDC 3V mA
IDDFLASH/MHz CPU efficiency, running CoreMark from flash, cache enabled,
LDO
102 µA/
MHz
IDDFLASHDCDC/MHz CPU efficiency, running CoreMark from flash, cache enabled,
DCDC 3V
56 µA/
MHz
CMFLASH CoreMark, running CoreMark from flash, cache enabled 212 CoreMark
CMFLASH/MHz CoreMark per MHz, running CoreMark from flash, cache
enabled
3.3 CoreMark/
MHz
CMFLASH/mA CoreMark per mA, running CoreMark from flash, cache enabled,
DCDC 3V
59 CoreMark/
mA
7.3 CPU and support module configurationThe ARM® Cortex®-M4 processor has a number of CPU options and support modules implemented on thedevice.Option / Module Description ImplementedCore optionsNVIC Nested vector interrupt controller 37 vectorsPRIORITIES Priority bits 3WIC Wakeup interrupt controller NOEndianness Memory system endianness Little endianBit-banding Bit banded memory NODWT Data watchpoint and trace YESSysTick System tick timer YESModulesMPU Memory protection unit YESFPU Floating-point unit YESDAP Debug access port YESETM Embedded trace macrocell YESITM Instrumentation trace macrocell YESTPIU Trace port interface unit YESETB Embedded trace buffer NOFPB Flash patch and breakpoint unit YESHTM AMBA™ AHB trace macrocell NO
8 Memory
Page 20
8 Memory
The nRF52840 contains 1 MB of flash and 256 kB of RAM that can be used for code and data storage.
The CPU and the peripherals having EasyDMA can access memory via the AHB multilayer interconnect.
The CPU is also able to access peripherals via the AHB multilayer interconnect, as illustrated in Figure 3:Memory layout on page 20.
RAM3 AHB slave
RAM2 AHB slave
RAM1 AHB slave
RAM0 AHB slave
RAM7 AHB slave
RAM6 AHB slave
RAM5 AHB slave
RAM4 AHB slave
AHB multilayer interconnect
AH
B
slav
e
Page 0
Page 1
Page 2
Page 3..254
Page 255
0x0000 0000
0x0000 2000
0x0000 3000
0x000F F000
FlashICODE/DCODE
AH
B
slav
e
NV
MC
ICODE
DCODE
Peripheral
EasyDMA
DM
A b
us
Peripheral
EasyDMA
DM
A b
us
CPU
ARM Cortex-M4S
yste
m b
us
ICO
DE
DC
OD
E
AHB2APB
AHB
APB
Block 0
Block 1
Block 2..6
Block 7
0x0000 0200
0x0000 0400
0x0000 1000
0x0000 0E00
I-Cac
he
0x2000 0000
0x2000 1000
0x2000 2000
0x2000 3000
0x2000 4000
0x2000 5000
0x2000 6000
0x2000 7000Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
0x2000 8000
0x2000 9000
0x2000 A000
0x2000 B000
0x2000 C000
0x2000 D000
0x2000 E000
0x2000 F000Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
Section 0
Section 1
Data RAMSystem
0x0080 0000
0x0080 1000
0x0080 2000
0x0080 3000
0x0080 4000
0x0080 5000
0x0080 6000
0x0080 7000
0x0080 8000
0x0080 9000
0x0080 A000
0x0080 B000
0x0080 C000
0x0080 D000
0x0080 E000
0x0080 F000
Code RAMICODE / DCODE
Section 0
Section 1
Section 2
Section 3
Section 4
Section 5
0x2001 0000 0x0081 0000
0x2001 8000 0x0081 8000
0x2002 0000 0x0082 0000
0x2002 8000 0x0082 8000
0x2003 0000 0x0083 0000
0x2003 8000 0x0083 8000
RAM8 AHB slave
Figure 3: Memory layout
See AHB multilayer on page 25 and EasyDMA on page 26 for more information about the AHBmultilayer interconnect and the EasyDMA.
The same physical RAM is mapped to both the Data RAM region and the Code RAM region. It is up to theapplication to partition the RAM within these regions so that one does not corrupt the other.
8.1 RAM - Random access memoryThe RAM interface is divided into 9 RAM AHB slaves.
RAM AHB slave 0-7 is connected to 2x4 kB RAM sections each and RAM AHB slave 8 is connected to 6x32kB sections, as shown in Figure 3: Memory layout on page 20.
Each of the RAM sections have separate power control for System ON and System OFF mode operation,which is configured via RAM register (see the POWER — Power supply on page 66).
8.2 Flash - Non-volatile memoryThe flash can be read an unlimited number of times by the CPU, but it has restrictions on the number oftimes it can be written and erased and also on how it can be written.
8 Memory
Page 21
Writing to flash is managed by the non-volatile memory controller (NVMC), see NVMC — Non-volatilememory controller on page 28.
The flash is divided into 256x4 kB pages that can be accessed by the CPU via both the ICODE and DCODEbuses as shown in Figure 3: Memory layout on page 20. Each page is divided into 8 blocks.
8.3 Memory mapThe complete memory map is shown in Figure 4: Memory map on page 22. As described in Memory onpage 20, Code RAM and the Data RAM are the same physical RAM.
8 Memory
Page 22
Device
Device
Device
RAM
RAM
Peripheral
SRAM
Code
Private peripheral bus
AHB peripherals
APB peripherals
UICRFICR
Data RAM
Code RAMFlash
0xFFFFFFFF
0x00000000
0x20000000
0x40000000
0x60000000
0x80000000
0xA0000000
0xC0000000
0xE0000000
0x00000000
0x10000000
0x40000000
0x50000000
0xE0000000
0x00800000
0x10001000
0x20000000
XIP0x120000000x19FFFFFF
System address map Address map
Figure 4: Memory map
8 Memory
Page 23
8.4 Instantiation
Table 6: Instantiation table
ID Base Address Peripheral Instance Description
0 0x40000000 CLOCK CLOCK Clock control
0 0x40000000 POWER POWER Power control
1 0x40001000 RADIO RADIO 2.4 GHz radio
2 0x40002000 UARTE UARTE0 Universal asynchronous receiver/transmitter with EasyDMA, unit 0
2 0x40002000 UART UART0 Universal asynchronous receiver/transmitter Deprecated
3 0x40003000 TWIM TWIM0 Two-wire interface master 0
3 0x40003000 SPIS SPIS0 SPI slave 0
3 0x40003000 SPIM SPIM0 SPI master 0
3 0x40003000 SPI SPI0 SPI master 0 Deprecated
3 0x40003000 TWIS TWIS0 Two-wire interface slave 0
3 0x40003000 TWI TWI0 Two-wire interface master 0 Deprecated
4 0x40004000 TWIS TWIS1 Two-wire interface slave 1
4 0x40004000 SPIS SPIS1 SPI slave 1
4 0x40004000 SPIM SPIM1 SPI master 1
4 0x40004000 TWI TWI1 Two-wire interface master 1 Deprecated
4 0x40004000 TWIM TWIM1 Two-wire interface master 1
4 0x40004000 SPI SPI1 SPI master 1 Deprecated
5 0x40005000 NFCT NFCT Near field communication tag
6 0x40006000 GPIOTE GPIOTE GPIO tasks and events
7 0x40007000 SAADC SAADC Analog to digital converter
8 0x40008000 TIMER TIMER0 Timer 0
9 0x40009000 TIMER TIMER1 Timer 1
10 0x4000A000 TIMER TIMER2 Timer 2
11 0x4000B000 RTC RTC0 Real-time counter 0
12 0x4000C000 TEMP TEMP Temperature sensor
13 0x4000D000 RNG RNG Random number generator
14 0x4000E000 ECB ECB AES electronic code book (ECB) mode block encryption
15 0x4000F000 AAR AAR Accelerated address resolver
15 0x4000F000 CCM CCM AES counter with CBC-MAC (CCM) mode block encryption
16 0x40010000 WDT WDT Watchdog timer
17 0x40011000 RTC RTC1 Real-time counter 1
18 0x40012000 QDEC QDEC Quadrature decoder
19 0x40013000 LPCOMP LPCOMP Low power comparator
19 0x40013000 COMP COMP General purpose comparator
20 0x40014000 EGU EGU0 Event generator unit 0
20 0x40014000 SWI SWI0 Software interrupt 0
21 0x40015000 EGU EGU1 Event generator unit 1
21 0x40015000 SWI SWI1 Software interrupt 1
22 0x40016000 EGU EGU2 Event generator unit 2
22 0x40016000 SWI SWI2 Software interrupt 2
23 0x40017000 EGU EGU3 Event generator unit 3
23 0x40017000 SWI SWI3 Software interrupt 3
24 0x40018000 SWI SWI4 Software interrupt 4
24 0x40018000 EGU EGU4 Event generator unit 4
25 0x40019000 SWI SWI5 Software interrupt 5
25 0x40019000 EGU EGU5 Event generator unit 5
26 0x4001A000 TIMER TIMER3 Timer 3
27 0x4001B000 TIMER TIMER4 Timer 4
28 0x4001C000 PWM PWM0 Pulse width modulation unit 0
29 0x4001D000 PDM PDM Pulse Density modulation (digital microphone) interface
30 0x4001E000 ACL ACL Access control lists
30 0x4001E000 NVMC NVMC Non-volatile memory controller
8 Memory
Page 24
ID Base Address Peripheral Instance Description
31 0x4001F000 PPI PPI Programmable peripheral interconnect
32 0x40020000 MWU MWU Memory watch unit
33 0x40021000 PWM PWM1 Pulse width modulation unit 1
34 0x40022000 PWM PWM2 Pulse width modulation unit 2
35 0x40023000 SPIM SPIM2 SPI master 2
35 0x40023000 SPIS SPIS2 SPI slave 2
35 0x40023000 SPI SPI2 SPI master 2 Deprecated
36 0x40024000 RTC RTC2 Real-time counter 2
37 0x40025000 I2S I2S Inter-IC sound interface
38 0x40026000 FPU FPU FPU interrupt
39 0x40027000 USBD USBD Universal serial bus device
40 0x40028000 UARTE UARTE1 Universal asynchronous receiver/transmitter with EasyDMA, unit 1
41 0x40029000 QSPI QSPI External memory interface
45 0x4002D000 PWM PWM3 Pulse width modulation unit 3
47 0x4002F000 SPIM SPIM3 SPI master 3
0 0x50000000 GPIO GPIO General purpose input and output Deprecated
0 0x50000000 GPIO P0 General purpose input and output, port 0
0 0x50000300 GPIO P1 General purpose input and output, port 1
42 0x5002A000 CRYPTOCELL CRYPTOCELL CryptoCell subsystem control interface
N/A 0x10000000 FICR FICR Factory information configuration
N/A 0x10001000 UICR UICR User information configuration
9 AHB multilayer
Page 25
9 AHB multilayer
AHB multilayer enables parallel access paths between multiple masters and slaves in a system. Access isresolved using priorities.
Each bus master is connected to the slave devices using an interconnection matrix. The bus masters areassigned priorities. Priorities are used to resolve access when two (or more) bus masters request access tothe same slave device. The following applies:
• If two (or more) bus masters request access to the same slave device, the master with the highest priorityis granted the access first.
• Bus masters with lower priority are stalled until the higher priority master has completed its transaction.• If the higher priority master pauses at any point during its transaction, the lower priority master in queue is
temporarily granted access to the slave device until the higher priority master resumes its activity.• Bus masters that have the same priority are mutually exclusive, thus cannot be used concurrently.
Below is a list of bus masters in the system and their priorities.
Table 7: AHB bus masters (listed in priority order, highest to lowest)
Bus master name DescriptionCPUCTRL-APUSBCRYPTOCELLSPIM1/SPIS1/TWIM1/TWIS1 Same priority and mutually exclusiveRADIOCCM/ECB/AAR Same priority and mutually exclusiveSAADCUARTE0SPIM0/SPIS0/TWIM0/TWIS0 Same priority and mutually exclusiveSPIM2/SPIS2 Same priority and mutually exclusiveNFCTI2SPDMPWM0PWM1PWM2QSPIPWM3UARTE1SPIM3
Defined bus masters are the CPU and the peripherals with implemented EasyDMA, and the available slavesare RAM AHB slaves. How the bus masters and slaves are connected using the interconnection matrix isillustrated in Memory on page 20.
10 EasyDMA
Page 26
10 EasyDMA
EasyDMA is a module implemented by some peripherals to gain direct access to Data RAM.
EasyDMA is an AHB bus master similar to CPU and is connected to the AHB multilayer interconnect fordirect access to Data RAM. EasyDMA is not able to access flash.
A peripheral can implement multiple EasyDMA instances to provide dedicated channels. For example,for reading and writing of data between the peripheral and RAM. This concept is illustrated in Figure 5:EasyDMA example on page 26.
Peripheral
READER
Peripheral core
AHB multilayer
AHB
WRITER
AHB
RAM
RAM
RAM
EasyDMA
EasyDMA
Figure 5: EasyDMA example
An EasyDMA channel is usually implemented like illustrated by the code below, but some variations mayoccur:
READERBUFFER_SIZE 5 WRITERBUFFER_SIZE 6
uint8_t readerBuffer[READERBUFFER_SIZE] __at__ 0x20000000; uint8_t writerBuffer[WRITERBUFFER_SIZE] __at__ 0x20000005;
// Configuring the READER channel MYPERIPHERAL->READER.MAXCNT = READERBUFFER_SIZE; MYPERIPHERAL->READER.PTR = &readerBuffer;
// Configure the WRITER channel MYPERIPHERAL->WRITER.MAXCNT = WRITEERBUFFER_SIZE; MYPERIPHERAL->WRITER.PTR = &writerBuffer;
This example shows a peripheral called MYPERIPHERAL that implements two EasyDMA channels - one forreading called READER, and one for writing called WRITER. When the peripheral is started, it is assumedthat the peripheral will:
• Read 5 bytes from the readerBuffer located in RAM at address 0x20000000.• Process the data.• Write no more than 6 bytes back to the writerBuffer located in RAM at address 0x20000005.
The memory layout of these buffers is illustrated in Figure 6: EasyDMA memory layout on page 27.
10 EasyDMA
Page 27
readerBuffer[0] readerBuffer[1] readerBuffer[2] readerBuffer[3]
readerBuffer[4] writerBuffer[0] writerBuffer[1] writerBuffer[2]
writerBuffer[3] writerBuffer[4] writerBuffer[5]
0x20000000
0x20000004
0x20000008
Figure 6: EasyDMA memory layout
The WRITER.MAXCNT register should not be specified larger than the actual size of the buffer(writerBuffer). Otherwise, the channel would overflow the writerBuffer.
Once an EasyDMA transfer is completed, the AMOUNT register can be read by the CPU to see how manybytes were transferred. For example, CPU can read MYPERIPHERAL->WRITER.AMOUNT register to seehow many bytes WRITER wrote to RAM.
10.1 EasyDMA array listEasyDMA is able to operate in a mode called array list.
The array list does not provide a mechanism to explicitly specify where the next item in the list is located.Instead, it assumes that the list is organized as a linear array where items are located one after the other inRAM.
The EasyDMA array list can be implemented by using the data structure ArrayList_type as illustrated in thecode example below:
#define BUFFER_SIZE 4
typedef struct ArrayList { uint8_t buffer[BUFFER_SIZE]; } ArrayList_type;
ArrayList_type ReaderList[3];
READER.MAXCNT = BUFFER_SIZE; READER.PTR = &ReaderList;
The data structure only includes a buffer with size equal to the size of READER.MAXCNT register. EasyDMAuses the READER.MAXCNT register to determine when the buffer is full.
buffer[0] buffer[1]0x20000000 : ReaderList[0]
0x20000004 : ReaderList[1]
0x20000008 : ReaderList[2]
buffer[2] buffer[3]
READER.PTR = &ReaderList
buffer[0] buffer[1] buffer[2] buffer[3]
buffer[0] buffer[1] buffer[2] buffer[3]
Figure 7: EasyDMA array list
11 NVMC — Non-volatile memory controller
Page 28
11 NVMC — Non-volatile memory controller
The non-volatile memory controller (NVMC) is used for writing and erasing the internal flash memory and theUICR.
Before a write can be performed, the NVMC must be enabled for writing in CONFIG.WEN. Similarly, beforean erase can be performed, the NVMC must be enabled for erasing in CONFIG.EEN, see CONFIG on page30. The user must make sure that writing and erasing are not enabled at the same time. Failing to do somay result in unpredictable behavior.
11.1 Writing to flashWhen writing is enabled, the flash is written by writing a full 32-bit word to a word-aligned address in theflash.
The NVMC is only able to write '0' to bits in the flash that are erased, that is, set to '1'. It cannot write back abit to '1'.
As illustrated in Memory on page 20, the flash is divided into multiple pages that are further divided intomultiple blocks. The same block in the flash can only be written nWRITE number of times before an erasemust be performed using ERASEPAGE or ERASEALL. See the memory size and organization in Memory onpage 20 for block size.
Only full 32-bit words can be written to flash using the NVMC interface. To write less than 32 bits to flash,write the data as a word, and set all the bits that should remain unchanged in the word to '1'. Note that therestriction about the number of writes (see above) still applies in this case.
The time it takes to write a word to th