noise modelling

8/7/2019 noise modelling

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EE 201A Modeling and Optimization for VLSI Layout Jeff Wong and Dan Vasquez

EE 201A

Noise Modeling

Jeff Wong and Dan Vasquez

Electrical Engineering Department

University of California, Los Angeles



MEMS Research Laboratory Joe Zendejas and Jack W. Judy

Efficient Coupled Noise Estimation

for On-Chip Interconnects

Anirudh Devgan

Austin Research Laboratory

IBM Research Division, Austin TX




Motivation

Noise failure can be more severe thantiming failure ± Difficult to control from chip terminals

±

Expensive to correct (refabrication) Circuit or timing simulation (like SPICE)

can be used ± Linear reduction techniques can be applied for

linearly modeled circuits i.e. moment matching methods

± Inefficient for noise verification and avoidanceapplications




Noise Estimation

The paper presents an electrical metric for efficiently estimating coupled noise for on-chip interconnects

Capacitive coupling between an aggressor net and a victim net leads to couplednoise ± Aggressor net: switches states; source of

noise for victim net

± Victim net: maintains present state; affected bycoupled noise from aggressor net




Circuit Schematic

Switchingsignal

Vs(t)

Coupling

capacitors

CC = [CC,ii]

C1 = [C1,ii]

C2 = [C2,ii]

Let¶s analyze the case for one aggressor net and one victim net

V2,1 V2,n

V1,1 V1,n




Circuit Equations

Coupled equation for circuit:

In Laplace domain:

1 1 111 12 1

2 2 221 22 2

d C dt

sd

C dt

C C v t v t A A Bv t

C C v t v t A A B

« » « »« » « » « »! ¬ ¼ ¬ ¼¬ ¼ ¬ ¼ ¬ ¼

- ½ - ½- ½ - ½ - ½

r r

r r

1 11 12 11 1

2 21 22 22 2

C s

C

C C A A B sV s V s V sC C A A B sV s V s

« » « »« » « » « »! ¬ ¼ ¬ ¼¬ ¼ ¬ ¼ ¬ ¼¬ ¼ ¬ ¼- ½ - ½- ½ - ½ - ½

r r

r r




Circuit Equations

Aggressor net:

Victim net:

1 1 2 11 1 12 2 1

1

1 1 11 12 2 1

C s

C s

sC V sC V A V A V BV

V sC A A sC V BV

!

« » ! - ½

r r r r

r r

1 2 2 21 1 22 2 2

1

2 2 22 21 1 2

C s

C s

sC V sC V A V A V B V V sC A A sC V B V

!

« »! - ½

r r r r

r r




Transfer Function

Transfer function:

Simplifications (details later):

Simplified transfer function:

1

21 1 11 1 22

1

2 22 21 1 11 12

C

s C C

A sC sC A B BV H s

V sC A A sC sC A A sC

! !

r

r

12 21 20, 0, 0 A A B! ! !

1

1 11 12

2 1

2 22 1 11

C

s C

sC sC A BV H s

V sC A sC sC A

! !

r

r




Simplifications

A12

= 0

± No resistive (or DC) path exists from the

aggressor net to the victim net

A21 = 0

± No resistive (or DC) path exists from the victim

net to the aggressor net

B2

= 0

± No resistive (or DC) path exists from thevoltage/noise source to the victim net




Maximum Induced Noise

H ( s=0) = 0

± Coupling between aggressor and victim

net is purely capacitive

± Maximum induced noise can be

computed

Assume V s is a finite or infinite ramp

± max

2 2lim 0 is finited dt

t V V

pg!

r r




Final value theorem:

±

Ramp input u( s): ±

±

±

1

1 11 1max

2 2 102 22 1 11

limC

sC

C sC A BV u

sC A sC sC A

p

!

r &

Maximum Induced Noise

max

2 2 20

lim limt s

V v t sV spg p

« »| ! - ½r r r

max

2 20 0 0lim lim lim s s s

H suV sH s u s sH s u

s sp p p

! ! !r

max 1 1

2 22 11 1C V A C A B u !

r




Circuit Interpretation

max 1 1

2 22 11 1C V A C A B u

!

r

Switching

slope

1

ssV &

C I




Circuit Computations

(matrix method)

Step 1: Compute

± Requires circuit analysis of the

aggressor net

Step 2: Compute

± Requires a matrix multiplication

Step 3: Compute

± Requires circuit analysis of the victim

net

1

1 11 1

ssV A B u!

& &

1

ss

C C I C V !r &

max 1

2 22 C V A I

!r r







(by inspection)

Step 1: Compute

± Typical interconnects:

Negligible loss: no resistive path to ground

1

1 11 1

ssV A B u!

& &

1

ss

sV V !& &





(by inspection)

Step 2: Compute

± Convert steady state derivative on the

aggressor net to a current on the victim

net

±

±

i : index of node on the victim net ± j : index of node on the aggressor net

1

ss

C C I C V !r r

&

? A , 1

ss

C i C ij j

j

I I C V « »

! ! ¬ ¼- ½§

r &





(by inspection)

Step 3: Compute

± Victim circuit transformation:

Replace capacitors with coupling currents

The voltage at each node corresponds to

that node¶s maximum induced noise

max max 1

2 22 C N V A I

| !r r r





(by inspection)

Step 3: Compute

± Typical interconnects:

Compute by inspection in linear time

max max 1

2 22 C N V A I

| !r r r

max max max

1

i

C i i j i

L

V V R I N

« »« »! ! ¬ ¼- ½

- ½

r





(by inspection)

Step 3: Compute

± 3RC Circuit example:

max max 1

2 22 C N V A I

| !r r r

max max

1

i

i i j i

L

N R I N

! §

max

1 1 1 2 3 N R I I I !

max

2 1 1 2 3 2 2 N R I I I R I !

max

1 1 1 2 3 3 3 N R

I I I R

I !






Experiment

Typical small RC interconnect

structure

± Rise time of 200 ps or 100 ps

± Power supply voltage of 1.8 V

± Conventional circuit simulation vs.

proposed metric

± Run-time comparisons for variouscircuit sizes




Accuracy Results

ode ircuit Simulation roposed Metric % Error 1 0.0084 0.0084 0.00%

2 0.016 0.016 0.00%

3 0.0227 0.0227 0.00%

4 0.0286 0.0286 0.00%

5 0.0336 0.0336 0.00%6 0.0378 0.0379 0.26%

7 0.0412 0.0412 0.00%

8 0.0437 0.0438 0.23%

9 0.0454 0.0454 0.00%

10 0.0462 0.0463 0.22%

10 nodes, 200 ps rise time




Accuracy Results

10 nodes, 100 ps rise time

ode ircuit Simulation roposed Metric % Error 1 0.0147 0.0168 7.73%

2 0.0277 0.0319 13.10%

3 0.0392 0.0454 13.65%

4 0.0492 0.0572 13.98%

5 0.0578 0.0673 14.11%6 0.0651 0.0757 14.00%

7 0.0709 0.0824 13.95%

8 0.0752 0.0875 14.05%

9 0.0782 0.0908 13.87%

10 0.0797 0.0925 13.83%




Accuracy Results

Metric accuracy degrades with reductionin rise times

Metric estimation is more conservative

than circuit model¶s ± Fast rise times don¶t allow circuit to reach

ramp steady state noise

Loading of interconnect normally does notallow for very small rise times ± Metric accuracy should be acceptable for

many applications




Run-time Results

ir uitum er um er of Elements Arnoldi ModelRedu tion roposedMetri Matri

Met od

roposedMetri y

Inspe tion

1 500 .2s .00s .00s

2 5,000 5.86s .07s .01s

3 50,000 145s 3.44s .05s

4 500,000 - 360.55s .35s

Arnoldi- ased model redu tion used amatri solution to ompute ir uit

response ± Requires repeated fa torizations, eigenvalue

al ulations, and time e ponential evaluations




Conclusions

The proposed metric determines anupper bound on coupled noise for RC and over-damped RLC

interconnects ± Metric becomes less accurate as rise

time decreases

The proposed metric is much more

run-time efficient than circuitmodeling methods



MEMS Research Laboratory Joe Zendejas and Jack W. Judy

Improved Crosstalk Modeling for Noise

Constrained Interconnect Optimization

Jason Cong, David Zhigang Pan &Prasanna V. Srinivas

Department of Computer Science, UCLAMagma Design Automation, Inc.

2 Results Way, Cupertino, CA 95014




Motivation Deep sub-micron net designs have higher

aspect ratio (h/w) ± Increased coupling capacitance between nets

Longer propagation delay

Increased logic errors --- Noise

Reduced noise margins

± Lower supply voltages

± Dynamic Logic

Crosstalk cannot be ignored




Aggressor

Victim

Aggressor / Victim Network

Assuming idle victim net

± Ls: Interconnect length before coupling

± Lc : Interconnect length of coupling

± Le: Interconnect length after coupling

Aggressor has clock slew t r




2- Model Victim net is modeled as 2-RC circuits

R d : Victim drive resistance

C x is assumed to be in middle of Lc

Rise timevictim / aggressor

coupling capacitance




Aggressor

Victim

2- Model Parameters

2

e

L l

C C C !

12

sC C ! 2

2

s eC C

C

!




Analytical Solution




Analytical Solution part 2 s-domain output voltage

Transform function H (s)






Simplification of Closed Form Solution

Closed form solution complicated Non-intuitive

± Noise peak amplitude, noise width?

Dominant-pole simplification




Dominant-Pole Simplification

RC delay from upstream resistance of coupling element

Elmore delay of victim net




Intuition of Dominant Pole Simplification

v ou t

rises until tr and

decays after

vmax evaluated at tr




Extension to RC Trees

Similar to previous model with addition of

lumped capacitances




Results

Average errors of 4

95 of nets have errors less than 10






Effect of Aggressor Location As aggressor is moved close to receiver,

peak noise is increased

Ls varies from 0 to 1mm

Lc has length of 1mm

Le varies from 1mm to 0




Optimization Rules

Rule 1:

± If R sC

1< R

eC

L

Sizing up victim driver will reduce peaknoise

± If R sC

1> R

eC

Land t

r << t

v

Driver sizing will not reduce peak noise

Rule 2:

±

Noise-sensitive victims should avoidnear-receiver coupling




Optimization Rules part 2 Rule 3:

± Preferred position for shield insertion is near anoise sensitive receiver

Rule 4:

± Wire spacing is an effective way to reduce

noise

Rule 5:

± Noise amplitude-width product has lower

bound

± And upper bound




Conclusions

2-model achieves results within6 error of HSPICE simulation

Dominant node simplification givesintuition to important parameters

Design rules established to reducenoise




References

Anirudh Devgan, ³Efficient Coupled Noise

Estimation for On-chip Interconnects´, ICCAD,

1997.

J. Cong, Z. Pan and P. V. Srinivas, ³Improved

Crosstalk Modeling for Noise Constrained

Interconnect Optimization´, Proc. Asia South

Pacific Design Automation Conference

(ASPDAC), Jan. 30 - Feb. 2, 2001, Pacifico

Yokohama, Japan.

Documents

noise modelling