Noise Canceling in 1-D Data: Presentation #2

Seri Rahayu Abd RaufFatima BoujarwahJuan ChenLiyana Mohd SharippArti Thumar

M2

Jan 24, 2005Architecture Proposal

Overall Project Objective: Implementing Noise Cancellation Algorithm in Hardware

Status

• Design proposal (Done)• Architecture proposal:

– Final algorithm description (Done)– High level simulation in C (Done)– Mapping of algorithm into hardware

(Done) – Behavioral Verilog simulation and test

bench (Debugging)• To be done:

– Floor plan– Structural Verilog– Layout– Spice simulation

Design Decisions

• Use 16-bit floating point numbers approximating up to 10-5

• Choose M=1 because target applications do not usually have higher harmonics

• Change integer multipliers and adders to floating point

• Make a bigger ROM table for the sine and cosine functions

Algorithm Description

• Goal: To minimize noise• Algorithm: Based on adaptive

filtering depending on signal weights

• Pseudo-code:i) Take the input signal and model it

using Fourier Transformii) For each sample, model it by

approximating the weight constant and feeding it back to the next sample

iii) Each sample model is then subtracted from the original input signal to monitor the error

Original Flow-chart

Revised Flow-chart

The Micron Experiment

High Level Simulation in C

Simulation of input before the modification

Simulation of input file after the modification

Error comparison

Mapping of Algorithm into Hardware

• Major functional components:– Floating point multipliers (FPM)– Floating point adders (FPA)– 16-bit Registers (Reg)– ROM – sine, cosine

– SRAM – μ, μ0, ω0

FP

A

w0 RO

M

FP

M

cos

FP

A

sin

FP

M

x2

FP

S

out

input

FP

MShifter

FP

M

FP

M

x1

error

mu

sumw0

FP

AF

PA

w1w2

Block Diagram

Behavioral Verilogalways@(datum)begin

w1=0;w2=0;offset = 10;in = datum - offset;sumw0 = sumw0 + w0;x1 = sin(sumw0);x2 = cos(sumw0);

/* output = truncated Fourier Series*/out = 0;out = w1 * x1 + w2 * x2;

/* calculate error*/e = in - out;

/*update amplitude weights */temp = 2*mu*e;w1 = w1 + temp*x1;w2 = w2 + temp*x2;

end

Revised Transistor Count

Part Transistors

16-bit FPA 5x500 = 2500

16-bit FPM 5x4000 = 20000

SRAM 500

ROM 1600

Registers 7x16x14 = 1568

Total ≈ 26168

Challenges…

• Timing issues– Need to reuse hardware

(multipliers)– Clock skew – Pipelined architecture to

increase speed and throughput

• SRAM implementation• ROM implementation• Transistor count is too high

Questions?