NF-Coupling w PCB Layout Fwj

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RLPLEDSource

Coupling

Victimvi

Source

RLP

M

LEDL2

Victim

L1

dt

didi1M2

dt2Lv +=i

Fig. 1. Magnetic coupling bet-ween two loops.

Teaching Near Field Coupling with PCB layout

W.-J. Timothy Foo1, Johnny Chee2Ngee Ann Polytechnic, School of Engineering, ECE Division, BME Center

1 Email: [email protected] Email: [email protected]

Abstract A novel EMC laboratory experiment toillustrate the effects of near field coupling is presented.Using two separate printed circuit boards (PCB), one beingthe emitter PCB with a digital oscillator circuit drivingcurrent in a loop, and the other being a receptor PCBhaving passive loop of identical size. An LED on board thereceptor PCB gives visual feedback on the intensity of thecoupling. The experiment helps to illustrates the effect ofimplementing several design rules. The effects are analysedusing equivalent circuits to explain coupling.

Lessons learnt from this experiment can be readilyapplicable to Multi-layer PCB design.

I.INTRODUCTION

In teaching medical instrumentation to our second year

students, a chapter on EMC supported with a 2 hour

laboratory experiment has been added to the curriculum.

The goal of the chapter is to demystify EMC and help our

students develop useful skills especially when handling

high-speed digital and radio-frequency designs.

We decided to use the limited time available for the

experiment, to teach EMC with respect to some design

rules for high-speed digital systems and its effect on PCB

layout. One design rule [1] states that lateral separation

is more effective than vertical separation, another statesthat keep loop areas small while yet a third states that

Chose logic families that are no faster than necessary

for the purpose of the design.

The experiment involves quantifying the effect of near

field coupling between an inverter driving a load, to an

unintentional receptor circuit in the light of those rules.

II.THEORY

An inverter (74ACT04) driving a low impedance load

RLP of 10 via a rectangular loop (PCB track) acts likethe primary winding of an air-core transformer. The

second PCB with an identical loop can be used to

simulate additional layers on a multi-layer PCB design.

This loop on the second PCB, acts like a secondary

winding of one turn. An LED was used in the secondary

loop to visually demonstrate that near field coupling is

not a negligible condition. An ultra bright LED

dramatizes the effect. Low-cost, large bandwidth digital

storage oscilloscopes (DSO) make it practical to conduct

the experiment for each of the 10 groups of the class of

20 students.

The TTL inverter switches at 10 MHz driving a load

current around a rectangular loop. The excitation circuitwas originally designed for radiated emission in the far

field [2]. This experiment was inspired by another

coupling experiment [3] that uses a RF sinusoidal

waveform generator with an amplifier acting on a circular

loop, and [4] that uses other more specialized instruments

like a vector impedance meter or LCR meter.

III.TEST SETUP

Firstly, the experiment was used to investigate how

certain PCB copper track layout patterns can be

susceptible to magnetic field coupling. The effect of both

vertical and horizontal (or lateral) separation between the

primary and secondary loops was demonstrated. An

extension of the experiment involves investigating theeffect of an open-circuit in the primary loop. Further

steps in the experiment required a sheet of metal to be

placed under the primary loop with the secondary loop on

top. This conductive plane acts as a shield and

demonstrates the effect of Lenz Law. Finally the

experiment gets the student to observe the effect of using

different IC families on near field coupling.

A.Near Field Radiated Emission and Magnetic Coupling Near-field coupling

dominated by the H

field as in the case

between two loops

can be modeled by

the mutual induc-

tance M, the self

inductance of the

secondary loop L2

and the rate of

change of the

currents in both the loops. M is determined by: (i) the

inductance of both loops which is a function of the area

covered by the loops and (ii) the coupling factor, k as in

the equation shown above.

B.Test EnvironmentThe circuit for the emitter PCB was designed such that

different loop sizes and hence their loop areas can be

selected by switches [2].

The receptor PCB has a single loop connected to an

LED which acts as a load. The LED gives a visual

indication of the intensity of the interference. The

receptor PCB is placed first on top of the emitter PCB

with their copper track loops insulated from each other

by a sheet of thin 0.2 mm plastic film.. Large C-shaped

clothes pegs secure the two PCBs together and keep theirseparation constant. The experiment is conducted well

21 LLkM =

Electromagnetic Compatibility, 2006. EMC-Zurich 2006. 17th International Zurich Symposium on , vol., no., pp. 557-560, 27

Feb.-3 March 2006


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LED as load on

secondary loop as

measurement and

observation location

14.8 cm

away from large metallic structures or surfaces and does

not required a shield room.

C.Alignment and Measurement ReferenceThe loops of the two PCBs are aligned at 10MHz to

obtained maximum interference. This is visually

observed by maximum brightness of the LED on the

receptor PCB and the induced RMS voltage as measuredby a digital storage oscilloscope.

Switches on the primary loop are first used to select the

largest of the two primary loop areas. Measured intensity

of the induced voltage vi,for the larger primary loop viL,is and used as the reference to calculate the coupling in

dB to compare the results

from the smaller primary

loop induced viS.

Fig. 1.

Fig. 2. Selected loop sizes on the digital emitter PCB acts as aninterfering source. SW2 and SW3 are shown in the large loop position. Dimensions as shown are used to determine the loopinductances and capacitances for the equivalent circuit.

Fig. 3. Secondary loop or victim circuit.

D.Instrumentation SetupThe experimental boards was designed to operate from

either a standard DC Power Supply or from a 9V battery.It is fitted with sockets for a DIP (dual inline package)

TTL/CMOS oscillator module or in the place of the

oscillator module connect to a standard laboratory signal

generator. If common mode currents is a problem, than

these boards can be operated from a 9V battery and the

plug-in oscillator module [2]. Voltage measurements are

measured by the build in function of the DSO to compute

the cyclic RMS value of the waveform done by taking the

average over 64 cycles to reduce the effect of common

mode interference from the mains. One important point

to note is the built in algorithm to detect for the

complete cycle can often give an erroneousinterpretation of what is a full cycle of the fundamental.

This is especially true when the coupling is week and the

measurement is done in the presence of strong harmonics

from a complex waveform. Care have to be taken to

check the location of the boundary cursers to ensure that

complete whole number of cycles are selected by the

DSO to compute the RMS value.

IV.PROCEDURE AND RESULTS

A.Frequency ResponseMeasurements are made as a ratio ofvi, resulting from the

two sizes of the primary loop areas. These are repeated

at different frequencies between 100kHz to 15MHz. The

student is expected to be calculating and plot the

coupling ratio as the experiment proceeds. The results of

the frequency response characteristics are graphically

illustrated in Fig.4.

Coupling Reduction when primary loop (RLP

=10

) is reduced by half size, secondary loop

loaded by LED

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

0 2 4 6 8 10 12 14 16

freq (MHz)

dB

coupling

reduction (dB)

Fig. 4. Frequency response characteristics between full and halfprimary loop size.

Fig. 5. Picture showing the setup for the frequency responsemeasurement using a DC Power Supply and a Function Generator,with X, Y & Z axis orientation.

B.Vertical SeparationMeasurement of is done (at 10MHz) to investigate the

combined effect of different vertical (Z-axis) separationon the coupling. Small pieces of PCB laminates (with no

copper foil!) of 1.5 mm thick are used as spacers.

SOURCEMain PCB

Primary loop

VICTIM

secondary loop

with LED

=

iL

iS

v

vdBCoupling 10log20)(

4

load on primary

loop, RLP=10

14.8 cm1

2.2cm

74ACT04

1 mm

X

Y

Z

Electromagnetic Compatibility, 2006. EMC-Zurich 2006. 17th International Zurich Symposium on , vol., no., pp. 557-560, 27 Feb.-3

March 2006


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Vertical Separation0.2 mm

(minimal)

1.5 mm

(1 spacer)

3 mm

(2 spacer)

Circuit (s) Topology and resultant

Coupling Ratio (dB)L S L S L S

RLP=10 0 0.3 (ref*) -2.51.0 -2.50.1 -6.00.2 -3.90.1 -7.3LED

RLP=open -2.4~-5.3 -6.6~-8.4 -6.9~-10.3 -10.3~-14.6 -12.0~-12.8 -16.7~-18.9

10k RLP=10 0.50.2 -3.3 -3.4 -7.1 -4.9 -8.7

RLP=10 -3.00.1 -9.11.4 -8.00.3 -12 -12 -16CP LED

RLP=open -0.9 -1.6 -4.70.3 -9.10.4 -9.4 -11.8

CP, 10k RLP=open -3.5 -6.71.7 -8.4 -13 -12 -16

L = Large Pri. Loop, S=Smaller Pri. Loop, CP= Conductive Plane under Pri. Loop, LED = LED as load on Sec. loop, 10k= resistive load in Sec. loop. Unless otherwise

stated all measurements are better than 0.4dB (or in absolute terms 5%).

TABLE I,SUMMARY OFNEARFIELD COUPLING AT VARIOUS VERTICAL SEPARATION

IC (Technology Family) ACT04 (ref) 74F04 74HCT04 74S04 74LS04 std. TTL

Coupling Ratio (dB) 0 0.1 -5.0 -5.0 0.6 -6.3 0.5 -7.6 0.5 -10.0 0.5

TABLE II,SUMMARY OFNEARFIELD COUPLING FROM USING ICS OF VARIOUS TECHNOLOGY FAMILIES

The glow is very dim and may not be readily seenunless the user look through the LEDs lens. Loading

and common mode interference can be a problem at this

stage.

Fig. 6. Cross sectional view of the stack with XZ planeorientation. Stack is shown, (a) at the minimal space between thetwo loops (without spacer) and (b) with 1.5 mm spacers.

C.LED vs Resistive loadA control measurement is made to check the validity

by using a resistor in place of a LED as a load in the

secondary loop. This is done with another identical sec-

ondary loop fitted with a 10k load. The results of theexperiment with the LED and 10 k load on thesecondary are tabulated in Table 1. These empirical

results show that the difference is minimal at 0.8dB.

D.Horizontal or Lateral SeparationWhile aligning the two loops in Subsection A the

student would have the opportunity to observe that a

lateral offset of 4 to 5 mm can reduce the coupling by

about 2dB. This is done by shifting the secondary loop

in the:

(i) X ;(ii) Y and

(iii) XY direction.

In all three cases the target is to obtain a value of the

horizontal separating distance where the reduction in the

coupling is roughly equivalent to that of the reduction in

primary loop area by half. A coupling reduction of 2.5dB

can be obtain by x=5mm OR alternatively y= 4mmORx=2mm,y=1.7mm (estimated 0.2mm).

E.Effect of an Open Circuit in the Primary Loop The primary loop can be made to be open-circuited in

3 (three) places. Each will show different results.

There are 3 variables (RLP and switches SW2 and

SW3) making a set of 8 different possibilities. To keep

the test measurement simple, one measurements are made

(with SW2 and SW3 flip UP (as in the position for the

large primary loop) with RLP removed and no spacers

between the two loops at 10MHz.

F.Conductive Plane and IC FamiliesIn this subsection, a metal plate is placed beneath the

primary loop. The student will observe that the metal

plate is not connected to the Ground of the primary

circuit and yet the presence of the metal plain will reduce

the coupling. This is Lenz Law in action!

Finally, the student can replace the inverter on the PCB

with an IC from different TTL families and take their

investigations to measure the coupling by ICs types:

ACT; F; HCT; LS and standard TTL. The result shows

that digital circuits implemented with ICs having slower

response times will have less coupling problems.

V.DISCUSSION WITH STUDENTS

The variation of the coupling as the frequency changes

from 100 kHz to 15MHz points to the presence of many

modes. When the primary loop area changes by half

(3dB), coupling from the frequency response

characteristics shows 2.40.7dB,inagreementwiththeory.The empirical results fromsection IV sub-part B and E,

suggested that a doubling of the vertical distance roughly

translate to 3dB (1.3~1.6dB without the conductive

plane, to 3~4dB in the presence of the conductive plane).

unless the load on the primary loop is open then the

measurement became more erratic. A mixture ofdifferent coupling modes is in play. Much care was

needed to avoid the pit falls of trusting the algorithms

used by the DSO (seePart III sub-part D). The

(a)

Victim circuit, secondary loop

tape

(b) 1.5 mm

spacer

Z

Y X


March 2006


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conductive plane becomes the coupling plane negating

the coupling from the metallic parts of the primary loop!

Since the conductive plane is so much larger. The

vertical separation had no effect!

The results from part III D, shows an asymmetric res-

ponse to lateral offset between the two loops. The

rectangular loop is longer in the X direction and more

lateral offset between the two loops are needed in the Xdirection to reduce the coupling by the same amount! It

turns out that the ratio of the rectangle, length (X) to

breath (Y) is 1.2. The lateral offset ratio is 1.25.

The first reaction is the intensity of the LED as it reacts

to the energy collected from the coupling. At the

maximum coupling position a high efficiency or ultra-

bright LED can really shines with an intensity that

surprises the uninitiated. The second reaction is that the

coupling is not entirely inductive because when the

primary is open, the interference remains, abet with the

LED much darken.

It is possible to develop an equivalent circuit. The

derivation of circuit inductance is a task for the over-

acivers [7, 8]. Fortunately the www can provide tools to

get an estimate. The full size primary loop L1, was

calculated with [5] using a wire of radius 0.32 mm being

equivalent to the surface area or cross section perimeter

to that of a flat PCB track of 1 mm width, considering

that skin depth , is 0.1 mm at 350kHz. L1.works out to be 570 nH. The inter-track capacitance C1 and C2 can

be found to be 5.4pF, by using the well know formula for

two parallel plates, similarly C3 can be estimated to be

4.1pF. The assumption being r=4.7 for FR4 used.When the smaller primary loop S, is used the smaller

primary loop changes L1 to 400nH and C1 and C2 isreduced to 1.7pF. These parameters are used to create a

more sophisticated equivalent circuit that can be

simulated using SPICE. LT-SPICE [6] was used for the

calculations and the RMS values are used to determine

the ratio of the reduction in coupling. The student will

find out that the rise and fall time of the IC driving the

waveform is important.

Fig. 7. Equivalent Circuit with SPICE simulation parameters.

Proper selection of tr and tf and K (usually between 0.8

and 1.0) will create simulation that shows a resulting

reduction in coupling (of 1.9dB) in agreement with

measurement results. It compares favorably with the

measurements.

VI.ADDITIONAL EXPERIMENTS

Further to this, a second experimental board with

dominant capacitive coupling is developed and illustrates

the same coupling principles with capacitive coupling as

the starting point. Similarly, the displacement currents

are strong enough to light up an LED!

VII.CONCLUSION

The experiment described in this paper demonstrates

the effects from a combination of inductive and

capacitive coupling with measurement that are supported

by simulation in the light of some PCB design rules. The

experiment on near-field coupling are part of the course

work in developing EMC skills in PCB layout for

medical instrumentation. On the surface, EMC seems

like some kind of Black Magic however the actual

situation can be simple enough to be analyzed by

students. In some of the steps, one type of coupling is

predominant but in others there is a combination of twotypes of coupling. It prompt the student to use analysis

to estimate the various parameters that affect coupling

and can use the skills acquired to analyze the dominant

mode in every EMC situation.

ACKNOWLEDGEMENT

The authors wish to acknowledge the assistance and

support of all those who contributed towards the making

of the experiments a reality, in particular the technical

support officers at the BME Center at Ngee Ann

Polytechnic.

REFERENCES

[1] W-J Foo, A Qualitative Evaluation of Design Rules relating toPCB Design for EMC, MSc Thesis, Dept of Electronics,University of York, Sept 22 1997, Research Supervisor: J FDawson, http://www.geocities.com/timfoo6143/Design_Rules.pdf

[2] M P Robinson and T M Benson and C Christopoulos and J FDawson and M D Ganley and A C Marvin and S J Porter and D WP Thomas, Effect of Logic Family on Peak Radiated Emissionsfrom Circuit Boards, 10th International Conference onElectromagnetic Compatibility, IEE Conference Publication No455, pages 9499, 1-3 Sept 1997.

[3] Manfred Albach and Hans Rossmanith, Teaching CouplingMechanisms A Case Study, 2003 IEEE Symp. on

Electromagnetic Compatibility, Boston, USA, Aug 2003, pages160165, IEEE Cat No 0-7803-7835-0.

[4] J L Drewniak, T H Hubing, T P VanDoren, and Fei Sha,Integrating Electromagnetic Compatibility Laboratory Exercisesinto Undergraduate Electromagnetics, 1995 IEEE Int. Symp. onElectromagnetic Compatibility, Atlanta, Aug, 1995, pages 3540,IEEE Cat No 0-7803-2573-7

[5] Inductance of a Rectangular Loop form with a round wire,http://emcsun.ece.umr.edu/new-induct/rectgl.html

[6] LT-SPICE, using the measure function to calculate the effectiveRMS value, a freeware from http://www.linear.com

[7] Frank B J Leferink, Inductance Calculations; Methods andEquations, 1995 IEEE Int. Symp. on Electromagnetic Com- patibility, Atlanta, Aug, 1995, pages 1622, IEEE Cat No 0-7803-2573-7

[8] A E Ruehli, Inductance Calculations in a Complex Integrated

Circuit Environment, IBM Journal of Research and Development,vol. 16, Sept 1972, pages 470481


March 2006

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NF-Coupling w PCB Layout Fwj