New Materials in Memory Development Sub 50 nm: Trends in Flash and DRAM

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DOI: 10.1002/adem.200800298
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New Materials in MemoryDevelopment Sub 50 nm: Trends inFlash and DRAM** By Karl Heinz Kuesters, Marc Florian Beug, Uwe Schroeder,Nicolas Nagel, Ulrike Bewersdorff, Gerald Dallmann, Stefan Jakschik,Roman Knoefler, Stephan Kudelka, Christoph Ludwig, Dirk Manger,Wolfgang Mueller* and Armin Tilke*
New materials are of key importance for scaling memories in the sub 50 nm generations. Currentlyhigh-k materials and metal gates are investigated for usage in Flash and DRAMmemory. However, therequirements in the applications are different, leading to different material combinations. This papergives an overview on new materials with focus on memory applications.

1. Introduction

Flash and dynamic random access memory (DRAM) are

the main memory market segments. Memories for mass

storage applications are cost-driven. The goal of newmaterials

is to allow aggressive scaling of ground rules for these

technologies. Data-Flash offers the lowest cost per bit of all

memories. The aggressive scaling of cell size per bit continues,

around 2010 we expect production to be at 36 nm ground

rule[1] and the cell size will be around 0.005mm2. Today, the

vast majority of data Flash devices are based on NAND

architecture and floating gate devices (see Reference [2–4]). To

achieve generations with a floating gate smaller than 40nm,

innovations have to be made, for example, in dielectric

materials: here high-k devices can offer a better coupling

between the floating and control gates.

[*] K. H. Kuesters, F. Beug, U. Schroeder, N. Nagel,U. Bewersdorff, G. Dallmann, S. Jakschik, R. Knoefler,S. Kudelka, C. Ludwig, D. Manger, W. Mueller, A. TilkeQimonda Dresden GmbH & Co. OHG Konigsbrucker Strasse180, 01099 Dresden, [email protected]; [email protected]

[**] This work was financially supported in part by the EuropeanCommission in the projects GOSSAMER and PULLNANO,and by the Federal Ministry of Education and Research of theFederal Republic of Germany (project nos. 01M3167 A and01M3171 A).

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For ground rules smaller than 30nm, floating gate

technology will be challenged by charge-trap technology.[5,6]

The charge storage in a nitride-trap layer allows some

limitations of floating gate technology, such as increased

gate-to-gate coupling at smaller groundrules, to be overcome.

However, charge-trap technology has to be based on new

dielectrics, for example, between the charge-trap layer and the

control gate,[7] in order to suppress electron injection from the

control gate into the charge-trap layer during erase operations

(‘‘erase saturation’’).[8] In addition, metal gates with high

work-functions are essential. The best known gate stack is

TANOS (TaN gates, Al2O3, nitride charge-trap layer, oxide,

silicon).[5,6] One of the key challenges for these new layers is

data retention.[7]

DRAM has also seen a continuous shrink of design rules;

around 2010 production will be at 45 nm ground rule,[1]

leading to a cell cell size of 0.012mm2 in a 6F2 cell and

0.008mm2 in a 4F2 cell. The key challenge for DRAM in

shrinking cell size is the requirement to keep the capacitance

of the memory capacitors the same as in previous generations

while reducing the cell area (see Reference [10]). New

dielectrics for capacitor scaling have to be considered for

the scaling of equivalent oxide thickness (EOT) to 0.5 nm by

the end of the decade (International Technology Roadmap for

Semiconductors; ITRS),[1] dielectrics with k> 50 have to be

combined with a three-dimensional metal-insulator-metal

(MIM) structure. In DRAM circuitry, device performance

requirements will become more demanding. Materials with a

high dielectric constant for metal oxide semiconductor (MOS)

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K. H. Kuesters et al./New Materials in Memory Development

Fig. 2. TEM picture of a floating gate structure in 48 nm technology. Isolation floatinggate to control gate by a combination of 5 nm oxide and 7 nm Al2O3.

transistors, which are already used in logic mass production,

will be introduced to give, as in logic devices, advantages in

leakage control and voltage scaling. For DRAM the new

materials have to be adapted to the DRAM process

environment, especially to the thermal budgets.

For both Flash and DRAM the challenges in cell and device

optimization have to bemetwhile introducing new patterning

techniques – in the sub 40 nm range the limits of optical

lithography are reached. Techniques like integrated self-

aligned double patterning are introduced to allow patterning

down to the 2x nm range. The combination of new materials

for hardmasks/self aligned features is essential for mastering

2x nm structures in multi-gigabit devices; the patterning of

structures including new materials will be a key aspect to

master the next generations of technology.

2. Flash Technology

Figure 1 shows the basic structure of a floating gate cell and

a charge-trap cell. Both cells contain a transistor as the storage

element; in both cells the threshold voltage of the transistor

(which defines the bit information stored) is determined by

the amount of injected charge. In programming and erase, the

charge must be transferred to and from the charge storage

layer overcoming the large potential of the bottom or

tunnelling dielectric.

In the standard floating gate structure, the charge is stored

in a polysilicon floating gate, which is isolated from the silicon

substrate by a tunnel-oxide of width >8 nm, and from the

control gate by an inter-poly-dielectric (IPD), typically oxide/

nitride/oxide (ONO). The IPD dielectric has to be thick

enough to prevent leakage, but thin enough to give a good

electric coupling between both gates for program and erase

operation. The scaling limitations of the tunnel-oxide and the

interpoly dielectric are key issues for this technology.[2] At

scaled dimensions, the coupling of the gates will be reduced,

while parasitic coupling between cells increases.

In the standard charge-trap cell, the charge is stored in a

nitride layer, isolated by oxide from silicon and from control

gate. The charge is now highly localized and capacitive

coupling between cells is much reduced compared to floating

gates. However, here the tradeoff between bad retention and

slow erase is the key challenge.

Fig. 1. Basic structure of a floating gate cell and a charge-trap cell.

242 http://www.aem-journal.com � 2009 WILEY-VCH Verlag GmbH & C

2.1. New Materials in Floating Gate Technology

For the IPD, the use of high-kmaterials instead of the ONO

can improve the coupling between the floating and control

gates.[2] A lower ‘‘effective oxide thickness’’ (EOT) (improving

the coupling of both gates) is possible while avoiding an

increase in leakage. Figure 2 shows a transmission electron

microscopy (TEM) picture of a floating gate, which is isolated

by a combination of 5 nm oxide and 7nm Al2O3 from the

floating gate. Accordingly, the voltages required for program

and erase should be reduced by approximately 2V, which is in

good agreement with the gate coupling ratio increase as

evaluated in 3-D field simulations. The combination oxide/

Al2O3 allows a thinner EOT than ONO-IPD (which has a limit

of 12 nm because of leakage). Since an Al2O3 layer without

oxide buffer layer has a disadvantage in terms of leakage

under retention conditions, only the combination of Al2O3 and

oxide is suitable to reach the strict retention requirement of a

Flashmemory. The oxide buffer layer is chosen to be as thin as

possible with respect to leakage current requirements.

Materials with higher k-values than Al2O3 would be very

interesting with respect to leakage due to reduced electrical

fields. However, this advantage generally has to be paid for

with lower band-gaps and lower breakdown fields than

Al2O3. This has been shown to be critical for the Flash

application where maximum electrical fields of 8MVcm�1 are

applied under programming conditions.

2.1.1. Summary.

The target material for inter-poly-dielectric (IPD) is Al2O3

(6–10 nm). Process integration could be achieved with a metal

gate and a sufficiently thick SiO2 buffer layer (approximately

4–5 nm) between the Al2O3 and the floating gate. The

optimisation target is: a) the lowest leakage current to fulfil

retention requirements, b) compatibility with high voltages

(>8MVcm�1), and, c) reduction of trap density in Al2O3.

Besides work on IPD, the tunnel-oxide is also getting more

focus; however, band-gap engineered tunnel-oxides for

floating gate need significant new development efforts.

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Fig. 3. Layer structure of charge-trap cell (charge storage in nitride). For erasure, theinjection of holes from silicon into charge-trap nitride gives a reduction of Vt; however,in the case of ‘‘erase saturation’’ electrons from the gate are also injected into the nitride.

Fig. 4. Reduction of Vt during erase. The erase to lower Vt stops with the erasesaturation. For faster, erase the high-k top oxide is thinned, for shifting ‘‘erasesaturation’’ to lower Vt the gate work function is tuned.

Fig. 5. Integration of a charge trap cell based on TANOS into a sub 50 nm ground ruleNAND string.

2.2. New Materials in Charge-Trap Technology

The use of charge-trap technology in NAND applications

requires programming and erase by Fowler-Nordheim

tunnelling of carriers: during programming and erase,

respectively, electrons and holes are injected from the silicon

into the charge-trap layer. However, since its invention 30

years ago, ‘‘erase saturation’’ has prevented the introduction

of charge-trap devices into the standard NAND-Flash

applications: when erasing to lower Vt, holes are injected

from silicon into charge-trap nitride; the injected charges

increase the field across the topoxide between the nitride and

the gate; therefore electron injection from the gate into the

nitride is enhanced and as a result the erase Vt level saturates

(Fig. 3 and 4). Furthermore, the erase Vt level depends on the

voltage used for erase: higher erase voltages cause a higher Vt

saturation level. In particular, for gate stacks consisting of

a polysilicon gate and a SiO2 topoxide in combination with a

bottom oxide thicker than �3.5 nm, erasure to less than

Vt¼ 0V is difficult to achieve. Better results can only be

achieved for a pþ poly-Si gates due to their higher work-

function compared to nþ gates. A reduced electron injection

from the gate and, therefore, lower saturation levels for pþ

gates can be observed.[8] Before introduction of high-k/metal

gate into charge-trap cells, the following two options were

implemented to avoid erase saturation:

– A

–

AD

very thin bottom-oxide of <3 nm shifts the competition

between hole injection from substrate and electron injection

from the gate in favor of hole injection;

however, in this case the thin bottom oxide

causes bad data retention, electrons can

backtunnel into the substrate during

anneal/room-temperature storage. There-

fore very thin bottom-oxides cannot be

used for a typical data Flash memory.

A different scheme for program and erase,

Fig. 6. Erase for different gatestacks: A) SANOS, B) TANOS, and C) optimized TANOS.

using hot electron/hot hole injection,[11]

which causes a different array architecture

toNANDand different product properties:

for example, a higher write /erase current

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per cell limits the parallelism of write/erase operations over

the array.

The only solution for charge-trap cell in NAND technology

is the use of new materials (see Fig. 4): a metal gate with

work-function towards 5.1 eV reduces the electron injection

over the top oxide, a high-k top dielectric between the nitride

and the gate reduces the field across the top-dielectric oxide.

The integration of these materials leads to some challenges.

Intensive work has been done on TaN metal gates and Al2O3

top dielectrics.[12–15] The integration of these new materials in

a sub 50 nm NAND technology included efforts in material

optimization, such as work-function tuning, but also in

etching/patterning of these materials. Figure 5 shows the

example of integration into a sub 50nm groundrule NAND

string.

The results for erasure in Figure 6 show the significant

improvements made by process engineering:

– F

ag

igure 6a shows the erase for an SANOS (Si-Al2O3-nitride-

oxide-Si) stack, which already contains Al2O3 as the top

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Fig

24

dielectric, but still has a nþ-silicon gate: erasure below

Vt¼ 0V is not possible; and, for erase voltages of �22 or

�24V, a clear erase saturation is visible at Vt¼ 0V after

100–1 000ms. This result is seen for large capacitors as well

as cells in NAND strings.

– F
igure 6b shows the erase for TANOS, which has a TaN gate
instead of silicon; here a <50 nm ground-rule NAND string

is shown. Erase saturation is visible at a Vt of �2V.

– F

Fig. 8. Retention for different gatestacks: B) TANOS, and C) optimized TANOS.Retention is measured first after programming, then after store at room temperature for1 h, then after 2 h at 200 8C, recording the Vt shift of the programmed level.

igure 6c shows an optimized TANOS gate stack: optim-

ization is not only concerned with the gate-stack materials,

but also other aspects of processing, for example, etching of

the gate stack can affect the composition ofmaterials close to

the etched areas. Therefore a protection of these areas by

spacer techniques, for example, after metal etch, improves

erase results. Here erasure to�4V is possible, aVt of<�2V

can be reached at an erase voltage of 21V within ca. 2ms.

This is sufficient for product requirements.

Besides erase/program performance the key criteria for the

use of a technology in product are endurance and retention.

Figure 7 shows the endurance for the same gatestacks used in

Figure 6. The SANOS stack behaves poorly, the erased level

degrades by 2V after only 100 cycles of write/erase. Here, it is

assumed that the high fields needed for erasure even to 0V

cause the bad endurance. The TANOS stack shows better

behavior – the optimized TANOS shows a degradation of the

erased level of about 1V even for 10 000 cycles. Hence, gate

stack C fulfils the basic requirement for use in products.

Retention has always been a critical topic for charge-trap

devices.[12–15] A typical retention measurement sequence

consists of a first Vt measurement after programming and

subsequent Vt measurements after 1 h of room-temperature

storage and 2h storage at 200 8C. The Vt shift of the

programmed level (typically programmed to Vt¼ 4V) is

analysed. For large TANOS capacitors we obtained a

relatively good result of <250mV (Vt loss after annealing

for 2 h at 200 8C). However, for cells in NAND strings with

<50 nm ground rules, the Vt loss was 1,7V for gate stack B,

and 800mV for gate stack C (Fig. 8).

Various factors contribute to retention: large capacitors

effects from the materials are relevant, such as detrapping

from the nitride trap and escape to gate across the Al2O3

(which has a smaller bandgap than SiO2).[16] Here, because of

the difference between large structures and NAND strings at

ground rule, the geometry effect for small ground rule

. 7. Endurance for different gatestacks: A) SANOS, B) TANOS, and C) optimized TA


structures seems to be the most important. The comparison of

gate stacks B and C shows that the processing of the gate-edge

is relevant. It is also known that a continuous nitride layer,

which is extending across the cell, can lead to lateral loss of

trapped charges, which would affect both stacks B and C.

More work is required to reach retention loss after anneal of<

200mV, as is commonly seen for floating gate cells in current

product applications. This work should focus on thematerials,

as well as on the processing and the geometry of the layers in

the cells, for example, a nitride trap layer self-aligned to active

area is very interesting.

A possible optimization of the pure stack retention, as seen

in large capacitor structures, could be achieved by the

introduction of a sealing SiO2 layer in between the nitride

and the Al2O3 layers.[14] However, this layer could adversely

affect the program operation by an enhanced fly-through

effect.[16]

2.2.1. Summary.

The target material is a top oxide of Al2O3 (10–14 nm)

combined with a metal gate (e.g., TaN), optimized to have a

NOS.

o. KGaA, Weinheim

work function close to the valence band edge

of silicon, 5.1 eV. The trend in integration is

the use of a metal gate, optimisation in the

stack etch process for word line patterning

and, possibly, an oxide sealing layer between

Al2O3 and nitride. The optimisation target is

the lowest leakage current, compatibility

with high voltages and reduction of trap

density in Al2O3. Al2O3 is the most interest-

ing material because of its wide bandgap,

high breakdown voltage and minimised

aging during Flash operation. Additional

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Fig. 9. Evolution of three-dimensional structures for trench technology and stacked technology (COB: capacitorover bitline, CUB: capacitor under bitline) (based on Reference [38]).

Fig. 10. Structure of a stacked capacitor: the capacitor is placed on top of the cell transistor (wordline) anddevelopment fron SIS (Si-insulator-Si) to MIM (metal-insulator-metal).[29]

work has to focus on the geometry of the cell. Furthermore, the

nitride charge trap layer should be investigated for trap

density and trap depthmodulation. The keywork topic for the

future is cell retention.

As well as optimization of the top oxide, alternatives to an

oxide bottom oxide have also received attention to improve

erase saturation and to reduce programming voltages: here

band-gap engineering of the bottom oxide (e.g., based on

ONO)[17] is a promising technique.

Fig. 11. Equivalent oxide thickness (EOT) needed depending on the ground rule (trenchand stacked technology).

3. DRAM Technology

3.1. Capacitor Development

The shrink of a DRAM cell, which consists of 1 transistor

and 1 capacitor (1T1C), has to meet the challenge of keeping

the capacitance (ca. 25 fF cell�1) of the capacitor while

shrinking the area on silicon for the devices. Therefore, the

capacitor is built into the 3rd dimension to increase the plate

surface area: for the trench technology the capacitor is placed

ADVANCED ENGINEERING MATERIALS 2009, 11, No. 4 � 2009 WILEY-VCH Verlag GmbH & Co. KGaA

in a trench in the substrate, and, for the

stacked technology the capacitor extends on

top of the transfer gates (Fig. 9 and 10).[10]

Stacked capacitor development put an

early focus on new materials for the dielec-

tric:[18–20] the extension of the capacitor into

the area above the silicon substrate is limited

by mechanical stability and, hence, early

introduction of high-k materials was neces-

sary. Also, the stacked capacitor could – due

to the introduction of high-k materials –

benefit from the lower temperature budget

after capacitor formation of 600–700 8C (vs.

900–1 000 8C for a trench capacitor). Due

to the higher surface area for trench

capacitor structures, ON was kept as the

node dielectric material. Here, capacitance

enhancement was reached by surface area

enhancement due to improved aspect

ratio etches (up to 70:1), introduction of

hemispherical grains and bottle-shaped

trenches.[21]

The required EOT of a stacked capacitor is

shown in Figure 11. Based on improvements

in high-k materials, the EOT of stacked

capacitor dielectric was shrunk from EOT¼1.5 nm at 80 nm groundrule to EOT¼ 1.0 nm

at 55 nm ground rule; the trend will continue

towards EOT¼ 0.5 nm at 40 nm groundrule

(base for this estimate: storage node height

1.4mm).[22]

For the 80 nm generation, commonly used

materials were HfO2–based, such as HfO2/

Al2O3 and HfxAlyOz stacks.[19] A strong

development focus was set on the tempera-

ture stability of the materials.[23] It was shown that MIM

capacitors (TiN electrodes) with a CET of 1.1 nm and

temperature stability of 700 8C can fulfill the stringent

leakage current requirements of the DRAM application

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Fig. 12. ZrO2/Al2O3/ZrO2 (ZAZ) dielectric film in a stacked capacitor.[22]

Fig. 13. TEM cross section of NMOS (dielectric: HfSiON, cap:La2O3, metal: TaC) andPMOS devices (dielectric: HfSiO, cap: Al2O3, metal: TaCN).[37]

(<1� 10�8A cm�2).[19,24] Mixed and laminate films were able

to reach higk-k values by phase optimization of the material

system.

For the 45–55 nm generation (EOT values < 1.0 nm) ZrO2/

Al2O3/ZrO2 (ZAZ) dielectric films were intensively investi-

gated. These films are a combined structure of tetragonal ZrO2

and amorphous Al2O3, showing a low leakage current of

<1 fA cell�1 (<1� 10�8A cm�2) and good reliability even for

EOT of 0.63 nm (Fig. 12).[22]An investigation of ALD ZrO2

growth, crystallization and electrical behaviour is included in

Reference [25,26].

The trend towards higher k-values in DRAM capacitor

engineering will continue. However, the implementation of

materials with higher k-values (see Reference [27]) goes along

with lower band gap[28] and reduced band offset. TiO2 based

materials are promising due to dielectric constants beyond 50,

but in this case the bandgap is significantly lower, in the range

of 3.5 eV. Because of the small band offset between the Fermi

level of the TiN electrode and the conduction[28] band of the

dielectric, it is very difficult to achieve low leakage currents. A

conduction band offset>1 eV can be reachedwith noble metal

electrodes, like RuO2, with higher workfunction values above

5 eV, but these materials are considered to have too high a cost

for production.

At present, efforts towards highest-k dielectrics, like TiO2

and SrTiO3, have increased, together with the work-function

engineering of the metal electrodes; doping of dielectrics/

induced dipoles is also receiving more attention.[29]

3.1.1. Summary.

Current target materials are ZrO2/Al2O3/ZrO2 (ZAZ)

dielectric films combined with TiN electrodes, which allow

an EOT of 0.8–0.9 nm. The leakage currents of<1 FA/cell�1 for

DRAM cells can be achieved. The trend to lower EOT causes

intensive work on higher k-value materials, like TiO2-based

materials and SrTiO3, combined with new RuO2-based

electrodes materials and doping of electrodes materials.

3.2. Logic Devices

The performance of logic devices has been continuously

increasing. From the 45 nm generation onwards, high-k


dielectrics and metal gates have been used in mass produc-

tion. The key challenges of: i) Vt control, ii) keeping a

channel electron mobility >90% for SiO2-based devices, and,

iii) maximum Idsat with minimum leakage currents (minimum

dielectric thickness with EOT <1.5 nm) were pioneered by

logic device development.[30–33]

DRAM will follow the device trend in logic, with the

scaling of voltages to <1V and the performance requirements

of 2GHz data rate. Low power requirements, for example, in

standby current will also become more important. It is

expected that DRAM will utilize the high-k/metal gate

devices in its periphery circuits from the <40 nm generation

onwards. DRAM targets EOT<2 nm at very stringent leakage

current requirements.[34]

A key difference between logic processes and DRAM

processes is the temperature budget after device processing

using temperatures of 800 8C. Therefore the ‘‘gate last’’

process,[31] which is widely used in logic technologies to set

work-functions for NMOS and PMOS,based on the choice of

material, cannot be integrated.

For DRAMonly ‘‘gate first’’[32] processes are considered:Vt

control in HfSiON-gated NFET is obtained by doping with La,

Sc, Er or Sr.[35,36] TheVt tuning is proportional to the net dipole

moment associatedwith theHf-O and rare earth (RE)-O bonds

at the high-k/SiO2 interface. LaO is most effective based onVt,

mobility and reliability. For PFET, Al doping is most common.

A CMOS process using HF-based oxides, suitable for

DRAM and able to give low-Vt CMOS, as required in DRAM,

has been shown, using HfSiON/La2O3 with a Ta2C gate

for NMOS and HfSiO/Al2O3 with a TaCN gate for PMOS

(Fig. 13).[37] This combination of dopedHFSiON dielectric and

metal gates was shown to achieve band-edge workfunctions

and, together with the appropriate post-deposition treatments,


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Fig. 15. Fanout pattern for NAND flash word-line in 30 nm technology (by the spacertechnique).

Fig. 16. Cross-section along word-line of NAND flash device in 30 nm technology. Thechosen double patterning scheme causes an odd/even signature with different active areadimensions for adjacent cells.

a low Vt CMOS integration (as also needed in DRAM) was

shown.

A combination of HfSiON dielectrics and a dual poly-Si

gate process or a thin metal inserted poly-Si (MIPS) gate for

DRAM was reported to significantly increase performance:

based on the implementation in a 50 nm DRAM, the

propagation delay of a CMOS inverter was decreased by

22% with a MIPS gate and the stand-by current was reduced

by one order of magnitude.[34]

3.3. New Patterning Techniques in Memory

Until now, the scaling of ground rules was always

dependant on the introduction of new lithography tools.

With the <40 nm technology generations, optical lithography,

based on 193 nmwavelength andNA¼ 1.35 tools, has reached

its limits. New lithography techniques, like extended UV

(EUV), are not yet available. Therefore ‘‘double patterning

techniques’’ are being introduced for the 30 nm generations.

Different process schemes are investigated (see Fig. 14):

Typically 2 hard-masks are used. The 1st hard-mask is

patterned by lithography and then shrunk to target dimen-

sions. At the two sidewalls of this ‘‘carrier’’ two spacer

(width¼ target dimension) are generated by deposition /

etching, which can be used for pattering the 2nd hard-mask

after the carrier strip (‘‘line-by-spacer’’). Alternatively, the

space between the two spacers can be filled, so that this fill and

the carrier (1st hard-mask) define the dimensions of the

structures after spacer strip (‘‘line-by-fill’’).

The challenges of these new techniques include more

complicated patterning of a full layer stack; here, the use of a

2nd mask to cut lines from a ‘‘line-by-spacer’’ technique may

also be necessary (see Fig. 15 with a fanout of a NAND Flash

gate layer). As a result of the double patterning techniques,

unequal spaces between lines (line-by-spacer) or unequal lines

(line-by-fill) can be obtained, which can influence the

construction of the cells. As an example, the NAND cell in

a 30 nm generation is shown, which may feature odd/even

lines (here active areas) with different area widths for every

2nd line (Fig. 16).

ig. 14. Process scheme for double patterning. Sequences for line-by-spacer (LBS) andne-by-fill (LBF) sub-lithographic patterning techniques (pitch fragmentation).

Fli

ADVANCED ENGINEERING MATERIALS 2009, 11, No. 4 � 2009 WILEY-VCH Verl

4. Conclusion

An overview of new material introduction for scaling

memories in the sub 50nm generations has been given; the

following trends are seen:

– F

ag

lash floating gate: high-k introduction in the 30 nm gener-

ations for inter-poly dielectrics;

– C
harge-trap Flash cells: high-k top oxides and metal gates
allow improvements of erase performance, improvements

in retention are key focus; introduction in Flash 22 nm

generation is expected;

– D
RAM: materials with k-values >60 allow EOT in the
0.5 nm range, which is essential for sub 40 nm generations;

and,

– L
ogic devices in DRAM: performance increase will lead to
introduction of high-k/metal gate devices in the 30–40 nm

generations.

Received: September 10, 2008

Accepted: January 19, 2009

[1] ITRS roadmap, see: http://www.itrs.net/.

[2] T. Mikolajick, Nanotechnology 2008, 3, 351, ISBN

978-3-527-31738-7.

[3] J. H. Park, IEDM Tech. Dig. 2004, 873.

[4] K. Kim, Proceedings of the 21st Nonvolatile Memory

Workshop 2006, 9.

[5] Y. Shin et al., IEDM Tech. Dig. 2005, 13.6.1, 337.

GmbH & Co. KGaA, Weinheim http://www.aem-journal.com 247

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[6] Y. Park et al., IEDM Tech. Dig. 2006, 29.

[7] M. Specht et al., ESSDERC 2003, 155.

[8] H. Bachhofer et al., JAP 2001, 89, 2791.

[9] T. Mikolajick et al., Proceedings VLSI-TSA 2007, 130.

[10] W. Mueller et al., IEDM Tech. Dig. 2006, 14.1.

[11] B. Eitan et al., IEEE Electr. Device Lett. 2000, 21, 543.

[12] C. H. Lee et al., Appl. Phys. Lett. 2005, 86, 152908-1.

[13] C. H. Lee et al., VLSI Symposium Tech. Dig. 2006, 3.4.

[14] L. Breuil et al., Proceedings ICMTD-NVSMW, IEEE 2008,

126, ISBN 1-4244-1546-2.

[15] T. Melde et al., Proceedings ICMTD-NVSMW, IEEE 2008,

130, ISBN 1-4244-1546-2.

[16] A. Furnemont, Proceedings ICMTD 2007, 205.

[17] H. T. Lue et al., VLSI Symposium Tech. Dig. 2008, 116.

[18] U. Schroeder, Freiberger Silicium Days 2007, Freiberger

Forschungshefte, in press.

[19] D. S. Kil et al., VLSI Symposium Tech.Dig. 2004, 73.

[20] U. Schroeder et al., DPG Spring Meeting 2008.

[21] J. Amon et al., IEDM Tech. Dig. 2004, 73.

[22] D. S. Kil et al., VLSI Symposium Tech. Dig. 2006, 73.


[23] Y. Ho, H. Gong, Appl. Phys. Lett. 2002, 81, 4218.

[24] C. Cho et al., VLSI Symposium Tech. Dig, 2005, 36.

[25] W. Weinreich, al. et, AVS-ALD Conference 2008, Bruges.

[26] J.-H. Kim et al., J. Phys. D – Appl. Phys. 2008, 41, 172005.

[27] J. Niinisto, K. Kukli, M. Heikkila, M. Ritala, H. Leskela,

Adv. Eng. Mater. 2009, 11, DOI: 10.1002\200800316

[28] J. Robertson, Solid State Electronics 2005, 49, 283.

[29] S. K. Kim, Adv. Mater. 2008, 20, 1.

[30] R. Chau et al., Electr. Device Lett. 2004, 25, 408.

[31] Y. Tateshita, IEDM Tech. Dig. 2006, 63.

[32] H. R. Harris, VLSI Symposium Tech. Dig. 2007, 154.

[33] M. Chudzik et al., VLSI Symposium Tech. Dig. 2007,

194.

[34] S. Hyun et al., VLSI Symposium Tech. Dig. 2007, 184.

[35] P. Sivasubramani et al., VLSI Symposium Tech. Dig. 2007,

p 68.

[36] S. Z. Chang et al., VLSI Symposium Tech. Dig. 2008, 62.

[37] S. Kubicek et al., IEDM Tech. Dig. 2007, 49.

[38] G. Jin et al., 2nd International Workshop on Nanoscale

Semiconductor Devices, 2005.


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