18 High Frequency Electronics

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LDMOS MODEL

New LDMOS Model DeliversPowerful Transistor Library— Part 1: The CMC Model

W. Curtice, W.R. Curtice Consulting; L. Dunleavy, W. Clausen, Modelithics, Inc.; R. Pengelly, Cree Microwave, Inc.

Anew LDMOS tran-sistor model hasbeen developed as

a collaboration betweenW.R. Curtice Consulting,Modelithics and CreeMicrowave. This article,the first of a two-partseries, describes the back-

ground and development of the model. Themodel has been shown to scale well and fit sig-nal, power and distortion performance for awide range of device sizes.

IntroductionNon-linear transistor models are being

increasingly utilized and demanded by thepower amplifier design community becausethey provide access to multiple simulatorcapabilities, including DC analysis, as well asanalyses of small-signal, nonlinear, timedomain, and complex modulation effects. Theavailability of accurate, validated modelseliminates the need for designers to maketheir own source and load pull and S-parame-ter measurements on every device, and allowfast “what-if” analysis e.g. change frequencyband, drain voltage etc. Savvy semiconductormarketing departments are also recognizingthat more and more design engineers use sim-ulators to minimize design risk, reduce designspins and cut design time. Good models willultimately sell more product.

It is well recognized that excellent powerperformance and linearity can be achieved atlow cost using laterally diffused metal-oxide-semiconductor (LDMOS) transistors. In factthey are the technology of choice for base sta-tion applications below a couple of GHz as

well as many other RF and microwave appli-cations. Existing LDMOS FET large-signalmodels show a number of disadvantages.They tend to show poor prediction of IMDs, donot work in the sub-threshold region, lack adynamic self-heating effect, do not use closed-form analytic equations to represent channelcurrent, have complex extraction routines anddo not scale well with the number of cells.Balancing the trade-off between linearity andefficiency and designing optimal matchingand bias networks requires more accurateLDMOS models with better treatment of theseeffects. Moreover, increasingly complex digitalmodulation schemes are placing increaseddemands on model fidelity through 5th or 7thorder distortion predictions.

This paper describes a new model thatmeets this challenge in an elegant and robustway. Part 1 of this paper outlines the topologyand methods used to extract and validate a

This new LDMOS modelaccurately predicts both

small-signal and nonlinearperformance, and is

scalable for devices ofdifferent sizes and power

output capabilities

Figure 1 · Four region current behavior ofthe 1 watt LDMOS cell device used in thisdevelopment.

From October 2004 High Frequency ElectronicsCopyright © 2004, Summit Technical Media, LLC

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baseline one watt (1 W) cell modelagainst I-V, S-parameter, and load-pull data. Part 2, to be published inthe next issue of this magazine, willdemonstrate the scaling of the modeland integration with package para-sitics and thermal models to create anon-linear model library for an entirefamily of related high power transis-tor products. A 60 watt Dohertyamplifier design example will also bepresented in Part 2.

The library is now available formultiple microwave electronic designautomation (EDA) software tools.

The CMC ModelThe presented model is based

upon the current control characteris-tics described by Fager, Pedro, deCarvelho and Zirath [1]. The keyadvantage of the Fager-Pedro modelis proper treatment of current in thefour regions identified in Figure 1.Shown is the measured I-V behaviorof a 1 watt cell device used in thiswork. Most LDMOS models, includ-ing MET [2] and Yang et al. [3], im-plement a gate current-control char-acteristic that transitions from thesubthreshold region to the linear gatecontrol region directly, without treat-ing the intermediate region, calledthe quadratic region. Fager et al.have implemented an equation andnew parameters to fit the quadratic

region. This leads to better agree-ment with measured IMD and othernonlinear characteristics.

The CMC (Curtice/Modelithics/Cree) model uses the current treat-ment of [1]. Gate charge is parti-tioned into gate-source and gate-drain charge. Each charge expressionis a function of both VDS and VGS.Using charge partitioning, it is possi-ble to fit most LDMOS capacitancefunctions and observed charge con-servation.

The topology of the CMC model isshown in Figure 2. The CMC modelincludes new capacitance functionsas well as modeling of the drain-source breakdown and self heating.

Self heating is treated with a spe-cial circuit as shown in Figure 2. Themodel has four ports, with the extraport providing a measure of the tem-perature rise. The voltage betweenthe external thermal circuit port andthe source node in Figure 2 is numer-ically equal to the junction tempera-ture rise in degrees C. This occursbecause the current source in thethermal circuit is numerically equalto the instantaneous power dissipat-ed in the FET and the resistance,R_TH is numerically equal to thethermal resistance. The RC productof the thermal circuit is the thermaltime constant.

The model also includes a silicon

substrate loss circuit, consisting of aseries combination of Rdd and Cddbetween the external drain andsource terminals. Fiorenza and delAlamo [3] have shown this effect tobe significant in LDMOS powerdevices. The CMC model properlyaccommodates the observed changein pinch-off voltage with tempera-ture as well as breakdown effects.The resulting model addresses thesharp turn-on knee in LDMOS FETsleading to the accurate prediction ofdouble IMD sweet spots in Class ABOperation. It is also wideband, scaleswell, up to at least 30:1, predictsIMDs well with high dynamic range,and predicts correct performanceeven in Class B and C.

The code for the model has beenimplemented to support multiplesimulators, including Agilent’sAdvanced Design System (ADS), andApplied Wave Research’s MicrowaveOffice, with others planned, includingEagle-ware’s HARBEC and AnsoftDesigner.

Model Extraction Efficient and systematic extrac-

tion procedures have been developedand implemented in Agilent Tech-nologies IC-CAP software. The modelparameters for CMC are extractedfrom I-V and S-parameter data usingcustom routines implemented in IC-CAP. The model includes an AREAparameter for relative scaling toother size devices as compared to theoriginal size extracted.

In the example shown in thispaper, a Keithley 4200 was used forDC parametric testing and anAnritsu Lightning vector networkanalyzer was used for S-parametermeasurements. Thermal resistancewas determined using pulsed I-Vmeasurements made over tempera-ture using an Accent OpticalTechnologies Dynamic i(V) Analyzer(DiVA) D225 along with a CascadeSummit 12000 Probe Station andMicrochamber. Relevant techniquesare outlined and validated against

Figure 2 · Topology used in the CMC model.

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the infrared thermal imaging resultsin [4]. This imaging system was usedfor the thermal resistance valuesused in the larger devices of the tran-sistor library to be described in Part 2of this paper, which will appear nextmonth.

Current-Voltage CharacteristicsFigure 3 shows a comparison of

pulsed I-V data to an iso-thermalsimulation made after extraction ofthe model parameters in IC-CAP. Forthis simulation the self-heating isturned off to emulate the iso-thermal

measurement condition representedby the pulsed I-V data.

Figure 4 shows the average DC I-V (static) data for a one watt deviceas extracted in IC-CAP, and alsoshows the model’s I-V characteristicfor this device. In all figures, thesolid, red line is the simulation andthe blue symbols represent the data.Heating effects significantly limit thehigh current values. Figure 3 and 4together demonstrate the properfunctioning of the self-heating model.

Small-Signal SimulationsNot shown in Figure 2 are the

external pad capacitances and leadinductances which are used in addi-tion to better fit measured S-parame-ter data, after extraction of theintrinsic model elements and bias-dependent capacitance functions.This is done by using the developedICCAP routine to manipulate S-parameter data taken at many biasconditions. Figure 5 shows goodagreement with small-signal S-parameter simulations made usingthe CMC model and the small-signalmeasured data. Note in particularthe good fits for S22 and S21 that aresometimes compromised in non-lin-ear FET models, since the dominantparameters (gm and Rds) are derivedessentially from the I-V equations.

Figure 3 · Comparison of pulsed I-V data from a zerovoltage quiescent condition to simulated I-V resultswith self heating turned off.

Figure 4 · Forward DC I-V curves for the 1 watt LDMOScell showing proper treatment of self-heating effects.

Figure 5 · Small-signal simulation for the 1 watt LDMOS cell. Displayed ismeasured S-parameter data (Blue circles) and an Agilent ADS simulationof the CMC model (Red line) at Vgs = 4.8 V and Vds = 25 V.

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Single Tone Large-SignalSimulations

Figure 6 shows a 900 MHz load-pull simulation for the 1 watt cellperformed to arrive at appropriatematching impedances to use for apower sweep. The simulation is com-pared to load-pull data acquiredusing a Maury Microwave ATS load-pull system. Figure 6 also demon-strates simulated and measuredtracking for a power sweep at 900MHz operation using the load andsource impedances derived from theload-pull simulations. The simulation

results shown are in good agreementwith measurements. The load con-tours show a power of 29 dBm wasreached, with close agreement on theoptimal impedance near 50 × (1.6+j2.6), or 80 +j130 ohms.

Two Tone Large-SignalSimulations

Figure 7 shows excellent simulat-ed to modeled agreement obtainedwith two-tone load-pull measure-ments that show about a 38 dBmOIP3 level. Two-tone power sweepsalso displayed in Figure 7 demon-

strate good tracking of IM3 withchanging power.

ConclusionsThis first part of a two-part article

has introduced the CMC LDMOSmodel that was derived to providecomprehensive treatment of LDMOSI-V behavior in the four regions ofsub-threshold, quadratic, linear andcompression, while also accountingfor self-heating, breakdown, non-lin-ear capacitance and careful parasiticmodeling. Measured to modeled com-parisons have validated the model’s

Figure 6 · Single-tone 900 MHz load pull contours areshown in the upper graph. (Blue is measured and Redis simulated data.) The lower graph shows measuredand modeled power sweep data for the matching con-ditions determined from the load-pull simulation.

Figure 7 · Displayed are measured IP3 load-pull con-tours (Blue contours) and the CMC model IP3 results(Red contours) for the 1W LDMOS chip at Vds = 27 V andVgs = 4.8 V with input power (Pin) is set to 0 dBm at 900and 910 MHz. The lower graph shows a 2-tone powersweep with the load condition held fixed at the valuedetermined to be optimal from the load-pull simulation.

October 2004 25

IV, small-signal and non-linear simu-lation accuracy for a 1 watt LDMOSchip. Part 2 will be presented nextmonth, covering application of themodel for a 30-watt transistor, whichis used in the design example of a 60-watt Doherty amplifier.

AcknowledgementsThe authors wish to thank Dr.

Tom Weller of Modelithics, SimonWood, Brian Behrendt and JamesCrescenzi of Cree Microwave, andCharles Baylis, II of the University ofSouth Florida for their contributionsto this work.

References1. Fager, Pedro, Carvalho and

Zirath, “Prediction of IMD in LDMOSTransistor Amplifiers Using a NewLarge-Signal Model,” IEEE Trans. OnMicrowave Theory and Techniques,Vol. 50, No. 12, pp. 2834-2842,December 2002.

2. W.R. Curtice, J.A. Pla, D.Bridges, T. Liang, E.E. Shumate, “ANew Dynamic Electro-ThermalNonlinear Model for Silicon RFLDMOS FETs,” 1999 IEEE MTT-SDigest, pp. 419-422, June 1999.

3. Yang, Yi and Kim, “Accurate RFLarge-signal model of LDMOSFETsincluding self-heating effects,” IEEETrans. MTT, Vol. 49, No. 2, Feb 2001,pp. 387-390.

4. Fiorenza and del Alamo, “RFPower Performance of LDMOSFETson SOI: An Experimental Compar-ison with Bulk Si LDMOSFETs,”IEEE RFIC Proceedings, 2001.

5. Charles P. Baylis II , LawrenceP. Dunleavy, John E. Daniel, “DirectMeasurement of Thermal CircuitParameters Using Pulsed IV and theNormalized Difference Unit,”Submitted December 2003 to the2004 IEEE MTT-S Int’l MicrowaveSymposium.

Author InformationInterested readers may contact-

the principal authors, LarryDunleavy at Modelithics, Inc., e-mail:ldunleavy@modelithics.com; or RayPengelly at Cree Microwave, Inc., e-mail: Ray_Pengelly@cree.com

Additonal information on LDMOSFET devices and the availability ofthe models described in this articlecan be obtained from either of thesecompanies:Cree Microwave, Inc.Sunnyvale, CA Tel: 408-962-7783www.creemicrowave.com

Modelithics, Inc.Tampa, FL Tel: (813) 866-6335 www.modelithics.com