Upload
others
View
2
Download
0
Embed Size (px)
Citation preview
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 1
July 19, 2005 J. A. Abraham 1
New Directions in Manufacturing Test
Jacob A. AbrahamComputer Engineering Research Center
The University of Texas at Austin
Shanghai Jiao Tong University
July 19, 2005
July 19, 2005 J. A. Abraham 2
Research Areas• Manufacturing test
– Dealing with faults in sub 100 nm circuits
– System-on-a-chip test issues• Design verification
– Formal approaches for property checking– Abstractions to deal with complexity
• Fault tolerance– Dealing with soft errors– Application-level techniques
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 2
July 19, 2005 J. A. Abraham 3
Outline• Manufacturing Test• Trends in Silicon defects• Hierarchy and abstractions to deal with test
generation complexity• Native-Mode Built-In Self-Test
– Application to testing processors– Test of A/D and D/A converters
• Testing of mixed-signal circuits• Future Directions
July 19, 2005 J. A. Abraham 4
Dealing with Faults
• Manufacturing faults, field failures: testing, design for testability• Design faults: simulation and emulation, formal techniques• Operational faults: concurrent error detection and fault tolerance
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 3
July 19, 2005 J. A. Abraham 5
Manufacturing Test• A speck of dust on a wafer is sufficient to
kill chip• Yield of any chip is < 100%
– Must test chips after manufacturing before delivery to customers to only ship good parts
• Manufacturing testers are very expensive– Minimize time on tester– Careful selection of
test vectors
July 19, 2005 J. A. Abraham 6
Test Generation
A test for a defect will produce an output response which is different fromthe output when there is no defectTest quality is high if the set of tests will detect a very high fraction of defectsDefect level is the percentage of bad parts shipped to customersYield is the percentage of defect-free chips manufactured
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 4
July 19, 2005 J. A. Abraham 7
Scan – Deal with Sequential Circuits• Convert each flip-flop to a scan register
– Only costs one extra multiplexer• Normal mode: flip-flops behave as usual• Scan mode: flip-flops behave
as shift register• Contents of flops
can be scannedout and new values scanned in
scan out
scan-in
inputs outputsLogicCloud
Flop
QD
CLK
SISCAN
July 19, 2005 J. A. Abraham 8
What About the Future• Are existing test solutions sufficient to deal
with the defects which may exist in emerging technologies?
• Look at some of the technology trends• Examine industry experience in new types of
defects and test problems
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 5
July 19, 2005 J. A. Abraham 9
IC Technology
July 19, 2005 J. A. Abraham 10
How Small Can It Get?
Polysilicon Gate
Gate Oxide
Silicon Channel
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 6
July 19, 2005 J. A. Abraham 11
Technology Trends
• Faster circuits• Decreasing Vt• Increasing leakage• Increasing parameter
variations
Source: Intel
1.0 0.8 0.6 .35 .25 .18
100
10
1
10-1
10-2
10-3
10-4
10-5
10-61.E-06
1.E-05
1.E-04
1.E-03
1.E-02
1.E-01
1.E+00
1.E+01
1.E+02
0 1 2 3 4 5 6 7
Active Power
Standby power (component Transistor
Leakage T=110C)
486DX CPU
Pentium Processor386
Pentium Pro Processor
R
R
Technology Generation (μm)
101
101
100
10-1
10-2
10-3
10-4
10-5
10-6
Pow
er
(W)
Effects exacerbatedby radiation
July 19, 2005 J. A. Abraham 12
Process Variations
Source: Intel
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 7
July 19, 2005 J. A. Abraham 13
Delay Effects of Crosstalk
0
2
1
Volts
Time
July 19, 2005 J. A. Abraham 14
Defects in Emerging Technologies• Resistive opens comprise the bulk of test
escapes in one production line– Likely in copper interconnect – cause delay faults
• Delay faults identified as the cause of most test escapes on another line– Speed differences of up to a factor of 1.5 can exist
between fast and slow devices - problems with “speed binning”
• Increasing possibility of shorts and crosstalk• Defects appearing as delays or soft failures
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 8
July 19, 2005 J. A. Abraham 15
Impact on Test• Existing Design for Test (DFT) structures are
geared to “stuck” faults– Not easy to apply two-pattern tests necessary to
check for path delays• Performance optimizations result in a large
number of paths close to the critical delay values
• Designs using statistical timing models would require the circuits to be also tested for paths close to the critical delay
July 19, 2005 J. A. Abraham 16
Static Timing Verification – Speed Paths
Use structure of circuit and delay to determine thelongest structural path in block (could be a false path)Only true paths on chip can be testedNeed access mechanisms to support at-speed test
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 9
July 19, 2005 J. A. Abraham 17
Scan Design and Delay Test
CircuitunderTest
Need two patterns for delay testShifting in second pattern changes state of the nodesSolutions: Scan Shifting or Last Shift Launch
Functional Justification or Broadside Test
July 19, 2005 J. A. Abraham 18
Tri-Scan Scheme
Based on state holding property of CMOS
tri
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 10
July 19, 2005 J. A. Abraham 19
Tri-Scan Schemescanenable
scan_in
scan_out
tristatebuffer
July 19, 2005 J. A. Abraham 20
Functional vs. Structural Test
P. Gelsinger, IEEE Design and Test, January 2000
Stuck-at Open Short ResistiveOpen
Leakage Resistiveshort
At-speed functional test Structural test
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 11
July 19, 2005 J. A. Abraham 21
Dealing With the Entire Design• Interest in chip-level (functional) tests• Delay tests generated at the block level may
be too conservative– “Long” paths at the block level may be false at the
next level• Problem of dealing with the entire design:
– Design with around 300 memory elements has more states than the number of protons in the universe!
July 19, 2005 J. A. Abraham 22
Dealing With the Entire Design• Experiments on benchmark processors
(target embedded module in processor)1. Tests for faults in module
under test (MUT) by itself 2. Tests for MUT faults when
embedded in processor
518241611992958893ARM-DP
991986763127016029ARM-2
FaultsPOsPIsSeq. Elems.Comb. Gates
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 12
July 19, 2005 J. A. Abraham 23
Test Generation on Module• Sequential ATPG can easily deal with a
module• Example: ARM-DP by itself• Results using commercial ATPG tool (on
HPUX-715, 125 MHz processor)– Fault Coverage: 99.70%– ATPG Efficiency: 99.93%– Test generation time: 33.1 seconds– Test length: 822 cycles
July 19, 2005 J. A. Abraham 24
Test Generation on Embedded Module• Sequential ATPG cannot deal with a module
when it is embedded in even a moderately complex design
• Results on ARM-DP when it isembedded in ARM-2– Fault Coverage: 17.66%– ATPG Efficiency: 17.66%– Test generation time: 316,199 seconds
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 13
July 19, 2005 J. A. Abraham 25
Abstraction to Deal With Complexity
July 19, 2005 J. A. Abraham 26
Test Generation Methodology
• Abstract HDL description (currently synthesizable Verilog) of environment, synthesize to gate level
• Commercial ATPG targeting faults in Module Under Test (MUT)
EM
• Program slicing for sound and complete abstraction
E’
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 14
July 19, 2005 J. A. Abraham 27
Key Theory• Lemma 1: Union of constraint slices provides
abstracted environment• Lemma 2: Process trace for signals defined in
a MUT preserved • Theorem 1: Valid set of patterns for the MUT
using constraint slices • Theorem 2: Hierarchical composition yields
the desired constraint slice
July 19, 2005 J. A. Abraham 28
Slicing Experiments• Automated into FACTOR (DATE 2002)• Verilog models of Viper and ARM-2
02000400060008000
1000012000140001600018000
# ga
tes
in e
nvir
onm
ent
VIPER_ALU ARM_ALU ARM_EXC
OriginalRaw SlicingHier. Slicing
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 15
July 19, 2005 J. A. Abraham 29
Test Coverage Improvement• 450 MHz dual UltraSPARC-II with 1 GB RAM• Commercial sequential ATPG tools used
0102030405060708090
100
Cov
erag
e (%
)
VIPER_ALU ARM_ALU ARM_EXC
OriginalRaw SlicingHier. Slicing
July 19, 2005 J. A. Abraham 30
Reduction in ATPG Time• Measured in system CPU seconds
02468
101214161820
Tim
e (s
)
VIPER_ALU ARM_ALU ARM_EXC
OriginalRaw SlicingHier. Slicing
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 16
July 19, 2005 J. A. Abraham 31
Native-Mode Built-In Self Test• Functional capabilities of processors can be
used to replace BIST hardware – (Shen and Abraham, ITC 1998)
• Application to self-test of processors at Intel –FRITS method applied to Pentium 4, Itanium (ITC 2002)
• Embedded processor can be used to test other modules in a System-on-a-Chip (research at Texas, Santa Barbara, San Diego)
• Extend approach to test embedded analog and mixed-signal modules
July 19, 2005 J. A. Abraham 32
Native-Mode Signature Compression
// S: general register or memory, holds signature
for each register Ri to be compressed {
Shift_Right_Through_Carry(Ri);
if (Carry) { S = XOR(S, feedback_polynomial) }
S = XOR(S, Ri);
}
D D D D
Cn Cn-1 Cn-2 C1
D1 . . .
1 2 3 n
Q1 D2 DnQ2 Qn
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 17
July 19, 2005 J. A. Abraham 33
Intel Functional BIST• Functional tests have good “collateral
coverage” for detecting unmodeled defects• Technique of Functional Random Instruction
Testing at Speed (FRITS) applied to Itanium processor family and Pentium 4 line– Parvathala et al., Int’l Test Conference, 2002
• Tests (kernels) are instruction sequences– Kernels loaded into cache and executed in real
time during test application– They generate and execute pseudo-random or
directed sequences of machine code
July 19, 2005 J. A. Abraham 34
FRITS Results• On Pentium 4, full chip-level coverage of
single-stuck faults was ≈ 70% with FRITS– Added 5% unique coverage to manually
generated tests• Helped reduce test “holes”
– Screen 10%–15% of chips which passed wafer sort/package tests by failed system tests
• Enables low cost testers– 40% increase in defect screening on structural
tester• Kernels execute 20 loops in ≈ 8 mSecs
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 18
July 19, 2005 J. A. Abraham 35
Automatic Mapping of Module Tests to Instruction Sequences
• Functional and directed random tests provide good fault coverage (95% – 96%) in high-performance microprocessors
• Need to develop tests for the remaining, hard-to-detect faults
• Able to generate tests for these faults at the module level
• Developing new techniques for mapping module-level tests to instruction sequences
July 19, 2005 J. A. Abraham 36
Change in Test Requirements• Analog and mixed-signal circuits need to be
tested for conformance with specifications• Delay tests (speed binning) for digital circuits
are also specification-based tests• Designing for process variations will require
sophisticated tests to screen for parts falling outside the acceptance limits
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 19
July 19, 2005 J. A. Abraham 37
On-Chip Delay MeasurementModified Vernier Delay Line
CLK CLK CLK
D D DQ Q Q
y
x
in OUT
mode
shiftclk
July 19, 2005 J. A. Abraham 38
Testing Mixed-Signal Circuits
SoCsSoCs
SoPsSoPs
MEMsMEMs OpticsOptics
RFRF
digitaldigital
MixedMixed--signalsignal
Have to deal with continuous signalsNeed to test for specifications
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 20
Alternate Tests: Key Idea
•• The mapping The mapping ffmsms is derived using regression is derived using regression (MARS)(MARS)
Source: Chatterjee
July 19, 2005 J. A. Abraham
Oscillation-Based Test
+-
+-+
-Vin
Test R4
R7
C2C1
R6
R5
R3
R2
R1
fosc
HPOLPOBPO
3dB Frequency
Pred
icte
d Va
lues
Actual Values
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 21
July 19, 2005 J. A. Abraham 41
Testing Cores in System
Processor
System Bus
Peripheral Bus
Source/Sink
Core 1Cache
Bridge
Core 2 Core 3TAI
Core 2
TAI
Core 3
Core 4TAI
Core 4
TAI
Core 1
Test accessmechanism
Source/Sink: Embedded ProcessorTest access mechanism: System/Peripheral BusTest Access Interface (TAI): Core test wrapper
Example random pattern generator:Xn = Xn-24 + Xn-55 (mod m)(Lagged Fibonacci sequence)
Primitive polynomial:X55 + X24 + 1
Period: 2(32-1)×(255 –1)
July 19, 2005 J. A. Abraham 42
DSP-Based BIST• Use Statistical Characteristic Equations (SCEs)• Statistical Parameters
– Good correlation between the inputs and the outputs– Physical or mathematical parameter
• Real faulty samples and ideal samples– Generated by fault injection on simulation models
Converters
IdealSamples
FaultySamples
Converters SCE
SCE
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 22
July 19, 2005 J. A. Abraham 43
BIST for Σ-Δ D/A – A/D Converters
DSP only deals with digital signals
Test point monitored by DSP
Input
DSPDSP
RegisterRegister Low-passFilter
Low-passFilter
Linearinterpolater
Linearinterpolater
DigitalDelta-Sigmamodulator
DigitalDelta-Sigmamodulator
AnalogLow-pass
Filter
AnalogLow-pass
Filter
AnalogLow-pass
Filter
AnalogLow-pass
Filter
AnalogDelta-Sigmamodulator
AnalogDelta-Sigmamodulator
DecimatorDecimatorLow-passFilter
Low-passFilter
Accumulateand
Dump
Accumulateand
Dump
Digital blockMixed blockAnalog blockDAC
ADC
Overall architecture
frequency
PSD Y(f)LB
Show DAC characteristics
Low pass filter
Frequency Response Y(f)LB
Show ADC characteristics
July 19, 2005 J. A. Abraham 44
Implementation
• Applied BIST technique to industry chip for wireless applications– Oversampling Δ-Σ converters– Analog loop-back– SNR measurement
New Directions in Manufacturing Test J. A. Abraham
July 19, 2005 23
July 19, 2005 J. A. Abraham 45
Results
DAC_measADC_measDAC_simADC_sim
Input dB
SNR
Model Accuracy:37.45 dB
DAC_measADC_measDAC_simADC_sim
Input dB
Model Accuracy:5.8 dB
SNR
Calibration
The setup for SNR measurement was a little noisy, but was used to get these preliminary results
Application: industry chip for wireless applicationsOversampled Σ-Δ converters, SNR measurement
July 19, 2005 J. A. Abraham 46
Ongoing Work in Test• New approaches for dealing with process
variations and sub-100 nm defects• Testability features for improved DSP-based
BIST• Applications to high-frequency designs (PLLs,
RF, etc)• Algorithms for mapping module-level tests to
instructions• Improved abstraction techniques to speed up
test for complex designs