New current conveyor for high-speed low-power current sensing

Y.K. Seng

Indexin;: terms: Current conveyor, SRAM, Circuit design and .simulution

Abstract: A novel low-voltage current conveyor for fast CMOS SRAM applications is presented. The sensing speed is independent of the bit-line capacitances and a positive feedback technique is employed to give the circuit a high-speed and low-power operation. Performance evaluation has shown that, based on equal area ratios, the new conveyor outperforms the conventional circuit in terms of speed and average power dissipation by at least 30'%. The static behaviour of the basic circuit is analysed, and HSPICE simulations have been used to characterise the circuits. Experimental results have verified the functionality of the new circuit and its superiority over the conventional CMOS current conveyor.

1 Introduction

As operating frequency increases, chip size grows big- ger and packing density reaches the ULSI (ultra large scale integration) level, power consumption becomes extremely important. As a result, low-voltage operation is inevitable for future ULSI applications [l-31. How- ever, reducing the supply voltage results in a serious problem in memory circuits because the time delay to sense the signals from the memory cells increases tre- mendously 141. Moreover, scaling the supply voltage reduces the readout voltage amplitude on the bit lines. Consequently, highly sensitive sense amplifiers are needed to detect these signals [4].

The memory capacities of SRAMs have roughly quadrupled every three years [5]. Each generation of CMOS SRAMs has advanced by reducing the memory cell size by about one-third and increasing the chip size by approximately 1.5 times 151. With the advances in integrated circuit technology, the density of SRAMs in embedded applications has grown substantially in recent years 161. This has resulted in an increase in both bit and data lines capacitances thereby constituting a major bottleneck in achieving higher sensing speed in memory systems.

The three most important parameters in a memory system are speed, power and area. In general, high

0 IEE, 1998 IEE Proceedings online no. 19981601 Paper received 10th January 1997 The author is with the School of Electrical and Electronic Engineering, S2-B2C-41, Nanyang Technological University, Nanyang Avenue, Singapore 639798

sensing speed is often achieved at the expense of an increase in both power consumption and silicon area: in other words a compromise. In this paper, a novel current conveyor which gives fast access time without sacrificing power dissipation and chip area is presented.

"dd h d

T I 1 0 6T cel l 1 1

BL 0 6T cell 1

---- Fi . I 0.8 m m o r y system

Proposed CMOS current conveyor and a sizrlplified reud-cycle-

2 Circuit description, operation, and experimental results

The proposed current conveyor together with a simpli- fied read-cycle-only memory system is shown in Fig. 1. It consists of nine PMOS (P3, P4, P5, P6, P7, P8, P9, P10 and P99) devices residing in a common n-well. The circuit topology resembles that of the conventional cur- rent conveyor, illustrated in Fig. 2, in which it has (ide- ally) zero input resistance during sensing. This property makes it insensitive to the bit-line capacitance. Unlike the conventional conveyor, the new circuit has the quality of transforming into a latch soon after differen-

8 5 IEE ProccCirmits Drvices Syst., Vol. 145, No. 2. April 1998

tial current signals appear at nodes A and B. This char- acteristic gives the new circuit high-speed, low-power operation. Transistors P1 and P2 are used to pull the bit lines close to the supply voltage to attain memory cell stability and soft-error immunity. They are biased in the triode region (grounded gate) and configured to operate at low supply voltages. Transistor P99 turns on only when there is no sensing. It forces the voltage at the sources of P9 and PlO to be equal. The bit and data lines capacitances are denoted CBL and CDL, respectively, and RS and CS are the row and column selectors, respectively. Fig. 1 also includes a conven- tional CMOS sense amplifier [7]. It comprises three current mirrors, namely (N3, N4), (N5, N6), and (P23, P24). Together with an output inverter, INV2, they detect, amplify and convert the differential signals at the data lines to a CMOS logic level output.

BL BL'

DL cs2 D L' Fig. 2 Conventional CMOS current conveyor

Consider both RS1 and CS2 lines being activated during a read cycle. Differential current signals then appear at the common bit lines. Since no differential capacitor discharging is required to sense the cell data, these signals propagate almost instantaneously to the current conveyor. Sufficient time delay is provided by inverter, INVl, to allow differential currents to appear at nodes A and B before turning off transistors P6 and P7. As soon as transistors P6 and P7 are off, the con- veyor transforms into a latch. Since the right-hand leg of the conveyor passes more current than the left-hand leg, the voltage at node B rises faster than that at node A. Owing to small capacitances at nodes A and B, the regenerative effect of the conveyor is very rapid. Because P3 turns off after the flip-flop action, there is only one bit line path that allows the current to flow through the conveyor. Consequently, a large differen- tial voltage is developed across the data lines, thereby enhancing the response speed of the sense amplifier. In addition, with only one branch of current flowing through the conveyor, the power consumption of the circuit is significantly reduced.

The new and conventional current conveyors were IC tested, to verify their functionality and performance, using integrated circuit HCF4007, a dual complemeii- tary pair with inverter, and a power supply voltage of 4.5V. In the experiment, only one memory cell and a column select were activated. No capacitance was con- nected to the bit and data lines due to the inherently large parasitic capacitance of integrated circuits. Dur- ing testing, the memory cell data was made to toggle at a frequency of 0.55MHz while the CS line was switched at a frequency of 1.2MHz. The sensing speeds of both circuits were measured from the time when CS was triggered (active low) to the time when there was a

86

valid output to be read. Fig. 3a shows the sensing delay of the conventional circuit. The access time was meas- ured to be 50.6ns. The same setup was used to test the proposed circuit. In order to ensure that correct differ- ential signals appear at nodes A and B before flip-flop action occurs, the inverter INVl in Fig. 1 was replaced with three inverters connected in series to provide the proper time delay. As shown in Fig. 36, an access time of 31.811s was measured, an improvement of about 37% over the conventional CMOS circuit.

a

b Fig. 3 Experimental ressuhfor the sensing delay a Conventional circuit (horizontal scale: 0.1 psidiv; vertical scale: 1 Vidiv) b New circuit (horizontal scale: 0. I pddiv; vertical scale: 1 Vidiv)

3 Analysis

In this Section, the differential small-signal input resist- ance of the new current conveyor looking into the sources of transistors P3 and P4 is derived. The analy- sis is based on the I-V relationships of submicron devices reported in [XI. Assuming all transistors operate in the saturation region, their drain currents can be expressed as [XI:

The device transconductance is given as: ISD kCoxWusat (VSG - VT) (1)

g m = kCoxWusat (2) where k is the short-channel effects factor in the satura- tion region [XI, Cox is the gate oxide capacitance, W is the channel width, V, is the threshold voltage, and usat is the saturation velocity. Eqn. 1 can be rearranged to give:

( 3 )

IEE Proc.-Circuiis Devices Sysi., Vol. 145, No 2, April 1998

In the static mode of operation, the gate voltage of transistors P6 and P7 are low (grounded). Let Is,(,,) and IsDiP4) be the drain currents flowing through devices P3 and P4, respectively. Suppose the channel widths of P3 and P4 are equal to the sum of the chan- nel widths of (P5, P6) and (P7, PZ), respectively, then the effective gate-source voltage of P3 and P4 can be written as:

VSG(P3) = VSG(P5,P6)

+ VT _. - ISD(P3)

Qm(P3)

- ISD(P3) -

Sm(P5) + Sm(P6)

VSG(P4) = VSG(P7,PS)

ISD(P4) + VT - -

Sm(P4)

- lSD(P4) -

gm(P7) + gm(P8)

As shown in Fig. 1, the voltage at the line bar are:

VBL VSG(P3) + YP7,PS)

+ - IS D (P 3) -

gm(P5) + gm(P6)

ISD (P4) + Qm(P7) + Qm(P8)

+ VT (4b)

bit line and bit

VT

f VT (54

VBLB = VSG(P4) + y P 5 , P 6 )

f VT ( 5 b ) ISD (P4) ISD(P3) +VT+- - - gm(P4) Qm(P3)

Hence, the result of the small-signal input resistance Ri, looking into the sources of P3 and P4 is:

where Agm = gm(P5) + gm(P6) + gm(P7). + grn(P8) - gm(P3) - g,(p4) and g , is the effective small-signal transconduct- ance of the MOS transistors [7]. Therefore in order to achieve a virtual short-circuit at the bit lines, g,(p5) +

can be shown that when P6 and P7 are off, R,, becomes negative. However, DC instability will not occur as long as R,, + 2 R, > 0, where R, is the bit line resistance. Therefore, the condition for flip-flop action to occur is:

[gm(PY) + ~ ( P Q ) ] - [ h ( P B ) + h ( ~ s ) ] > 2(&)’RB

where g’, is the effective small-signal transconductance of the new circuit when both transistors, P6 and P7, are off.

gm(P6) + gm(P7) + gm(P8) = gm(P3) i- gm(P4). From eqn. 6, it

(7 )

4 Simulation results and performance evaluation

Extensive circuit simulations, using the HSPICE BSIM model, have been carried out to verify the circuit oper- ation and characterise its perf-ormance. The simulation results are based on 200ps rise and fall times and two CMOS technologies, namely, 3.3VIO.5pm and 2.2Vl 0.35pn-1 with threshold voltage of about f 0.65V and

IEE Proc.-Circuits Devices Syst.. Vol. 145, No. 2, April 1998

f0.42V, respectively. Fig. 4 shows the key currents of the new and conventional conveyors at a supply volt- age of 2.2V. As shown in the Figure, once latching occurs, there is only one bit line path that allows the current to flow through the proposed circuit, thereby reducing the power dissipation. In Fig. .5, the voltages at the data lines of both circuits are illustrated. The new conveyor generates a large differential voltage at the data lines and as a result, its sensing speed is much faster than its conventional counterpart.

-1 00

- 2 0 0

-

-

a ? -300-

E 5 - 4 0 0 -

..- C

I ,I: I I I

25 30 35 40 1 5 time, ns

Key currents ojnew and conventional CMOS current conveyors Fig. 4 Vdd = 2.2V; C, = O.lpF; C,, = C,, = I p F

DL’ (conv) /’ !

! DL (conv) I

. . -. -. -. -. - . -. - .

i , . . . . , . . . . . . . . . . . . . . . . . . . . . . ..

I

2 5 30 35 1 0 45 time, ns

Voltages at data 1ine.Y of proposed and conveiitioital CMOS cur- Fig.5 rent conveyor.5’ Vdd = 2.2V; C, = 0.1 pF; C,, = C,, = I pF

Both the conventional and new current conveyors are simulated together with a simplified read-cycle-only memory system as shown in Fig. 1. They are compara- tively evaluated, based on the same area, in terms of the propagation delay and average power dissipation with different bit and data lines capacitances, power supply voltages and processes. The layout of both cir- cuits are shown in Figs. 6u and 6. Their active chip areas are 206pm2 and 2 0 2 p 2 , respectively. The lay- outs are drawn according to the Lambda design rules in [9, 101 and for a 0.35pn, single poly, double metal,

87

n-well p-substrate CMOS process. The aspect ratios of both circuits are shown in Table 1.

n nw

nwel l

contact

metal

Poly

PPlUS

I U U E4E DLE

a

d

I I b

Fig.6 LZ Conventional b New

Layout of CMOS currmt conveyory

The effect of bit lines capacitances on both propaga- tion delay and average power consumption for the 3 .3V lO.Spn and 2.2Vl0.3Spm technologies are shown in Figs. 7 and 8, respectively. Both circuits are insensi- tive to the bit lines capacitances, but the new circuit has a lower propagation delay (i.e. faster sensing speed). The average power dissipation, during a read operation, of the new circuit is also less than the con- ventional circuit. For example, at a load (C,) of 0.1 pF, at a frequency of SOMHz, and with C,, = C,, = lpF , the average power consumption of the new circuit is

59'Yo and 63 'YO lower than the conventional circuit for the 3.3VIO.5pn and 2.2VIO.35pm technologies, respec- tively.

Table 1: Aspect ratios of the new and conventional cur- rent conveyors for 2.2V10.35pm technology

~

Aspect ratios (W/L), pmipm

Conventional Proposed Device

P3 - 9/0.35

P4 - 9/0.35

P5 - 4.510.35

P6 - 4.510.35

P7 - 4.510.35

P8 - 4.510.35

P9 - 9/0.35

PI0 - 9/0.35

P I 1 18/0.35 - PI2 1810.35 -

PI3 1810.35 - PI4 1810.35 -

P99 - 1/0.35

m t

VI c .-

- W

t 0.11

0 . 2 1 il 01 I I I I I I I I I 0 0.5 1.0 1 5 20 2.5 3.0 3.5 L.0 L.5 5.0

bit Lines capacitance, p F Fig.7 capacitances for 3 3 V/O S p z technology CDL = 1 0 p F C, = 0 IpF

~ delay powei

Sennng delay and average power disspation against bit liner

~~~~

1.0r I

o.2 t 1' W

>

0 1 0 0

0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.0 1 .5 5.0 b i t l ines capacitance, pF

Fig.8 capacitances for 2.2 V0.35pz technology

~ delay

Sensing delay and average power dissipation against bit lines

C,, = 1.OpF; CL = O.lpF

power _ _ _ ~

IEE Proc.-Circuits Devices Syst., Vol 145. No. 2, April 1998 88

2.5r -!?

0.5 t 01 I I , I I 8 1 I I 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 L.0 1.5 5.0

data lines capacitance, pF Fig.9 cupucitunces for 3.3 V/OSpn iechnology

__ delay power

Sensing dehy und average power di.c.tipution against duta lincx

CBL = 1.OpF; CL = O.lpF

- - - -

0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 1.0 4.5 5.0

data Lines capacitance, pF Fig. IQ cupacitunces for 2.2 V 0 . 3 5 ~ technology CB, = l.OpF; CL = O.lpF __ delay - _ - _ power

Sensing delay und average power dissipation against data lines

The sensing delay with respect to the data lines capacitances for the 3.3V10.5pm and 2.2V10.35pn technologies are illustrated in Figs. 9 and 10, respec- tively. Unlike the conventional current conveyor, the sensing speed of the new circuit increases very gradu- ally with the data lines capacitance. Its sensing delay is also at least 30% lower than the conventional circuit. For example, for the 3.3ViO.5pm technology, C, = 0.1 pF and C,, = 1 pF, the data lines capacitance char- acteristics of the conventional and new circuits are 378psipF and 189ps/pF, respectively. Likewise, for the 2.2V10.35pm technology, the data lines capacitance

characteristics are 321 psIpF and 171 ps/pF, respec- tively. Hence, the proposed circuit is very suitable for use in high density SRAMs.

5 Conclusions

A new current conveyor for low-volta ge low-power environments is presented. It is based on the positive feedback technique and its access time is unaffected by bit lines capacitances. The static behaviour of the new circuit is analysed. The analysis not only provides greater physical insight into the circuit operation, but also relates key device parameters to the circuit per- formance. The condition for DC instability (latching behaviour) to occur is also stated. The superiority of the proposed circuit over the conventional conveyor has been confirmed by HSPICE simulations. Compara- tive evaluation shows that with the same chip area, the new circuit gives higher sensing speed and lower power consumption than the conventional circuit. The access time obtained from the experimental work also shows that the proposed conveyor is 37%) faster than its con- ventional counterpart.

6 Acknowledgment

The author is grateful to K.H. Eu for technical sup- port.

7 References

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