New-Analog and Digital Electronics Lab Manual_2013 (1)

8/10/2019 New-Analog and Digital Electronics Lab Manual_2013 (1)

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CS6211 Digital Laboratory

LIST OF EXPERIMENTS1. Verification of Boolean Theorems using basic gates.

2. Design and implementation of combinational circuits using basic gates for arbitrary functions,code converters.

3. Design and implementation of combinational circuits using M! devices"

# $ bit binary adder % subtractor

&arity generator % chec'er

Magnitude (omparator

)pplication using multiple*ers

#. Design and implementation of se+uential circuits"

hift $registers

ynchronous and asynchronous counters. (oding combinational % se+uential circuits using -D.

/. Design and implementation of a simple digital system 0Mini &roect.

LIST OF EXPERIMENT (CYCLE I)

1. Study of logic gates.

2. Design and implementation of Code Converters using logic gates.

3. Design and implementation of 4-bit binary Adder/Subtractor and CD adder

using !C "4#3.

4. Design and implementation of $ultiple%er and De-multiple%er using logicgates.

&. Design and implementation of 'ncoder and Decoder using logic gates.

(. Construction and veri)cation of 4-bit *ipple Counter and $od-1+/$od-12

ripple counter.

". Design and implementation of 3-bit Sync,ronous up/don counter.

#. !mplementation of S!S S!0 0!S and 0!0 s,ift registers using ip-ops.

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EXPT NO.

D!TE DESI"N !ND IMPLEMENT!TION OF CODE CON#ERTOR

!IM

o design and implement 4-bit

i inary to 5ray code converter

ii 5ray to inary code converter

iii CD to '%cess-3 code converter

iv '%cess-3 to CD code converter

!PP!R!T$S RE%$IRED

Sl.6o. C$06'6 S0'C!7!CA!6 891. :-* 5A' !C "4#( 12. A6D 5A' !C "4+# 13. * 5A' !C "432 14. 6 5A' !C "4+4 1&. !C *A!6'* ;! - 1(. 0AC< C*DS - AS

*'8=!*'D

T&EORY,e availability of large variety of codes for t,e same discrete elements of

information results in t,e use of di>erent codes by di>erent systems. A

conversion circuit must be inserted beteen t,e to systems if eac, uses

di>erent codes for same information. ,us code converter is a circuit t,at ma?es

t,e to systems compatible even t,oug, eac, uses di>erent binary code.

,e bit combination assigned to binary code to gray code. Since eac, code

uses four bits to represent a decimal digit. ,ere are four inputs and four outputs.

5ray code is a non-eig,ted code.

,e input variable are designated as 3 2 1 + and t,e output

variables are designated as C3 C2 C1 Co. from t,e trut, table combinational

circuit is designed. ,e oolean functions are obtained from ;-$ap for eac,

output variable.

A code converter is a circuit t,at ma?es t,e to systems compatible even

t,oug, eac, uses a di>erent binary code. o convert from binary code to '%cess-

3 code t,e input lines must supply t,e bit combination of elements as speci)ed

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Ma* 3or "/

"/4 '/Ma* 3or "2

Ma* 3or "1

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Ma* 3or "0

LO"IC DI!"R!M

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"R!Y CODE TO 'IN!RY CON#ERTOR

TR$T& T!'LE

"ray Co- 'iary Co-

"/ "2 "1 "0 '/ '2 '1 '0

000000001

11

000011111

11

001111000

01

011001100

11

000000001

11

000011110

00

001100110

01

010101010

10

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/


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11111

10000

11100

00110

11111

01111

10011

10101

Ma* 3or '/

'/ 4 "/

Ma* 3or '2

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Ma* 3or '1

Ma* 3or '0

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LO"IC DI!"R!M

'CD TO EXCESS/ CON#ERTOR

TR$T& T!'LE 'CD i*+t E5, 7 / o+t*+t

'/ '2 '1 '0 E/ E2 E1 E0

000000001111

000011110000

001100110011

010101010101

000001111155

011110000155

100110011055

101010101055

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1111

1111

0011

0101

5555

5555

5555

5555

Ma* 3or E/

E/ 4 '/ 8 '2 ('0 8 '1)

Ma* 3or E2

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Ma* 3or E1

Ma* 3or E0

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LO"IC DI!"R!M

EXCESS/ TO 'CD CON#ERTOR

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TR$T& T!'LE

E5, 7 / I*+t 'CD O+t*+t

X9 X/ X2 X1 ! ' C D

0000011111

0111100001

1001100110

1010101010

0000000011

0000111100

0011001100

0101010101

Ma* 3or !

! 4 X1 X2 8 X/ X9 X1

Ma* 3or '

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Ma* 3or C

Ma* 3or D

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LO"IC DI!"R!M

PROCED$RE

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i Connections ere given as per circuit diagram.

ii ogical inputs ere given as per trut, table

iii bserve t,e logical output and verify it, t,e trut, tables.

RES$LT

EXPT NO.

D!TEDESI"N OF 9'IT !DDER !ND S$'TR!CTOR

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,e output of to decimal digits must be represented in CD and s,ould appear

in t,e form listed in t,e columns.

A CD adder t,at adds 2 CD digits and produce a sum digit in CD. ,e 2

decimal digits toget,er it, t,e input carry are )rst added in t,e top 4 bit adderto produce t,e binary sum.

PIN DI!"R!M FOR IC ;9


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LO"IC DI!"R!M

9'IT 'IN!RY !DDER

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LO"IC DI!"R!M

9'IT 'IN!RY S$'TR!CTOR

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LO"IC DI!"R!M

9'IT 'IN!RY !DDER:S$'TR!CTOR

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TR$T& T!'LE

LO"IC DI!"R!M'CD !DDER

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I*+t Data ! I*+t Data ' !--itio S+btra,tio

!

9

!

/

!

2

!

1

'

9

'

/

'

2

'

1

C S

9

S

/

S

2

S

1

' D

9

D

/

D

2

D

1

1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0

1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0

0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0

0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0

1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1

1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1

1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

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M!PY 4 S9 (S/ 8 S2)

TR$T& T!'LE

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'CD S$M C!RRY S9 S/ S2 S1 Y 0 0 0 0 00 0 0 1 00 0 1 0 0

0 0 1 1 00 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 01 0 0 0 01 0 0 1 01 0 1 0 11 0 1 1 11 1 0 0 1

1 1 0 1 11 1 1 0 11 1 1 1 1

PROCED$RE

i Connections ere given as per circuit diagram.

ii ogical inputs ere given as per trut, table

iii bserve t,e logical output and verify it, t,e trut, tables.

RES$LT

EXPT NO.

D!TE

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DESI"N !ND IMPLEMENT!TION OF M$LTIPLEXER !ND DEM$LTIPLEXER

!IM

o design and implement multiple%er and demultiple%er using logic gates.

!PP!R!T$S RE%$IRED

Sl.6o. C$06'6 S0'C!7!CA!6 89.1. 3 !/0 A6D 5A' !C "411 22. * 5A' !C "432 13. 6 5A' !C "4+4 12. !C *A!6'* ;! - 13. 0AC< C*DS - AS

*'8=

!*'D

T&EORY

M$LTIPLEXER

$ultiple%er means transmitting a large number of information units over a

smaller number of c,annels or lines. A digital multiple%er is a combinational

circuit t,at selects binary information from one of many input lines and directs it

to a single output line. ,e selection of a particular input line is controlled by a

set of selection lines. 6ormally t,ere are 2ninput line and n selection lines ,ose

bit combination determine ,ic, input is selected.

DEM$LTIPLEXER

,e function of Demultiple%er is in contrast to multiple%er function. !t ta?es

information from one line and distributes it to a given number of output lines. 7or

t,is reason t,e demultiple%er is also ?non as a data distributor. Decoder can

also be used as demultiple%er.

!n t,e 1H 4 demultiple%er circuit t,e data input line goes to all of t,e A6D

gates. ,e data select lines enable only one gate at a time and t,e data on t,e

data input line ill pass t,roug, t,e selected gate to t,e associated data output

line.

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'LOC DI!"R!M FOR 91 M$LTIPLEXER

F$NCTION T!'LE

S1 S0 INP$TS Y 0 0 D0 = D0 S1> S0>0 1 D1 = D1 S1> S01 0 D2 = D2 S1 S0>1 1 D/ = D/ S1 S0

Y 4 D0 S1> S0> 8 D1 S1> S0 8 D2 S1 S0> 8 D/ S1 S0

CIRC$IT DI!"R!M FOR M$LTIPLEXER

TR$T& T!'LE

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S1 S0 Y 4 O$TP$T0 0 D00 1 D11 0 D21 1 D/

'LOC DI!"R!M FOR 19 DEM$LTIPLEXER

F$NCTION T!'LE

S1 S0 INP$T0 0 X = D0 4 X S1>

S0>0 1 X = D1 4 X S1> S01 0 X = D2 4 X S1 S0>1 1 X = D/ 4 X S1 S0

Y 4 X S1> S0> 8 X S1> S0 8 X S1 S0> 8 X S1 S0

LO"IC DI!"R!M FOR DEM$LTIPLEXER

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TR$T& T!'LE

INP$T O$TP$TS1 S0 I:P D0 D1 D2 D/0 0 0 0 0 0 00 0 1 1 0 0 00 1 0 0 0 0 00 1 1 0 1 0 01 0 0 0 0 0 01 0 1 0 0 1 01 1 0 0 0 0 01 1 1 0 0 0 1

PROCED$RE

i Connections are given as per circuit diagram.

ii ogical inputs are given as per circuit diagram.

iii bserve t,e output and verify t,e trut, table.

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RES$LT

EXPT NO.

D!TECONSTR$CTION !ND #ERIFIC!TION OF 9 'IT RIPPLE CO$NTER !ND MOD

10:MOD 12 RIPPLE CO$NTER

!IM

o design and verify 4 bit ripple counter mod 1+/ mod 12 ripple counter.

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!PP!R!T$S RE%$IRED

Sl.6o. C$06'6 S0'C!7!CA!6 89.

1. I; 7!0 70 !C "4"( 22. 6A6D 5A' !C "4++ 13. !C *A!6'* ;! - 14. 0AC< C*DS - AS

*'8=!*'D

T&EORY

A counter is a register capable of counting number of cloc? pulse arriving atits cloc? input. Counter represents t,e number of cloc? pulses arrived. A speci)ed

seuence of states appears as counter output. ,is is t,e main di>erence

beteen a register and a counter. ,ere are to types of counter sync,ronous

and async,ronous. !n sync,ronous common cloc? is given to all ip op and in

async,ronous )rst ip op is cloc?ed by e%ternal pulse and t,en eac, successive

ip op is cloc?ed by 8 or 8 output of previous stage. A soon t,e cloc? of second

stage is triggered by output of )rst stage. ecause of in,erent propagation delaytime all ip ops are not activated at same time ,ic, results in async,ronous

operation.

PIN DI!"R!M FOR IC ;9;6

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LO"IC DI!"R!M FOR 9 'IT RIPPLE CO$NTER

TR$T& T!'LE

CL %! %' %C %D0 0 0 0 0

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1 1 0 0 02 0 1 0 0/ 1 1 0 09 0 0 1 0? 1 0 1 0

6 0 1 1 0; 1 1 1 0< 0 0 0 1@ 1 0 0 1

10 0 1 0 111 1 1 0 112 0 0 1 11/ 1 0 1 119 0 1 1 11? 1 1 1 1

LO"IC DI!"R!M FOR MOD 10 RIPPLE CO$NTER

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TR$T& T!'LE

CL %! %' %C %D0 0 0 0 01 1 0 0 02 0 1 0 0/ 1 1 0 09 0 0 1 0? 1 0 1 0

6 0 1 1 0; 1 1 1 0< 0 0 0 1@ 1 0 0 1

10 0 0 0 0

LO"IC DI!"R!M FOR MOD 12 RIPPLE CO$NTER

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TR$T& T!'LE

CL %! %' %C %D0 0 0 0 01 1 0 0 02 0 1 0 0/ 1 1 0 09 0 0 1 0? 1 0 1 06 0 1 1 0; 1 1 1 0< 0 0 0 1@ 1 0 0 1

10 0 1 0 111 1 1 0 112 0 0 0 0

PROCED$RE




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RES$LT

EXPT NO.

D!TE

DESI"N !ND IMPLEMENT!TION OF / 'IT SYNC&RONO$S $P:DOANCO$NTER

!IM

o design and implement 3 bit sync,ronous up/don counter.

!PP!R!T$S RE%$IRED

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Sl.6o. C$06'6 S0'C!7!CA!6 89.1. I; 7!0 70 !C "4"( 22. 3 !/0 A6D 5A' !C "411 13. * 5A' !C "432 14. :* 5A' !C "4#( 1&. 6 5A' !C "4+4 1(. !C *A!6'* ;! - 1". 0AC< C*DS - AS

*'8=!*'D

T&EORY

A counter is a register capable of counting number of cloc? pulse arriving at

its cloc? input. Counter represents t,e number of cloc? pulses arrived. An

up/don counter is one t,at is capable of progressing in increasing order or

decreasing order t,roug, a certain seuence. An up/don counter is also called

bidirectional counter. =sually up/don operation of t,e counter is controlled by

up/don signal. E,en t,is signal is ,ig, counter goes t,roug, up seuence and

,en up/don signal is lo counter follos reverse seuence.

M!P

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ST!TE DI!"R!M

C&!R!CTERISTICS T!'LE

%

%t81 B

0 0 0 X0 1 1 X1 0 X 1

1 1 X 0

LO"IC DI!"R!M

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TR$T& T!'LE

I*+t

$*:Do

Prt

Stat

%! %' %C

N5t Stat

%!81 %'81 %C81

!

B! !

'

B' '

C

BC C

0 0 0

0

1 1

1

1 X 1 X 1 X

0 1 11

1 10

X 0 X 0 X 1

0 1 1

0

1 0

1

X 0 X 1 1 X

0 1 0

1

1 0

0

X 0 0 X X 1

0 1 0

0

0 1

1

X 1 1 X 1 X

0 0 1

1

0 1

0

0 X X 0 X 1

0 0 10

0 01

0 X X 1 1 X

0 0 0

1

0 0

0

0

X

0 X X 1

1 0 0

0

0 0

1

0 X 0 X 1 X

1 0 0

1

0 1

0

0 X 1 X X 1

1 0 1

0

0 1

1

0 X X 0 1 X

1 0 1 1 0 1 X X 1 X 1

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1 01 1 0

0

1 0

1

X 0 0 X 1 X

1 1 0

1

1 1

0

X 0 1 X X 1

1 1 1

0

1 1

1

X 0 X 0 1 X

1 1 1

1

0 0

0

X 1 X 1 X 1

PROCED$RE




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RES$LT

EXPT NO.

D!TE

DESI"N !ND IMPLEMENT!TION OF S&IFT RE"ISTER

!IM

o design and implement

i Serial in serial out

ii Serial in parallel out

iii 0arallel in serial out

iv 0arallel in parallel out

!PP!R!T$S RE%$IRED

Sl.6o. C$06'6 S0'C!7!CA!6 89.1. D 7!0 70 !C "4"4 22. * 5A' !C "432 13. !C *A!6'* ;! - 14. 0AC< C*DS - AS *'8=!*'D

T&EORY

A register is capable of s,ifting its binary information in one or bot,

directions is ?non as s,ift register. ,e logical con)guration of s,ift register

consist of a D-7lip op cascaded it, output of one ip op connected to input of

ne%t ip op. All ip ops receive common cloc? pulses ,ic, causes t,e s,ift in

t,e output of t,e ip op. ,e simplest possible s,ift register is one t,at uses

only ip op. ,e output of a given ip op is connected to t,e input of ne%t ip

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op of t,e register. 'ac, cloc? pulse s,ifts t,e content of register one bit position

to rig,t.

PIN DI!"R!M

LO"IC DI!"R!M

SERI!L IN SERI!L O$T

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TR$T& T!'LE

CL

Srial i Srial o+t

1 1 02 0 0

/ 0 0

9 1 1

? X 0

6 X 0

; X 1LO"IC DI!"R!M

SERI!L IN P!R!LLEL O$T

TR$T& T!'LE

CL D!T!

O$TP$T

%! %' %C %D

1 1 1 0 0 0

2 0 0 1 0 0

/ 0 0 0 1 1

9 1 1 0 0 1

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LO"IC DI!"R!M

P!R!LLEL IN SERI!L O$T

TR$T& T!'LE

CL %/ %2 %1 %0 O:P0 1 0 0 1 11 0 0 0 0 02 0 0 0 0 0/ 0 0 0 0 1

LO"IC DI!"R!M

P!R!LLEL IN P!R!LLEL O$T

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TR$T& T!'LE

CL

D!T! INP$T O$TP$TD! D' DC DD %! %' %C %D

1 1 0 0 1 1 0 0 12 1 0 1 0 1 0 1 0

PROCED$RE




CS6211 DIGITAL LAB

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RES$LT

Documents

New-Analog and Digital Electronics Lab Manual_2013 (1)