netX50 Technical Data Reference Guide - hilscher.com€¦ · netX50 Technical Data Reference Guide Functional Overview • 8 Hilscher Gesellschaft für Systemautomation mbH – Rheinstr

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Technical Data Reference Guide netX 50

next Generation of Communication Controllers

Language: English

netX50 Technical Data Reference Guide • 2

Hilscher Gesellschaft für Systemautomation mbH – Rheinstr. 15 – D 65795 Hattersheim Edition 1.2 – Technical Data Reference Guide:netX50#EN – 2008/11

TECHNICAL DATA REFERENCE GUIDE 1

1 INTRODUCTION 5

2 FUNCTIONAL OVERVIEW 7 2.1 CPU 7 2.2 Oscillator 7 2.3 System LED and Boot Options 8 2.4 Extended System Information 9 2.5 Reset 10 2.6 Reset Configuration 11 2.7 Watchdog 12

2.7.1 WDGACT Signal 12 2.8 Internal Memory 13 2.9 External Memory 13

2.9.1 SRAM / FLASH Interface 13 2.9.2 SDRAM Interface 24

2.10 Extension Bus 28 2.10.1 Extension Bus Configuration 28 2.10.2 Extension Bus Address Space and netX Memory Allocation 28 2.10.3 Address and Data Byte Steering 29 2.10.4 Intel / Motorola Data Format 29 2.10.5 Multiplexed / Non-Multiplexed Data Bus 29 2.10.6 Data Ready or Data Acknowledge 29 2.10.7 End-Of-Cycle 30 2.10.8 Pin Description Of Extension Bus 30 2.10.9 Extension Bus Component Connection 32 2.10.10 Extension Bus Timing without Wait-states 34 2.10.11 Extension Bus Timing with Wait-states 35

2.11 Dual-Port memory 36 2.11.1 Dual-Port Memory Interface Mode 36 2.11.2 Dual-Port Memory Structure and Allocation 37 2.11.3 Global Control Block 38 2.11.4 Data Memory Area / Data Memory Blocks 41 2.11.5 Handshake Registers 42 2.11.6 Dual-Port Memory Interface Configuration 44 2.11.7 DPM interface signals 44 2.11.8 Interrupts and Interrupt Signal 45 2.11.9 Data Ready Signal 46 2.11.10 Dual-Port Memory circuits 48

2.12 Timer 50 2.13 IEEE 1588 System Time 51 2.14 JTAG Debug Interface 52

2.14.1 Standard JTAG connector 52 2.14.2 Hilscher “mini-JTAG” Connector 53 2.14.3 Boundary Scan mode 54 2.14.4 Embedded Trace Macrocell ETM 55

2.15 Vectored Interrupt Controller 56 2.15.1 Interrupt generation 58 2.15.2 Interrupt priority logic 59 2.15.3 Interrupt flow sequence 59

2.16 DMA Controller 60 2.16.1 Functional Description 61

2.17 Multiplex Matrix 64



2.18 IO-Link Controller 66 2.18.1 Introduction 66 2.18.2 Typical Application 67 2.18.3 Functional Description 68 2.18.4 IO-Link datagram 70

2.19 CCD-Sensor Interface 72 2.19.1 Functional Description 73

2.20 UART 78 2.21 USB 81 2.22 I2C Interface 82

2.22.1 Overview 82 2.22.2 Functional Description 83

2.23 SPI 87 2.23.1 Overview 87 2.23.2 Functional description 88 2.23.3 Typical Applications 90

2.24 GPIO 92 2.25 PIO 93 2.26 Ethernet Interface 96

2.26.1 Real Time Ethernet 98 2.27 Fieldbus Interface 100

2.27.1 AS interface Master 101 2.27.2 CANopen Interface 102 2.27.3 CC-Link Interface 103 2.27.4 DeviceNet Interface 104 2.27.5 PROFIBUS Interface 105

3 ELECTRICAL SPECIFICATIONS 106 3.1 Absolute Maximum Ratings 106 3.2 Power Up Sequencing 107 3.3 Power Consumption / Power Dissipation 109 3.4 AC / DC Specifications 111

3.4.1 DC Parameters 111 3.4.2 System Oscillator / PLL 114 3.4.3 Power On Reset / Reset Input 115 3.4.4 MMIOs 116 3.4.5 USB 125 3.4.6 PHY 126 3.4.7 SDRAM 127 3.4.8 SRAM / FLASH 132 3.4.9 SPI 134 3.4.10 I2C 140 3.4.11 UART 141 3.4.12 Dual-port memory 142 3.4.13 JTAG 144

3.5 Failure Rate (FIT) 145 4 PACKAGE AND SIGNAL INFORMATION 146 4.1 Thermal Package Specification 146 4.2 Soldering Conditions 147

4.2.1 Infrared Reflow Soldering Characterization 147 4.2.2 Vapour Phase Reflow Soldering (VPS) Characterization 148

4.3 General storage conditions 148 4.4 Signal Definitions 149

4.4.1 Schematic View of netX Pad Types: 154 4.5 Multiplex Matrix Signals 155

netX50 Technical Data Reference Guide Introduction • 4


4.6 Pin Table Sorted By Pin Numbers 158 4.7 Pin Table Sorted By Signals 160 4.8 Pin overview 162

4.8.1 Overview 1 (unmarked) 162 4.8.2 Overview 2 (digital power pins marked) 163

4.9 Mechanical Dimensions / Physical Dimensions 164 4.10 Material composition 165

4.10.1 Solder balls 165 4.11 Ordering Information 165 5 PRINTED CIRCUIT BOARD DESIGN 166 5.1 Routing hints 167 5.2 Vcc Pin Requirements / Decoupling Capacitors 167 6 REFERENCE PCB LAYOUT DESIGN 167

7 REFERENCE SCHEMATICS 168

8 REVISION HISTORY 169

9 CONTACTS 170



1 Introduction

Product Features

• Powerful 200 MIPS ARM 966 CPU • ARMv5TE technology with enhanced DSP capability • Internal data switch between master and slave data resources to avoid bottle necks • 2 10/100MBit/s Ethernet Channels with integrated PHYs • Time stamping and synchronization according to IEEE 1588 • Special Hardware Support for Real-time Ethernet Features • Supports Real-time Ethernet Protocols EtherCAT, Ethernet/IP, Powerlink, PROFINET, SERCOS-III • Fieldbus Controller for AS interface, CAN, CC-Link, PROFIBUS • Integrated IO-Link Master Controller with eight channels • Integrated CCD-Sensor Controller • 96 KByte internal RAM for small applications without external memory components • 64 KByte ROM • SDRAM controller for large memory • SRAM and FLASH interface without glue logic • 32Bit Dual port memory interface for easy interface to host controller • Extension bus to add peripherals for stand alone applications • USB interface, runs as host or device, eight pipes • 3 UARTs, 16550 compatible • SPI with separate input and output-fifos, fully interrupt driven • I2C Interface • Watchdog with active signal for safety purposes • JTAG Debug Interface • ARM Embedded Trace Macrocell for real time tracing • Small BGA package • Extended temperature range • Guaranteed 10 years life time • Boot option via parallel or serial FLASH, serial EEPROM, MMC, Dual-Port Memory or UART • Software support for protocol stacks • Debug and Development Environment with standard ARM Tools support by HITEX and other Third

Party Companies

Typical Applications

• Communication Interfaces for PLC, Drives, HMIs and all types of Sensors or Actuators • Standalone Application for I/Os, Identification Devices or Gateways



RS232 USBser. FLASHIOs

SDRAM / SRAM / FLASH Host CPU / Peripherial Debug

2x Ethernet or 2x Fieldbus

DataSwitch

DPM

ARM 966

8/8 KB TCM Data/Instruction

ETM

ExtensionBus

MemoryController

32 KB SRAMTimerIRQ

IEEE 1588Sys Time

3x UART USBSPII2CPIO

JTAGController

xPEC

PHY

xMAC

xPEC

PHY

xMAC

32 KB SRAM

32 KB SRAM

64 KB ROM

DMA

Multiplexer 40 IO-Lines

Peripherial

CCDInterface

IO LinkGPIO

The netX50 is a member of Hilscher’s family of highly integrated network controllers with a new system architecture optimized for communication and maximum data throughput. Connected through its integrated dual-port memory with up to 32 Bit bus width, the netX50 can be used as a companion chip to virtually any host CPU and provides the complete scope of industrial communi-cation from fieldbus systems up to the Real-Time Ethernet systems. In applications without an external host CPU, the host interface can be configured as Extension Bus or used as digital inputs and outputs. The integrated ARM 966E-S 32-Bit CPU is clocked with 200 MHz and provides a total of 108 KB inter-nal RAM (including 8KB instruction TCM and 8 KB data TCM) and 64 KByte ROM. Memory can be expanded flexibly by use of the 32-Bit memory controller allowing the connection of external SDRAM, SRAM or FLASH. Extensive periphal functions, serial interfaces, such as UART, USB, SPI, I²C, as well as the integrated IO-Link and CCD controller allow a large scope of applications. The central data switch and the free configurable communication channels with their own intelligence are the unique selling proposition of the netX as a “high end” network controller. The data switch provides five data paths, connecting the ARM CPU, the communication, Host and DMA controllers with the memory or the peripheral units. This allows all controllers to transmit their data in parallel, contrary to the traditional sequential architecture with only one common data bus and additional bus allocation cycles. The identical set of controllers of the two communication channels are structured on two levels. They consist of dedicated ALUs and special logic units that receive their protocol functions via Microcode. For Ethernet the PHYs are integrated which means that the external circuit for Ethernet is reduced to pas-sive componets: transformer and RC components. The Medium-Access-Controller xMAC sends or receives the data according to the respective bus ac-cess process and encrypts or converts these into Byte depictions. The Protocol Execution Controller xPEC compiles these into data packets and controls the telegram traffic. Large data amoutns are exchanged in DMA blocks over the memory of the ARM. In addition, every channel has a Dual-port-memory available for status information. Alternatively a triple buffer logic is implemented for a conflict free data exchange which always gives the address of the next free buffer. With the intelligent communication ALUs, the netX carries out the most varied protocols and protocol combinations on one chip – an absolutely new feature in industrial communication technology.

Blockdiagram netX 50

netX50 Technical Data Reference Guide Functional Overview • 7


2 Functional Overview The following chapters provide an overview of the Key Function Units within the netX 50.

2.1 CPU

The netX 50 is equipped with an ARM966E-S processor core, implementing the ARMv5TE instruction set and providing a flexible memory system and DSP Instruction Set Extensions. The CPU runs on a 200 MHz system clock and has one 8 Kbyte block of Instruction-TCM and one 8 Kbyte block of Data-TCM (TCM = tightly coupled memory with zero wait states).

2.2 Oscillator

All internal clock signals of the netX are generated by a PLL which is driven from an internal oscillator that requires an external 25 MHz crystal. Alternatively, an external oscillator can be used. In this case the clock signal has to be connected to OSC_XTI, while OSC_XTO is left unconnected. Oscillator schematic for the 25 MHz clock

netX

OSC-XTOOSC-XTI

25 MHz

22 pF22 pF

OSC-VDDCOSC-VDDIO

1.5V3.3V

OSC-VSS GND



2.3 System LED and Boot Options

The general status of a netX based system is displayed by the System LED(s). It is recommended to use a dual LED here, but two single LEDs can also be used. The general definition of this LED is RDY yellow the netX with operating system is running RUN green the user application is running without errors However, after booting a firmware, the LEDs are firmware controlled and their behavior is hence com-pletely application- or firmware specific. The RDY and RUN signals are also used as inputs after a reset to select the boot mode. Applying cer-tain logic levels to these pins during and shortly after reset, results in a pre-selection of the several available boot options and hence determines, where the ROM boot loader looks for executable program code. Further, these pins are used to connect a secure EEPROM to the netX50, containing licenses and other application specific information like MAC addresses or SDRAM parameter as well as the de-sired bootmode. In applications, where no secure EEPROM is connected, the desired boot mode is selected according to the following schematic:



In applications, where a secure EEPROM is used (mandatory for master applications), the desired boot mode is selected by a parameter, stored in the EEPROM. In that case, boot jumpers can’t be used, as the EPPROM will not be accessed unless a high level is applied to both pins, RDY and RUN. The use of a boot mode button, forcing the serial boot mode, is however possible and recommended. The following schematic shows the proper circuit for attaching the SYS LED, a boot mode button and a secure EEPROM to the netX50:

2.4 Extended System Information The two LEDs 'RDY' and 'RUN' described in chapter 'System LED and Boot Options' are controlled by the netX via a special system status register, containing information about the system status of the netX. The NETX_STA_CODE is set by the netX boot software or firmware. The definition of each status bit and status code is software specific. Also, there are some flags which can only be controlled by an external host system. When a write access to the status flags is performed by the netX, an interrupt request can be generated, to notify the host about the changes. For a detailed description of the register bits see the 'netX50 Program Reference Guide' and chapter 2.11.3.3 (System Status) of this document.



2.5 Reset

The netX offers nine reset sources which can generate a system reset of the chip. Two of them are external inputs, while the others are generated by different internal function blocks. PORn Power on reset, input pin (Schmitt trigger)

This (active low) signal shall be connected to the output of a voltage supervi-sor chip, which checks the power supply voltages and pulls the power on reset pin low, whenever the voltages are below the minimum specified netX system operating voltages. The power on reset signal causes an asynchro-nous reset of the netX chip and initializes all internal registers and signals to their power on reset state. Reset timing is specified in chapter 3.4.3.

RSTINn External reset input pin (Schmitt trigger)

This is the second reset input signal (active low) from an external reset source e.g. from the host system. Unlike the PORn, this is a synchronous reset and is an optional signal. When not used, this signal may be left unconnected, since the pin is equipped with an internal pull-up resistor (nom. 50k).

WDG_RES If the internal watchdog counter expires, this reset is generated. It is also pos-

sible to generate an interrupt before the watchdog resets the chip. For more details see chapter 2.7 (netX system watchdog).

HOST_RES This reset is initiated by the host system interface by writing a special se-

quence into a host interface register. The reset will occur 1 ms after starting the write cycle allowing the host to finish the access and prepare for the netX chip reset.

FIRMW_RES This reset can be activated by a software command. XPEC0_RES This reset is generated by xPEC of communication channel 0. XPEC1_RES This reset is generated by xPEC of communication channel 1. The following figure shows an overview of the netX50 reset circuit block.



Block diagram of the Reset Controller There is also one output signal to reset external connected peripherals: RSTOUTn This is an output signal to reset connected peripheral devices. It is a tri-state-able

signal that can be enabled and set to high or low level by a software command. Any Reset, regardless if Power On, Reset In or internal reset, will disable the output driver of the signal, allowing to set the desired reset default level to low or high by either using a pull-down or pull-up resistor.

A power on reset is the only reset condition that will clear the value of the RESET_CTRL register. All other reset requests are stored in the RESET_CTRL register. This information can be used by the Firmware to determine which reset source has activated the last reset signal and act accordingly (e.g. not restart the system after a Watchdog initiated reset). Additionally the RESET_CTRL register provides four bits that can be used to save information, unaf-fected by any reset, except the Power on reset. The firmware can disable the internal system reset signals to the XPEC modules, allowing these mod-ules to continue to run even while the chip is performing a reset.

2.6 Reset Configuration

With the rising edge of the last active power on reset signal (PORn or RSTINn), the levels of I/O pins PIO[85:32] are stored in the corresponding Host interface registers. It is possible to read these values for hardware controlled power on configuration. For details see the register description of the host input / output port control and chapter 2.25 (PIO, Power-On-Reset Sampling of PIO 32-85 Pins) of this docu-ment.



2.7 Watchdog

For system supervision, the netX is equipped with an internal 2-stage watchdog counter. Once the watchdog is active, the timeout counter has to be triggered continuously. The watchdog works in two stages: When the IRQ timeout counter has reached zero, an Interrupt is generated, to indicate that the watchdog will soon perform a reset and needs attention. When the reset timeout counter reaches zero as well, the netX will be reset by the watchdog. The timeout register values are reloaded to the watchdog timer whenever the watchdog is triggered, which is done by setting the watchdog trigger bit. This will also clear an active interrupt request flag (timeout, stage 1 was reached). Writing to the timeout register is only possible when the write enable timeout flag is set. This allows to prevent undesired access to the timeout registers.

Internal structure of the Watchdog Logic

2.7.1 WDGACT Signal

This signal shows that the watchdog supervision is active and not expired. It can be combined for ex-ample with the power stage of a motion control system. After reset this signal is low. When the watchdog will be activated the signal goes into high state. When the watchdog timeout expired this sig-nal is cleared. When the watchdog is not enabled this signal stays low.

Timing diagram of WDGACT



2.8 Internal Memory

The netX50 contains 96 KByte static RAM, 32 KByte of Boot ROM and 32 KByte ROM reserved for special applications. The 96 KByte RAM is divided into three separate blocks of 32 Kbytes, with each block having its own interface to the data switch, allowing simultaneous data transfers to all three mem-ory blocks. Further, the chip provides two TCM (Tightly Coupled Memory) blocks (8KB data, 8 KB instruction) which can be accessed by the ARM CPU without wait states.

2.9 External Memory The netX Memory Controller can drive static RAM or FLASH and SDRAM without any additional glue logic. SRAM / FLASH and SDRAM Interface share the address and data lines and the DQM Byte lane signals, while control signals are separate for each interface. The controller has not been designed to support peripherals, which can be connected via the Extension Bus and does hence not support WAIT or READY signals (cycle times are fixed (programmable) and can not be extended by external compo-nents). Note: If more than one memory device is connected, the allowed maximum load capacity has to be consid-ered, to ensure stable operation throughout the whole temperature and operating voltage range!

2.9.1 SRAM / FLASH Interface The SRAM / FLASH Interface provides a total of three memory areas, which do not only have their own chip select signals, but also provide three independent configuration registers, allowing to set Memory Bus width and wait state parameters separately for each area. The parameters allow bus width configu-rations of 8, 16 or 32 Bit and wait states of up to 63 clock cycles. Depending on the bus width of the appropriate memory component, the 24 Bit address bus allows ac-cess to 16 MByte, 32MByte or 64 MByte of static memory per memory area. For 8 Bit areas, address lines A23:0 represent the byte address, for 16 Bit areas the word address and for 32 Bit memory areas the dword address. Hence no address lines and thus address space are wasted when using 32 Bit or 16 Bit components. To allow byte or word access in 32Bit and 16Bit mode, four Byte Lane signals (MEM_DQM3-0) are provided. Note: The interface does not support Burst or Page mode, as provided by many FLASH memory devices.

2.9.1.1 SRAM / FLASH Parameters The following parameters can be set separately for every memory block:

Parameter Description Value Dimension Tws Waitstates 0-63 CYC Twspre Additional Waitstates for setup time

MEMSR_CS0-2 and MEM_A0-23 to MEMSR_OEn and MEMSR_WEn

0-3 CYC

Twspst Additional Waitstates after data access Some components need this time to avoid data hold violations.

0-3 CYC

Bus width Data bus width of the connected component 8 16 32

Bit



2.9.1.2 SRAM / FLASH Timing SRAM / FLASH Read Cycle, 32 Bit memory SRAM / FLASH Read Cycle, 32 Bit memory (no Pre and Post Wait-states)



SRAM / FLASH Pseudo Burst Dword Read Cycle

SRAM / FLASH Pseudo Burst Dword Read Cycle (no Pre and Post Wait-states)



SRAM / FLASH Dword read access to 16 Bit memory SRAM / FLASH Dword / Word / Byte read access to 16 Bit memory (no Pre and Post Wait-states)



SRAM / FLASH Dword read access to 8 Bit memory SRAM / FLASH Dword / Word / Byte read access to 8 Bit memory (no Pre and Post Wait-states)



SRAM / FLASH Write Cycle SRAM / FLASH Dword write access to 16 Bit memory



SRAM / FLASH Dword / Word / Byte write access to 16 Bit memory (no Pre and Post Wait-states) SRAM / FLASH Dword write access to 8 Bit memory



SRAM / FLASH Dword write access to 8 Bit memory (no Pre and Post Wait-states) SRAM / FLASH Word / Byte write access to 8 Bit memory (no Pre and Post Wait-states)



The access labeled “Pseudo Burst Read Cycle” is accomplished by using ARM load multiple commands (e.g. LDMIA), allowing the consecutive read of up to 14 Dwords in a row. The same kind of cycle ap-plies when executing firmware directly from FLASH or SRAM (instructions are fetched by burst type reads, that can however be longer than 14 dwords). These accesses require the AHBL waitstate for the memory interface (which is enabled by default after reset) to be disabled (-> “SDRAM timing fix”). If this waitstate is not disabled, the chip select signal will be de-asserted between consecutive read cycles with a minimum pause of 20ns between the cycles. During write cycles the chip select signal will always be de-asserted between consecutive cycles, re-gardless of the AHBL waitstate, however the minimum pause between two cycles will drop from 30ns to 10ns with the waitstate disabled. Analog to the read cycle, the minimum pause can further only be achieved using ARM store multiple commands (e.g. STMIA). For more detailed timing information (setup and hold times) see chapter 3.4.8 of this document.

Parameter min. typ. max. Unit Remarks Tcb (cycle base time) - 10 - ns Twspre (pre cycle waitstate time) 0 - 30 ns configurable in 10ns steps Tws (waitstate time) 0 - 310 ns configurable in 10ns steps Twspst (post cycle waitstate time) 0 - 30 ns configurable in 10ns steps Tgap - 10 - ns Tpw (write to write pause) 10 - 30 ns Either 10ns or 30ns (see below) Tpr (read to read pause) - 20 - ns only if mem waitstate enabled *


Hilscher Gesellschaft für Systemautomation mbEdition 1.2 – Technical Data Referenc

The following schematics show how to connect SRAM and FLASH to the Memory Interface of the netX.

2.9.1.3 Connecting parallel FLASH Interface with 16 Bit FLASH up to 32 MBytes Interface with two 16 Bit FLASH up to 64 MBytes

Note: These examples assume the use of FLASH components that reserve address lineA0 for Low / High Byte Selection (when operat-ing In BYTE mode). However, this does notapply to all FLASH components on the market.Some components always expect 16-Bit ad-dresses and hence require to connect theaddress lines one-to-one (A0 to A0, A1 to A1,etc.) Users should always consult the datasheetof their FLASH to determine the correct way tohook up the FLASH.

H – Rheinstr. 15 – D 65795 Hattersheim e Guide:netX50#EN – 2008/11



2.9.1.4 Connecting SRAM Interface with 16 Bit SRAM up to 2 MBytes Interface with two 16 Bit SRAM up to 4 Mbytes



2.9.2 SDRAM Interface

The SDRAM controller can drive all SDRAM Single Data Rate Types from 16 MBit to 512 MBit, provid-ing a 1 GByte address space from 0x80000000 to 0xBFFFFFFF. The following parameters can be set: • Number of banks 2, 4 • Number of rows 2k, 4k, 8k, 16k • Number of columns 256, 512, 1k, 2k, 4k • Data size 32 and 16 Bit • Refresh-mode high and low priority • Power save mode SDRAM-Self-refresh-Mode with disabled clock

switch on / off SDRAM Controller The SDRAM data bus width can be either 16 or 32 Bit. In order to achieve maximum memory perform-ance, the use of 32 Bit is recommended. However, depending on your performance requirements, 16 Bit may still be the better choice for some applications, due to reduced effort for the PCB layout and smaller board size. The following table shows all supported memory combinations up to 128 (256) Mbytes total memory.

SDRAM Memory Size

Organization

Number of Chips Configuration Total Memory Size

64 MBit 2 MBit x 32 1 1x32 8 MBytes 4 MBit x 16 1 1x16 8 MBytes 4 MBit x 16 2 2x16 16 Mbytes 1) 128 MBit 4 MBit x 32 1 1x32 16 Mbytes 8 MBit x 16 1 1x16 16 Mbytes 8 MBit x 16 2 2x16 32 Mbytes 1) 256 MBit 8 MBit x 32 1 1x32 32 Mbytes 16 MBit x 16 1 1x16 32 Mbytes 16 MBit x 16 2 2x16 64 Mbytes 1) 512 MBit 16 MBit x 32 1 1x32 64 Mbytes 32 MBit x 16 1 1x16 64 Mbytes 32 MBit x 16 2 2x16 128 Mbytes 1) 64 MBit x 8 4 4x8 256 Mbytes 2)

Notes: 1) If more than one memory device is connected (e.g two 16 Bit SDRAMs instead of one 32 Bit com-

ponent or SDRAM and parallel FLASH or SRAM), the allowed maximum load capacity (data signals: max. 15 pF, control signals max. 10 pF) has to be considered, to ensure stable operation throughout the whole temperature and operating voltage range!

2) Although the SDRAM controller basically supports 4-chip configurations, such a configuration will

most likely exceed the maximum allowed load capacity!



2.9.2.1 SDRAM Parameters The SDRAM Controller runs with the 100 MHz system clock. There are a few parameters which have to be configured, according to the SDRAM components used. These are listed in the following table:

Parameter Description Value Dimension Trcd ACTIVE to READ or WRITE delay / RAS to CAS delay

1-3 CYC

Twr WRITE recovery time

1-3 CYC

Trp PRECHARGE command period time

1-3 CYC

Tras ACTIVE to PRECHARGE command time

3-10 CYC

Trfc REFRESH to command time / AUTO REFRESH period

4-19 CYC

Trefi Average periodic refresh interval 3.9 7.8 15.6 32.2

µs

CAS Latency CAS Latency 2-3 CYC For details on the SDRAM configuration registers, please consult the “netX50 Program Reference Guide”. Further timing information on the SDRAM interface can be found in chapter 3.4.7 of this docu-ment.



2.9.2.2 SDRAM Timing The following diagrams demonstrate the SDRAM parameters: SDRAM read cycle SDRAM write cycle



2.9.2.3 Connecting SDRAM The following schematics show how to connect the SDRAM to netX for the different configurations.



2.10 Extension Bus

The Extension Bus mode is one of the two basic modes, the host interface of the netX can be operated in. It is used for direct access of external peripherals or static memory from the netX. The following list provides an overview of the features of the Extension Bus: • up to 4 chip select signals with independent programmable bus width size and timing • 8 / 16 bit data bus width • multiplexed or non multiplexed data bus • 25 bit address range (32MByte) for each chip select, maximum address range 4 x 32 MByte • programmable Bus timing with wait states, setup and hold times • support for external ready or wait signal • unused interface pins can be used as general purpose input / output pins

2.10.1 Extension Bus Configuration

In order to use the Extension Bus, the netX host interface must be configured for 'Extension Bus Mode' in the DPM_ARM_IF_CFG0 register. Further, it is important to also configure each required signal line of the Extension Bus for host interface mode in the DPM_ARM_IO_MODE0 and DPM_ARM_IO_MODE1 registers. Unused signal lines of the Extension Bus may be left configured for I/O mode (e.g. unused upper address lines or data lines 15-8 when using an 8 Bit device only), allowing to use them as additional PIO signals. If the Extension Bus is enabled there is no possibility for a host system to access the virtual Dual-Port memory of the netX chip. The configuration of each Extension Bus memory area is done through the 'Extension Bus Configura-tion Chip Select' register. For a detailed register description see the 'Program Reference Guide'.

2.10.2 Extension Bus Address Space and netX Memory Allocation

The Extension Bus address space is accessible by the netX through four different memory base ad-dresses. All internal accesses between 0x2000_0000 and 0x3FFF_FFFF are mapped to the external peripherals or memory connected at the Extension Bus. Each of the four chip select signals uses a 32M byte memory window. The address lines EXT_A25 and EXT_A26 are internally decoded for the chip select generation. The upper address lines EXT_A27 and EXT_A28 are not decoded. The following table shows the allocation addresses in the netX memory range.

netX Start Address netX End Address Description ARM buffered 0x3FFF_FFFF - Mirrored address windows no 0x3600_0000 0x27FF_FFFF EXT_CS3n 32M byte address window no 0x3400_0000 0x25FF_FFFF EXT_CS2n 32M byte address window no 0x3200_0000 0x23FF_FFFF EXT_CS1n 32M byte address window no 0x3000_0000 0x21FF_FFFF EXT_CS0n 32M byte address window no 0x2800_0000 0x2FFF_FFFF - Mirrored address windows yes 0x2600_0000 0x27FF_FFFF EXT_CS3n 32M byte address window yes 0x2400_0000 0x25FF_FFFF EXT_CS2n 32M byte address window yes 0x2200_0000 0x23FF_FFFF EXT_CS1n 32M byte address window yes 0x2000_0000 0x21FF_FFFF EXT_CS0n 32M byte address window yes



2.10.3 Address and Data Byte Steering

The Extension Bus logic is capable of handling all 8, 16 or 32 bit netX accesses from netX to the exter-nal peripherals or memory devices. According to the bus width configuration of the Extension Bus an access from netX side is converted to external 8 or 16 bit accesses. For example a 32 bit access to an 8 bit device is converted to four 8 bit accesses. The following table shows the address and data steering between netX and external devices. Note: When performing an access to an Extension Bus memory location by the ARM CPU, the CPU will be stopped, until the access is completed. Hence, 32 bit accesses to a slow 8 bit device may have a sig-nificant impact on the netX performance and will increase interrupt latency, or DMA transfer times. Extension Bus Data Width Address / Data Byte Steering

8 Bit

netX Data 0-7 netX Data 8-15 netX Data 16-23 netX Data 24-31

→

Extension Bus Data 0-7 Extension Bus Data 0-7 Extension Bus Data 0-7 Extension Bus Data 0-7

ADR[1:0] = 00 ADR[1:0] = 01 ADR[1:0] = 10 ADR[1:0] = 11

16 Bit (Byte access)

netX Data 0-7 netX Data 8-15 netX Data 16-23 netX Data 24-31

→

Extension Bus Data 0-7 Extension Bus Data 8-15 Extension Bus Data 0-7 Extension Bus Data 8-15

ADR[1:0] = 00 ADR[1:0] = 01 ADR[1:0] = 10 ADR[1:0] = 11

16 Bit (Word access) netX Data 0-15 netX Data 16-31 → Extension Bus Data 0-15

Extension Bus Data 0-15 ADR[1:0] = 00 ADR[1:0] = 10

Address and Data Byte Steering

2.10.4 Intel / Motorola Data Format

The netX system works with Intel memory format (little endian). There is no special mode for connecting to Motorola type (big endian) memory systems, hence any necessary data conversions must be pre-formed by software, when accessing big endian components.

2.10.5 Multiplexed / Non-Multiplexed Data Bus

Besides devices with a separate memory and data bus, the Extension Bus also supports devices with a multiplexed data bus. The timing and polarity of the address latch enable signal and data hold times can be programmed in a wide range.

2.10.6 Data Ready or Data Acknowledge

When the external wait/ready function is enabled, the EXT_RDY signal is sampled at the rising system clock edge during the active access. It must be asserted at least 2.5 clock cycles prior to the rising edge of read or write strobe signal to add wait states to the current cycle. The polarity of the signal can be programmed, supporting devices with ready- as well as devices with wait signal generation.



2.10.7 End-Of-Cycle

When the end of the access cycle specified by the Trdwrcyc parameter is reached, the cycle will be stopped immediately and all active signals will be de-asserted. Users should take care when setting timing parameters, as the versatility of the interface also allows settings that don’t make sense. If, for example, the write delay time Twron is greater than the complete cycle time specified by the Trdwrcyc parameter, the EXT_WRn signal will never be asserted!

2.10.8 Pin Description Of Extension Bus

The following table provides an overview of all Extension Bus signals. Pin Name Intel Motorola Description EXT_D0-15 DATA[15:0] DATA[15:0] Extension Bus Data 0-15 EXT_A0-24 ADDR[24:0] ADDR[24:0] Extension Bus Address 0-24 EXT_CS0n CS0n CS0n Extension Bus Chip select 0 EXT_CS1n CS1n CS1n Extension Bus Chip select 1 EXT_CS2n CS2n CS2n Extension Bus Chip select 2 EXT_CS3n CS3n CS3n Extension Bus Chip select 3 EXT_ALE ALE ASn Extension Bus Address Latch Enable EXT_BHEn BHEn BHEn Extension Bus High Enable EXT_RDn RDn RD/WRn Extension Bus Read EXT_WRLn WRLn DSLn Extension Bus Write Low EXT_WRHn WRHn DSHn Extension Bus Write High EXT_RDY WAITn READYn Extension Bus Ready EXT_IRQ IRQn IRQn Extension Bus Interrupt Request

Extension Bus Interface signals



EXT_D0-15 Bi-directional data bus. When an 8 bit data bus is selected the high byte of the

data bus can used as programmable input / output pins. EXT_A0_24 25 Bit address bus. Each address line can be individually enabled or disabled.

So it is possible to use the higher address lines as programmable input / out-put pins if the complete address range is not required. The address line EXT_A0 is low when an even byte or word is accessed. It will be active for 8 bit and 16 bit data bus width.

EXT_CS0n External chip selects for extension bus. These signals are decoded using EXT_CS1n internal address lines EXT_A27 and EXT_A28. EXT_CS2n EXT_CS3n EXT_ALE Address latch enable used for multiplexed address- / data-bus accesses. If

active, it indicates a valid address driven on the data bus. Used for Intel and Motorola multiplexed bus modes.

EXT_BHEn Byte High Enable. This signal is asserted when an odd byte or a word is ac-

cessed. It will be active for 8 bit and 16 bit data width. EXT_RDn Active low read signal, can be also configured as a direction signal

EXT_RD/WRn for Motorola type interfaces. EXT_WRLn Active low write or write low signal, depending on configuration. This signal

can be configured as the data strobe or low byte data strobe signal for Mo-torola type interfaces.

EXT_WRHn This is the high byte write strobe signal and can be also configured as the

high byte data strobe signal for Motorola type interfaces. EXT_RDY External data ready or data acknowledge input for access cycle extension.

The polarity of this signal can be configured. The input signal is internally con-nected to high level when used as input / output pin.

EXT_IRQ External interrupt request pins, level triggered. The interrupt lines are inter-

nally connected to a low level when the pins are programmed as input / output pins.



2.10.9 Extension Bus Component Connection

Intel, 8 Bit non multiplexed, one write signal Intel, 8 Bit multiplexed, one write signal Intel, 16 Bit non multiplexed, one write signal Intel, 16 Bit multiplexed, one write signal Intel, 16 Bit non multiplexed, write low/high signals Intel, 16 Bit multiplexed, write low/high signals



Motorola, 8 Bit non multiplexed, one write signal Motorola, 8 Bit multiplexed, one write signal Motorola, 16 Bit non multiplexed, one data strobe Motorola, 16 Bit multiplexed, two data strobe



2.10.10 Extension Bus Timing without Wait-states

Parameter Description Value Dimension Talewidth Delay time from start cycle until ALE inactive 0-7 CYC Tadrhold Delay time from start cycle until invalid address at the data bus. 0-7 CYC Tcson Delay time from start cycle until Chip Select insertion 0-7 CYC Trdon Delay time from start cycle until RD low in system clocks 0-7 CYC Twron Delay time from start cycle until WR low in system clocks 0-7 CYC Trdwroff Delay time from start cycle until RD or WR inactive delay for accesses

in system clocks 0-31 CYC

Trdwrcyc Set the end of an access cycle in system clocks The values 0x00 and 0x01 are interpreted as 0x20

2-32 CYC

Tdsu Data setup time for read accesses 1 CYC



2.10.11 Extension Bus Timing with Wait-states

Parameter Description Value Dimension Trvwsi Ready valid to waitstate insertion delay 2.5 CYC



2.11 Dual-Port memory

The Dual-Port Memory (DPM) interface is used for allowing data transfer between the netX chip and an external host system. Unlike standard DPM components, the netX DPM is a virtual Dual-Port memory, which appears as a 64k linear memory to the host side, while accesses to the DPM are redirected to one or up to eight different memory areas, located anywhere within the complete netX memory map, including also register areas. The interface of the netX DPM is widely configurable and can hence support virtually any common µP interface like Intel 80186/188, Motorola MC68000, ColdFire, or ARM CPU based processors, just to name a few. The Dual-port memory structure is programmable from netX side and hence fully firmware specific. The following list provides an overview of the Dual-port memory features. • 64 kByte maximum total size with a fixed structured control block at the highest 512 Bytes • up to eight DPM memory areas of individual size, that can be mapped to different areas of netX

memory space. • up to sixteen handshake register pairs with programmable register width of 8 or 16 bit • support for 8, 16 or 32 bit data bus • support for multiplexed or non multiplexed data bus • programmable control lines that let external glue logic become obsolete • interrupt and data ready generation Note: Like all other digital I/Os of the netX50, the DPM interface uses 3.3V signaling voltage and can NOT be made 5V tolerant (like the netX500/100)!

2.11.1 Dual-Port Memory Interface Mode

In order to use the netX Dual-port memory interface, the netX host interface must be configured for 'µP Bus Mode' in the DPM_ARM_IF_CFG0 register. Further, it is important to also configure each required signal line of the DPM for host interface mode in the DPM_ARM_IO_MODE0 and DPM_ARM_IO_MODE1 registers. Unused signal lines of the DPM may be left configured for I/O mode (e.g. the unused upper address lines or data lines 15-8 when using an 8 Bit device only), allowing to use them as additional PIO signals. If the Dual-port memory is enabled, there is no possibility to use the Extension Bus interface. Note: As long as not configured otherwise (firmware or DPM boot mode), all host interface pins are configured for input mode and are pulled high by internal pull-up resistors. Users should make sure, that these high level signals will not cause undesired behaviour of their host system (e.g. active high Interrupt signal) and provide appropriate pull-down resistors where necessary.



2.11.2 Dual-Port Memory Structure and Allocation

As mentioned in the previous chapter, the netX does not contain a real Dual-port memory as the user may know it. All addresses within the linear address range of the Dual-port memory are mapped to one or more netX memory areas a programmable address decoder. The destination can be a special control register, an internal memory area or an external memory device. Only a small area of 512 bytes located at the end of the DPM is “hard-mapped” to the host accessed control register block. Note: Though they are destined for host access only, these host accessed control registers, as well as the host accessed handshake register block are also accessible from netX side. This possibility was imple-mented for debugging purposes and should hence only be used with great care! Reading or writing these control registers from netX side may cause undesired behavior. This applies particularly to ac-cesses to the handshake register block, which affects the handshake interrupt handling (reading a host access handshake register from the netX side may clear a pending handshake interrupt linked to this handshake cell, before the host was able to respond to that interrupt) The total address size of the linear accessed Dual-port memory is 64 kByte with a fixed structured con-trol block at the highest 512 Bytes from 0xFE00 until 0xFFFF. The rest between address 0x0000 and 0xFDFF is available for data transfer. The following table shows the Dual-Port memory structure from host side. Keep in mind that the the lower area from 0x0000 until 0xFDFF is only an example because the structure can be programmed from netX side.



Byte 3 Byte 2 Byte 1 Byte 0

0xFFFC - 0xFF00

fixed global control block - Interrupts - Software Reset - System Status - Host Timer - Process Data Watchdog Timer

0xFEFF - 0xFE00 extended control block

0xFDFF - 0xA000 Unused area with nearly 24k bytes 0x9FFF - 0x9FFC Host netX Handshake Flags (16 bit) netX Host Handshake Flags (16 bit) 0x9FFB - 0x7800 Data Memory Block 8 with nearly 10k bytes 0x77FF - 0x7000 Data Memory Block 7 with 2k bytes 0x6FFF - 0x6000 Data Memory Block 6 with 4k bytes 0x5FFF - 0x5000 Data Memory Block 5 with 4k bytes

0x4FFF - 0x4FFC Host netX Handshake Flags

netX Host Handshake Flags Handshake Data Memory 2 Bytes

0x4FFB - 0x2800 Data Memory Block 4 with nearly 10k bytes 0x27FF - 0x2000 Data Memory Block 3 with 2k bytes 0x1FFF - 0x1000 Data Memory Block 2 with 4k bytes 0x0FFF - 0x0000 Data Memory Block 1 with 4k bytes

Example of Dual-port memory structure

2.11.3 Global Control Block

The global control block hosts several DPM related registers for exchanging status information, interrupt handling, watchdog and timer functions.This ‘hard mapped’ 512 Byte block is located at DPM offset 0xFE00. The next chapters describe the functions that can be accessed through the global control block.

2.11.3.1 DPM Interrupts The global control block contains interrupt status and mask registers for all DPM related interrupts. Sources of a netX side DPM interrupt can either be the five possible interrupt input signals (PIOs 35,36,40,47,72), the 16 handshake cells, a DPM watchdog timeout or a memory lock error (host access to unmapped DPM memory area). On the host side, possible interrupt sources are again the 16 hand-shake cells, DPM watchdog timeout, a system status change and host timer event. Each interrupt request can be enabled or disabled independently and is “OR-ed” with any other enabled DPM interrupts to the global interrupt request for the host interface, which is routed to the VIC (Vectored Interrupt Controller) of the netX, respectively to the host interrupt output signal of the netX. While all DPM interrupt sources have separate flag bits, their status can additionally be read through a common 8 Bit interrupt vector, that always reflects the active (and enabled) interrupt with the highest priority. When this interrupt is cleared, the vector displays the next active (and enabled) interrupt with the next lower priority. When no (enabled) interrupts are active, the vector has the value 0x00. An inter-rupt status flag is cleared by writing a one to the status flag (writing a zero has no effect). When a handshake register is read, the corresponding interrupt is cleared automatically.



One global interrupt request bit signals, that one or more interrupt request is active. While all interrupt status flags will always be set when the appropriate source is active (regardless if the interrupt has been enabled or not), the global Bit is only set when at least one of the active interrupts has also been en-abled, which correspondingly applies to the reset vector. For more details see the appropriate chapter of the 'netX - Program Reference Guide'.

2.11.3.2 DPM Software Reset The DPM Software Reset register allows the host processor to reset the netX chip. This is done by a special access procedure. After initiation, the chip will be reset after 1 ms (this delay ensures the proper completion of the current write cycle). The software reset is comparable to any other Reset except the Power On Reset (see chapter 2.5 (Reset) for details). For initiation of the DPM software reset, the host has to write the sequence 0x00, 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40 and 0x80 to the 'DPMHS_RES_REQ' register. For more details see the appropriate chapter of the 'netX - Program Reference Guide'.

2.11.3.3 System Status The DPM Global Control Block also contains a system status register ('SYS_STA) which is determined for exchanging status information between the netX and the host processor chip. Some bits of this reg-ister can only be written from netX side and some bits are only writeable from host side. This register also controls the state of the status LED 'RDY' and 'RUN' (see chapter 2.3 ). There is an 8 bit field for the NETX_STATUS_CODE which can be used by the netX software to provide status information to the host. If enabled, a system status interrupt (external interrupt to the host system) will be generated on any write access to the data bits 8 to 15 of the system status register. For more details of the system status register see the 'netX - Program Reference Guide'.

2.11.3.4 Host Timer The host has the possibility to use this timer for cyclic interrupt generation or as a count down timer. The timer is a 16 bit count down timer and can generate an interrupt at the host system side. There are two different timer modes: The first mode will let the timer stop after counting down to zero and set the interrupt event only once. In the second mode, the interrupt can be generated too but on reaching zero, the timer will be reloaded with the configured timeout value and will continue to run allowing a cyclic interrupt event to be generated. Host Timer programming is done by setting the timer start count value TMR_START in the 'DPMHS_TMR_START' register, selecting the time base, the function mode and setting the start flag in the 'DPMHS_TMR_CTRL' register. When the start flag is set, the counter is loaded with the timer start count value and started. Setting the start flag again is also possible during timer operation and causes a reload of the timer, while clearing the start flag causes the timer to stop counting. The clock divider register bits provide the possibility to select different clock time bases. The divider counter for time base generation will be also cleared when the host timer start flag is being set or the time base value is changed. For more details of host timer programming see the 'netX50 - Program Reference Guide'.



2.11.3.5 Process Data Watchdog Timer Besides the system watchdog (see chapter 2.7) the netX contains two more watchdog timers for super-vision of netX and host system: • Watchdog Timer Host • Watchdog Timer netX Watchdog Timer for Host Supervision (Watchdog Host) This 16 bit count down watchdog timer can be used for supervision of the host system. The netX chip can set a timeout value, which can be read from the host system. The timeout value can be changed by the netX any time. The watchdog timer is being disabled by setting the timeout value to zero, which is the default value after a power on reset. Once the timer is running, the host system has to periodically trigger the timer within the watchdog timeout period to avoid generating the host timeout event which causes a host timeout interrupt on the netX side. Whenever the watchdog timer is triggered by the host system, the timer register will be loaded with the timeout value. Setting another timeout value from netX side will not change the current counter value of the watchdog timer. The new timeout value will be loaded when the host system per-forms the next triggering of the watchdog timer. After configuration by the netX, the timer will not start to run, until the host system triggers the watchdog the first time. The time base of the watchdog timer is fixed to 100 µs. The timeout range can be selected between 100µs and 6.50 sec. The following formula is used for calculation of the timeout parameter: TIMEOUT_HOST = TIMEOUT_VALUE x 100 µs For triggering the watchdog timer, there is a register which can be accessed from the host system. Trig-gering the watchdog timer is only possible with a special access code. This access code is generated by a pseudo random generator and is only valid for one access, which reduces the probability that a crashed host application still retriggers the watchdog. The following sequence must be completed to trigger the watchdog timer:

• read the watchdog trigger register to get the next WDG_TRIGGER_CODE • write back the new watchdog access code to the WDG_HOST_TRIG register

Watchdog Timer for netX Supervision (Watchdog netX) This watchdog timer has an analog functionality to the watchdog timer for host supervision, however the direction is reversed (netX triggers watchdog and host interrupt is generated on a watchdog timeout). For details on watchdog timer registers see the 'netX - Program Reference Guide'.

2.11.3.6 Extension Control Block This block is reserved for future extensions.



2.11.4 Data Memory Area / Data Memory Blocks

The complete DPM memory area can be divided into a maximum of eight memory blocks. From host view, these blocks are located at the address range between 0x0000 and 0xFDFF. The start address, where each Dual-port memory block is mapped in the internal netX address range, is programmable by the netX. Accesses to these data memory blocks are forwarded by the netX host interface to the netX memory range. The target of a data memory block can either be an internal memory area, a register area, or external memory (SDRAM/SRAM/FLASH). There is no default mapping after a power on reset, yet the host interface isn’t even enabled, hence the DPM area can only be accessed from the host, after the DPM has been configured by the netX firm-ware or the DPM boot mode (see chapter 2.3 ) When the host system tries to access a memory address of the Dual-port memory which is not mapped, the access is aborted and, if enabled, an interrupt event occurs on the host side (Memory Lock Inter-rupt). While write accesses will be ignored, read accesses will always reveal the data 0x0BAD. For details on how to configure the DPM mapping, please consult the netX50 Program Reference Guide (chapter 5.2)



2.11.5 Handshake Registers

To allow synchronization of the data transfer between host system and netX, a total of 16 handshake register pairs with interrupt capability are available. Handshake registers can be 8 or 16 bit wide and are hence available for all selectable DPM bus widths. While both registers of a handshake register pair are readable by host and netX, the upper register of the pair can only be written by the host, while the lower register can only be written by the netX. Writing to a handshake register from the host side, can gener-ate a host interface interrupt on netX side, while writing from the netX side can generate a host interrupt (signal DPM_INT). After receiving an interrupt, the processor (host CPU, respectively netX) has to ei-ther check the interrupt vector or the handshake flags to identify the handshake register(s) that caused the interrupt and either read the corresponding handshake register, which will automatically clear this handshake interrupt, or clear the corresponding handshake interrupt flag (by writing ‘1’ to the flag bit). The Dual-port memory offset address of each register pair is set by the netX. If the handshake register pair is located at the upper end of a data memory block, then the structure is equal to standard Dual-port memory devices which are commonly used to connect two microprocessor systems with each other. The base address of the 8 or 16 bit handshake register pairs in the Dual-port memory must be a DWORD aligned address. These addresses can be set anywhere in the Dual-port memory address range, except the 512 Byte control block at the upper end of the DPM address range. The absolute address of a handshake register in the Dual-port memory depends on the register width. The following example shows the address assignment: 8 bit register width Host netX handshake register = BASE_ADDRESS[15:2] + 03h

netX Host handshake register = BASE_ADDRESS[15:2] + 02h 16 bit register width Host netX handshake register = BASE_ADDRESS[15:2] + 02h

netX Host handshake register = BASE_ADDRESS[15:2] + 00h While it does not make sense, to set up 16 Bit Handshake registers with an 8 Bit wide DPM interface, 8 Bit handshake registers may also be used when operating the DPM interface in 16 Bit mode. Any access of the host to a handshake register address will not be redirected to a netX data memory area, but will be mapped into the corresponding register within the handshake register block. If the 8 bit handshake register mode is selected any access from host side to memory location at byte 0 and byte 1 of the DWORD aligned handshake pair base address will also be mapped into the handshake registers. Though each handshake register pair comprises of only one physical 32 Bit register, there are three ways to access the register pairs. There is an address block for netX access, an address block for host access and the standard access path through the DPM. The register addresses for netX access are located between 0x1C003500 and 0x1C00353F. When accessing the handshake registers via these addresses, only the netX-to-host part of the register is writeable and reading a register automatically clears an appropriate netX side handshake interrupt. The register addresses for host access are located between 0x1C003200 and 0x1C00323F. When accessing the handshake registers via these addresses, only the host-to-netX part of the register is writeable and reading a register automatically clears an ap-propriate host side handshake interrupt. It is also this address range that will internally be used, when directly accessing the handshake register pair from host side through the DPM. If for example, hand-shake register pair 1 has been set up at DPM address 0x2000, an access to 0x2000 will be redirected to address 0x1C003204, the host side address for handshake register pair 1. (of course, the whole host side handshake address block could also be mapped to a DPM memory range. In that case, each handshake register could be accessed through two different DPM addresses). As both address ranges, netX side and host side, are part of the netX address range, it is possible to also access the host side registers from the netX. This was implemented for debugging purposes and should be used with care to avoid undesired system behaviour (if a host handshake interrupt is pending and the netX reads the corresponding host side register, the interrupt may be cleared before the host



had the chance to respond to the interrupt)! As the netX side handshake registers address block could be mapped into a DPM memory area, the note above also applies to the host side. Through such a mapping, a host could read a handshake register through the netX path instead of the host path (and clear a pending netX interrupt, that was actually supposed to be cleared by the netX). Due to the full programmability of the Dual-port memory structure, configurations are possible, where the global control block, one (or more) handshake register pair(s) and a data memory block overlap each other. A hardware priority decoder of all data memory blocks and registers will solve such a situa-tion. The following table shows the priority assignment of the memory blocks:

Priority Level Memory Block Name

highest Global Control Block Handshake Register Pair 0

:

Handshake Register Pair 15 lowest Data Memory Block [7:0]

Dual-port memory data priority level Note: There is no default handshake register mapping after a power on reset, hence the desired handshake registers must be configured by netX firmware, before they can be used.



2.11.6 Dual-Port Memory Interface Configuration

The Dual-port memory interface configuration is done from netX side by the 'DPM_ARM_IF_CFG0' and ' DPM_ARM_IF_CFG1' registers. For more information about these registers, see the 'netX50 - Pro-gram Reference Guide'.

2.11.7 DPM interface signals

The control signals of the DPM interface are user configurable, which allows to connect common host processors to the netX without external glue logic. The following table shows an overview of all interface pins (in 32 Bit mode, DPM_A16-19, DPM_SELA12-19, DPM_ALE, DPM_A0, DPM_A1, DPM_BHEn and DPM_WRHn are not available, as they are used for the upper 16 data signals and the four Byte enable signals). Pin Name Intel Motorola Description DPM_D0-15 D[15:0] D[15:0] Dual port memory Data 0-15 DPM_D16-31 D[16:31] D[16:31] Dual port memory Data 16-31 DPM_A0 A[0] A[0] / BE0n / LDSn Dual port memory Address 0 or Byte Enable 0 DPM_A1-15 A[15:1] A[15:1] Dual port memory Address 1-15 DPM_A16-19 A[19:16] A[19:16] Dual port memory Address 16-19 (optional) DPM_SELA12-19 - - Inputs for internal address comparator (A12-19) DPM_BE0-3 - - Dual port memory Data Byte Enables (32 Bit mode, only) DPM_ALE ALE AS Dual port memory Address Latch Enable DPM_CSn CSn CSn Dual port memory Chip Select DPM_BHEn BHEn EN / BE1n / UDSn Dual port memory High Bus Enable DPM_RDn RDn RD/WRn Dual port memory Read DPM_WRLn WRLn - Dual port memory Write Low DPM_WRHn WRHn - Dual port memory Write High DPM_RDY WAITn TA Dual port memory Ready DPM_INT INT INT Dual port memory Interrupt

Host interface pins in DPM mode DPM_0-31 Bi-directional data bus. The interface supports 8, 16 and 32 bit data busses

and can be operated in multiplexed or non multiplexed mode. DPM_A0-19 Address bus. In multiplexed address mode the lowest 8 or 16 bit lines can be

used as programmable input /output signals. DPM_ALE Address latch enable or address strobe. In multiplexed data bus mode this

signal can be configured as active high / low or positive / negative edge trig-gered signal.

DPM_CSn Chip select signal for Dual-port memory access. Instead of the chip select, an

internal address comparator can also be used. DPM_BHEn Byte high enable signal. Controls the access to the upper byte of the Dual-port

data bus. DPM_RDn Read signal (Intel type interface) or data direction signal RD/WRn (Motorola

type interface). DPM_WRLn



DPM_WRHn Write strobe lines for high and low data byte. For 8 bit modes only the DPM_WRLn line is used

DPM_RDY The ready signal or transfer-acknowledge signal controls the access end of

each cycle to the netX. Several operating modes are programmable. The po-larity and the driver type can be configured. It is possible to switch the signal between wait mode (waitstate insertion) and ready mode (transfer ready).

DPM_INT The interrupt signal is the global interrupt request output to the host system.

Several operating modes are programmable like polarity and driver mode.

2.11.8 Interrupts and Interrupt Signal

The electrical characteristic of the interrupt request line from netX to the host system is programmable. There are four different interrupt output modes: • High Impedance • Fixed high or low output level • Push-Pull output, active high or active low • Open Drain / Open Source output depending on the interrupt polarity. After power up, the interrupt pin will be in high impedance state until configured otherwise. When pro-grammed as a normal interrupt output (push / pull), the signal is driven high or low when an interrupt request has occurred. In Open Drain / Open Source configuration it is necessary to connect an external pull-up or pull-down resistor for maintaining a valid (and inactive) signal level when no interrupt is active. Interrupt signaling for open source output with external pull-up resistor



2.11.9 Data Ready Signal

The Data Ready Signal allows the netX to extend the current DPM access cycle until the requested data is available (read) or write data has been accepted. The signal mode and polarity, as well as the drive mode, are programmable: Signal modes: • WAIT/BUSY mode, active low (Mode 0) • WAIT/BUSY mode, active high (Mode 1) • READY mode, active low (Mode 2) • READY mode, active high (Mode 3) Drive modes: • High Impedance output (Mode 0) • Push-Pull output (Mode 1) • Sustained Tri-state output (Mode 3) • Open Drain / Open Source (depending on the configured polarity (Mode 2)) After power up, the DPM_RDY pin will be in high impedance state until configured otherwise. In push-pull mode, the signal is always driven. In Open Drain / Open Source mode the signal will be driven only during its active state, hence it is necessary to use external pull-up or pull-down resistors for maintain-ing a valid (and inactive) signal level when the DPM_RDY is not active. The sustained tri-state output mode works similar to the Open Drain / Open Source output mode, however the signal remains being driven when entering the inactive state for one cycle before entering the high impedance state. This provides a faster signal edge than it could be achieved by a pull-down or pull-up resistor, while the sig-nal may still be shared with other components. In WAIT/BUSY mode, an active signal means, that the netX DPM is not yet ready and the host needs to extend the access. In READY mode an active signal means that the netX DPM is ready and the host may terminate the access. However, the READY mode is not just a negation of the WAIT mode (see the following diagram for the difference between WAIT/BUSY and READY) When in WAIT/BUSY mode, the DPM_RDY signal will always become active on a read access, while single write accesses are usually accepted without activating the signal. In READY mode, the signal will be activated on any access. If enabled, an internal counter ensures, that the access time will not exceed 256 µs, which would occur if an access from host side is mapped into external netX memory which will be always signaling not ready (e.g. unconfigured or powered down SDRAM). In such cases, the current access will be aborted after 256µs, allowing the host processor to end the cycle, which prevents system lock up conditions at the host side. The netX50 further provides a corresponding host interrupt, allowing the host CPU to detect such timeout events.



Comparison of different data ready configurations (see chapter 3.4.12 for timing parameters)



2.11.10 Dual-Port Memory circuits

This chapter provides a brief view of some standard interface circuits. See the 'netX50 – Program Ref-erence Program' for corresponding interface configuration register setting.





2.12 Timer

The netX provides five 32-Bit Counters which can be configured to: • count from zero to a maximum value and backward (symmetric Mode) • count from zero to a maximum value and set back to zero (asymmetric Mode) • single shot or count continuously • generate an interrupt if it reaches zero • count external events • set back to zero by an external event • capture the timer value by an external event • generate a PWM signal by comparing the timer value with a threshold value As external events, any GPIO can be assigned. This can be a rising or falling edge respectively a high or low level at the GPIO by setting the inverting bit at the GPIO configuration register. The counter value can be read and overwritten any time. Timer function diagram



2.13 IEEE 1588 System Time

The precision System Time derives from a counter, clocked with the 100 MHz system clock and has a resolution of 10 ns from the view of the application. Due to drift, aging or failure of the crystal this time can differ from a system wide master clock which is very often needed in Real-time Ethernet system. The System Time is not realized by a standard counter but uses an adder which increases the current time value by a programmable number (nominally10) every clock period. If the 100 MHz clock has a deviation to the master clock then the added value will slightly differ of 10 with a resolution of 2-28 ns to compensate the deviation. This can be calculated based on the protocol of IEEE 1588 or other Real-time Ethernet functions. The System Time is provided in two 32-Bit registers. One register represents the seconds and the other represents the nanoseconds from time zero. The application has to read the seconds value first, be-cause this will freeze the nanoseconds register to get a consistent System Time. Calculation of the System Time The following diagram shows how the time clock compensation works. With a clock period of ∆T =10ns the value ∆CNT = 10 will be added continuously to the System Time CNT1 to reach CNT 2 exactly at T2. If the clock runs to fast CNT2 will be reached after T2fast or if the clock is too slow, CNT2 is reached after T2slow. If ∆CNT is calculated exactly then CNT2 will be reached at T2. The procedure of an ongoing correction prevents the problems of a one step correction resulting in a large step of the System Time.

Ongoing correction of time failure



2.14 JTAG Debug Interface

2.14.1 Standard JTAG connector The netX Debug Interface is based on the Joint Test Action Group (JTAG) IEEE Standard 1149.1 and supports debugging tools, compliant with this standard. It provides two different modes of operation: ARM Debug mode and Boundary Scan mode. By default, the netX JTAG interface operates in ARM Debug mode, passing all JTAG signals to the integrated ARM CPU. See chapter 2.14.3 for information, on how to activate the Boundary Scan mode. The JTAG connector is a 20 pin Insulation Displacement Connector (IDC) keyed box header (2.54 mm male) that matches with IDC sockets mounted on a ribbon cable and provides the following signals:

Pin ARM Signals netX Signals Pin ARM Signals netX Signals 1 VTref +3.3V 2 Vsupply +3.3V 3 nTRST JT_TRSTn 4 GND VSS 5 TDO JT_TDO 6 GND VSS 7 TMS JT_TMS 8 GND VSS 9 TCK JT_TCK 10 GND VSS 11 RTCK Not used 12 GND VSS 13 TDI JT_TDI 14 GND VSS 15 nSRST PORn 16 GND VSS 17 DBGRQ Not used 18 GND VSS 19 DBGACK Not used 20 GND VSS

Two different reset signals are involved when using the JTAG interface of the netX: nSRST Open collector output form the ICE to the target system reset. This is also an input to the ICE so that a reset initiated on the target can be reported to the debugger. nTRST Open collector output from ICE to the reset signal on the netX JTAG port. The target board must include a pull-up resistor on both reset signals.

JTAG Interface with voltage supervisor chip (i.e. MAX 823).



18

Top View

1 8

Front View

2.14.2 Hilscher “mini-JTAG” Connector For netX products with small board size that do not allow implementation of the standard 20 pin JTAG connector, while still requiring access to the JTAG interface, Hilscher has defined an 8 pin JTAG inter-face port for the connection of Flex Cables. Of course, users are free to use any suitable connector for a JTAG interface in their application, along with a custom cable adaptor. Implementing the Hilscher de-fined connector however releases the user from defining and building such an adapter, as there is already an appropriate adapter for the “mini-JTAG” connector available from Hilscher. This adapter provides a standard 20 pin JTAG connector to be used with common debugger devices and a Flex cable, that connects to the “mini-JTAG” port. The adaptor also provides the required pull-up resistor on the JT_TRST signal, leaving the netX JTAG interface disabled (in Reset state), achieved through the internal pull-down on the JT_TRST pin, when not connected to the application. For details on the connector (dimensions, recommended land pattern, etc) please consult the appropri-ate manufacturer datasheet). Connector Signals Manufacturer Product ZIF Flex cable connector,vertical 8 JST 08FLT-SM1-TB ZIF Flex cable connector, horizontal 8 JST 08FLZ-RSM1-TB

Connector Pinout:

Note: The “mini-JTAG” connector does not allow the debugger to reset the netX (Target Reset), as the appro-priate signal (PORn) ist not available on the connector! This means, that resetting and stopping the target before the bootloader has been started is not possible with this solution. Further, some debug-gers have problems to properly connect the target when the PORn signal is not available, hence the use of this solution is only recommended when the design does not provide enough space for a stan-dard JTAG connector or a custom solution that provides the PORn signal!

Pin Signal name 1 +3V3 2 GND 3 JT_TCK 4 JT_TDO 5 JT_TDI 6 JT_TMS 7 JT_TRST 8 GND



2.14.3 Boundary Scan mode Besides the (default) ARM Debug mode, the netX JTAG interface also supports a second mode, allow-ing the user to run Boundary Scan tests on the netX, by the use of appropriate (third-party-) tools. To activate the Boundary Scan mode, refer to the following table, indicating the required state of certain netX signals: Signal Pin number State TEST G5 high MMIO14 (GPIO14) T1 high MMIO08 (GPIO08) M1 low MMIO09 (GPIO09) N1 low MMIO10 (GPIO10) N2 low MMIO11 (GPIO11) P1 low

As all above mentioned pins are equipped with internal pull-down resistors (50k), MMIOs08-11 can be left unconnected, however TEST and MMIO14 need to be pulled high. Due to the digital nature of Boundary Scan, some (analog-) netX pins can inherently not be controlled by Boundary Scan, while others are involved in the scan mode itself and are hence not accessible ei-ther. This applies to all power pins (VSS, VDDIO, VDDC), as well as all pins of the Ethernet PHYs, the USB port, the JTAG port, all test pins (TEST, TMC1, TMC2, TACT_RST), all oscillator-pins, as well as MMIOs08-14. For further details please consult the appropriate netX50 BSDL files, which will be avail-able for download from the Hilscher website as soon as published .



2.14.4 Embedded Trace Macrocell ETM The ETM is a Real-Time trace module capable of instruction and data tracing. The ETM is an integral part of the ARM microcontroller and works with special debug tools like the Hitex Tool chain for ARM. The ETM comprises the following main components: Trace port Output signals that help to understand the operation of the processor. Triggering and filtering facilities An extensible specification enables to control tracing by specifying the exact

set of triggering and filtering resources required for particular application. Re-sources include address comparators and data comparators, counters and sequencers.

The netX contains the ETM9 Rev 2a (ETM Architecture ETMv1.3) in medium configuration. The connector for the ETM is standardized by ARM. Further information is available at www.arm.com. It is highly recommended to implement accordingly otherwise the debug tools will not work correctly. The following table shows the pin assignment of the 38-pol. AMP Mictor connector 2-767004-2 as de-fined by ARM.

Pin ARM Signals netX Signals Pin ARM Signals netX Signals 1 Nc 2 Nc 3 Nc 4 Nc 5 GND VSS 6 TRACECLK ETM_TCLK 7 DBGRQ ETM_DRQ 8 DBGACK ETM_DACK 9 nSRST Not used 10 EXTTRIG 11 TDO JT_TDO 12 VTRef VCCIO 13 RTCK Not used 14 VCC VCCIO 15 TCK JT_TCLK 16 TRACEPKT[7] ETM_TPKT07 17 TMS JT_TMS 18 TRACEPKT[6] ETM_TPKT06 19 TDI JT_TDI 20 TRACEPKT[5] ETM_TPKT05 21 nTRST JT_TRSTn 22 TRACEPKT[4] ETM_TPKT04 23 TRACEPKT[15] ETM_TPKT15 24 TRACEPKT[3] ETM_TPKT03 25 TRACEPKT[14] ETM_TPKT14 26 TRACEPKT[2] ETM_TPKT02 27 TRACEPKT[13] ETM_TPKT13 28 TRACEPKT[1] ETM_TPKT01 29 TRACEPKT[12] ETM_TPKT12 30 TRACEPKT[0] ETM_TPKT00 31 TRACEPKT[11] ETM_TPKT11 32 TRACESYNC ETM_TSYNC 33 TRACEPKT[10] ETM_TPKT10 34 PIPESTAT[2] ETM_PSTAT2 35 TRACEPKT[9] ETM_TPKT09 36 PIPESTAT[1] ETM_PSTAT1 37 TRACEPKT[8] ETM_TPKT08 38 PIPESTAT[0] ETM_PSTAT0

Note: The AMP Mictor connector has four additional through-hole-pins in the center which have to be grounded for proper operation of the trace port! For the PCB layout it is recommended to have the lines for the ETM signals as short as possible (the signal delay should be < 100ps). The length of the lines should be equal to avoid different signal delays. To improve signal quality, matching resistors can be placed in the signal lines (located as close as pos-sible to the chip pins (<10mm)) to match the output impedance of the chip signal driver with the PCB trace impedance.

http://www.arm.com/



2.15 Vectored Interrupt Controller

The Vectored Interrupt Controller (VIC) supports 32 interrupt sources, whereas 16 can be vectored. The interrupt priority and the type of interrupt, IRQ or Fast IRQ, are configurable. All Interrupts can be masked. Some of the Interrupts represent the result of a logical OR of up to 32 single interrupts of a function block. Hence the Interrupt service routine may have to check further registers to determine the actual source of an interrupt (e.g. resolving the GPIO interrupt to the GPIO input that caused it). The following table shows the different interrupt sources: Interrupt Source Standard Use Remark 0 Reserved for Software Interrupt ARM standard configuration 1 Timer / Counter 0 Real-time operating system timer Timer / counter interrupt from GPIO module 2 Timer / Counter 1 Timer / counter interrupt from GPIO module 3 Timer / Counter 2 Timer / counter interrupt from GPIO module 4 System Time nanoseconds compare Configurable, e.g. ‘1-second-IRQ’ 5 System Time seconds compare Windows CE Configurable, e.g. ‘1-day-IRQ’ 6 GPIO31 External interrupt from GPIO31 7 Watchdog Watchdog expired 8 UART0 general diagnostic port 9 UART1 10 UART2 11 USB USB Interface 12 SPI0, SPI1 Common Int. for SPI 0 and SPI 1 Interface 13 I2C I2C Interface 14 n/a Reserved 15 HOST Dual port memory and Extension Bus 16 GPIO GPIO 0-30 17 XPEC0 Communication channel 0 / XP_IRQ(11:0) 18 XPEC1 Communication channel 1 / XP_IRQ(11:0) 19 n/a Reserved 20 n/a Reserved 21 SYNC0 Synchronization channel 0 / XP_IRQ(15:12) 22 SYNC1 Synchronization channel 1 / XP_IRQ(15:12) 23 n/a Reserved 24 n/a Reserved 25 PHY0 / PHY1 Internal Phy 0 or Phy 1 26 n/a Reserved 27 DMA Controller Common Interrupt for all four DMA channels28 TRIGGER_LT Real-time Ethernet protocols Real-Time-Ethernet Trigger Latch from XC 29 Timer / Counter 3 Timer / counter interrupt from GPIO module 30 Timer / Counter 4 Timer / counter interrupt from GPIO module 31 n/a Reserved IRQ Table, netX50



The Vectored Interrupt Controller (VIC) provides a software interface to the interrupt system. In an ARM system, two levels of interrupts are available: • Fast Interrupt Request (FIQ) for fast, low latency interrupt handling • Interrupt Request (IRQ) for more general interrupts. Generally, only one single FIQ source is used at a time in a system, to provide a true low-latency inter-rupt. This has the following benefits: • The interrupt service routine can be executed directly without having to determine the source of the

interrupt. • Interrupt latency is reduced. The banked registers available for FIQ interrupts can be used more

efficiently, because a context save is not required. There are 32 interrupt lines. The VIC uses one bit position for each different interrupt source. The soft-ware can control each request line to generate software interrupts. There are 16 vectored interrupts. These interrupts can only generate an IRQ interrupt. The vectored and non-vectored IRQ interrupts provide an address for an Interrupt Service Routine (ISR). Reading from the vector interrupt address register, VICVectAddr, provides the address of the ISR, and updates the interrupt priority hardware that masks out the current and any lower priority interrupt requests. Writ-ing to the VICVectAddr register, indicates to the interrupt priority hardware that the current interrupt is serviced, allowing lower priority interrupts to become active. The FIQ interrupt has the highest priority, followed by interrupt vector 0 to interrupt vector 15. Non-vectored IRQ interrupts have the lowest priority. A programmed interrupt request allows to generate an interrupt under software control. This register is typically used to downgrade an FIQ interrupt to an IRQ interrupt. The block diagram on the following page shows an overview of the VIC. Note: The priority of the FIQ over IRQ is set by the ARM. The VIC can raise both an FIQ and an IRQ at the same time. The VIC is compatible to ARMPrimeCell VIC (PL190), hence appropriate documentation from ARM should also be consulted.



Block diagram of the Vectored Interrupt Controller

2.15.1 Interrupt generation

Interrupt request generation For generation of FIQStatus[31:0] and IRQStatus[31:0], the interrupt requests from the peripherals are received and combined with the software interrupt requests. Then any undesired interrupt requests are masked out and the results are either routed to FIQStatus[31:0] or IRQStatus[31:0] (see block diagram). Non-vectored FIQ interrupt (nVICFIQ) generation By combining FIQStatus[31:0] (see block diagram) the non-vectored FIQ (nVICFIQ) which is connected to the ARM CPU, is generated. Non-vectored IRQ interrupt generation By combining IRQStatus[31:0] (see block diagram) the non-vectored IRQ is generated. This signal is used as input of the Interrupt Priority Logic. Vectored interrupt generation There are 16 vectored interrupt blocks which generate 16 vectored interrupt signals (VectIRQ0-15). The vectored interrupt blocks receive the IRQStatus[31:0] (Interrupt Requests) and set the VectIRQx if the following conditions are met: • the selected interrupt is active • the selected interrupt is currently highest requesting interrupt • the selected interrupt is enabled in the vector control register (VICIntCntl[0-15]) Software interrupts The software can control the source interrupt lines to generate software interrupts. These interrupts are generated before interrupt masking, in the same way as external source interrupts. Software interrupts



are cleared by writing to the software interrupt clear register, VICSoftIntClear (see Software interrupt clear register, VICSoftIntClear). This is normally done at the end of the interrupt service routine.

2.15.2 Interrupt priority logic

The interrupt priority block prioritizes the following requests: • Non-vectored interrupt requests • vectored interrupt requests The highest-priority request generates an IRQ interrupt if the interrupt is not currently being serviced. The FIQ interrupt has the highest priority (outside the Interrupt priority logic), followed by interrupt vector 0 to interrupt vector 15. non-vectored IRQ interrupts have the lowest priority.

2.15.3 Interrupt flow sequence

Vectored interrupt flow sequence: The following procedure shows the sequence for the vectored interrupt flow: • An interrupt occurs. • The ARM processor branches to either the IRQ or FIQ interrupt vector. • If the interrupt is an IRQ, read the VICVectAddr register and branch to the interrupt service routine.

This can be done using an LDR PC instruction. Reading the VICVectorAddr register updates the hardware priority register of the interrupt controller.

• Stack the workspace so that IRQ interrupts can be re-enabled. • Enable the IRQ interrupts so that a higher priority can be serviced. • Execute the Interrupt Service Routine (ISR). • Clear the requesting interrupt in the peripheral, or write to the VICSoftIntClear register if the request

was generated by a software interrupt. • Disable the interrupts and restore the workspace. • Write to the VICVectAddr register. This clears the respective interrupt in the internal interrupt priority

hardware. • Return from the interrupt. This re-enables the interrupts. Simple interrupt flow: The following procedure shows how you can use the interrupt controller without using vectored inter-rupts or the interrupt priority hardware. For example, you can use it for debugging. • An interrupt occurs. • Branch to IRQ or FIQ interrupt vector. • Branch to the interrupt handler. • Interrogate the VICIRQ Status register to determine which source generated the interrupt, and pri-

oritize the interrupts if there are multiple active interrupt sources. This takes a number of instructions to compute.

• Branch to the correct ISR. • Execute the ISR. • Clear the interrupt. If the request was generated by a software interrupt, the VICSoftIntClear register

must be written to. Check the VICIRQ Status register to ensure that no other interrupt is active. If there is an active request go to Step 4 (Interrogate …).

• Return from the interrupt. Note: If the simple flow is used, you must not read or write to the VICVectorAddr register.



2.16 DMA Controller

The netX50 is equipped with a DMA Controller that provides the following features: • ARM DMAC software and register compatible • 1 AHBL (32 -Bit) master port, for DMA transfer and list operations • 1 AHBL (32 -Bit) slave port, for programming interface • 4 DMA channels with separate linked lists • 4 Dword (32 -Bit) FIFO per channel • Linked list operation support on each channel • Incrementing or non-incrementing addressing for source and destination (support FIFO read and

write). • Software programmable DMA channel priority strategy. Hardware priority (0 highest, 3 lowest) or

priority lists (last served channel gets new lowest priority). • Programmable burst size • Memory-to-memory, memory-to-peripheral, peripheral-to-memory and peripheral-to-peripheral DMA

transfers. • DMAC or peripheral flow control. Support peripheral DMA flow control signals (request, last burst ). • Error and finish interrupt generation • Interrupt masking, clear interrupt • 32-, 16- and 8-Bit support for source and destination in all combinations. • Hardware DMA channels priority. Each DMA channel has a specific hardware priority. DMA channel

0 has the highest priority and channel 3 has the lowest priority. • Programmable Interrupt capabilities



2.16.1 Functional Description

The following chapter provides a detailed description of the DMA controller and its features. The 4 channel DMA controller supports the following transactions in the netX50: • Peripheral to memory transfer • Memory to peripheral transfer • Peripheral to peripheral transfer • Memory to memory transfer

Internal structure of the DMA controller

Each channel supports a unidirectional up to 32-Bit DMA transfer for a single source and destination address, hence a bidirectional transfer requires one stream for transmitting and a second stream for receiving. The source and destination address can either be a memory region or a peripheral device of the netX50. The default bus width is 32-bit. Source and destination of transfers can have different widths, and can be the same width or narrower than the physical bus width. The DMA Controller packs or unpacks data according to the programmed parameters. The DMA Controller supports little-endian addressing only. Internally, the DMAC treats all data as a stream of bytes instead of 16-bit or 32-bit quantities.



Note: To avoid byte swapping of the data always address the peripheral interfaces in 32-bit mode. Source width

Destination width

Source transfer

Source data

Destination transfer

Destination data

8 8 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24]

21 43 65 87

1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24]

21212121 43434343 65656565 87878787

8 16 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24]

21 43 65 87

1/[15:0] 2/[31:16]

43214321 87658765

8 32 1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24]

21 43 65 87

1/[31:0] 87654321

16 8 1/[7:0] 1/[15:8] 2/[23:16] 2/[31:24]

21 43 65 87

1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24]

21212121 43434343 65656565 87878787

16 16 1/[7:0] 1/[15:8] 2/[23:16] 2/[31:24]

21 43 65 87

1/[15:0] 2/[31:16]

43214321 87658765

16 32 1/[7:0] 1/[15:8] 2/[23:16] 2/[31:24]

21 43 65 87

1/[31:0] 87654321

32 8 1/[7:0] 1/[15:8] 1/[23:16] 1/[31:24]

21 43 65 87

1/[7:0] 2/[15:8] 3/[23:16] 4/[31:24]

21212121 43434343 65656565 87878787

32 16 1/[7:0] 1/[15:8] 1/[23:16] 1/[31:24]

21 43 65 87

1/[15:0] 2/[31:16]

43214321 87658765

32 32 1/[7:0] 1/[15:8] 1/[23:16] 1/[31:24]

21 43 65 87

1/[31:0] 87654321

DMA controllers data packing respectively unpacking depending on programmed mode

The DMA channel priority is fixed. DMA channel 0 has the highest priority and DMA channel 3 has the lowest. If a channel with a higher priority is activated, while the DMA controller is currently transferring data for a lower priority channel, the number of transfers delegated to the master interface by the lower priority channel, are completed first before switching over to transfer data for the higher priority channel. The netX50 has four AHB masters in total (ARM966, HIF, DMA controller and XC unit). Due to the netX50 bus matrix all masters can operate in parallel, if no shared resources are used. If these masters get in conflict by accessing the same resources (e.g. external memory), the bus matrix solves this con-flict by a fix priority for each master. The host interface has the highest priority, followed by the XC unit, the ARM966 and the DMA controller (lowest priority). The following recommendations should be considered, to reduce latency and improve performance of DMA Transfers:



• Reduce conflicts in the first place by separating software of the system processors (ARM966 and XC) running in different memory areas.

• If possible, use separate memory areas for data storage and liked list information. • All memory transactions should be 32 bits wide to improve bus efficiency. Internal structure of the DMA controller interrupts

The DMA controller generates a common interrupt output which is the result of a logical OR of the indi-vidual interrupt requests. The vector interrupt controller (VIC) again generates a logical OR of all peripherals and provides mask-ing the DMA interrupt for the fast interrupt request (FIQ) and the general interrupt request (IRQ) of the ARM CPU of each interrupt source. For further information, refer to the register description of the DMA controller and the vector interrupt controller.



2.17 Multiplex Matrix

While the netX500 already raised the challenge of making a large number of peripheral interfaces ac-cessible through a necessarily limited number of physical pins, this task has tightened with the netX50, due to its reduced chip size.and hence lower pin count. To provide more flexibility in the use of the pe-ripheral resources, the netX50 is equipped with a Multiplex I/O matrix. This matrix connects to the “outside world” via a total of 40 MMIO pins (Mutliplex Matrix Input / Output). On the chip side, a total of 148 signals are connected to the matrix, that can be routed to any of the MMIOs by setting the Configu-ratin Registers of the MMIOs accordingly. The following figure provides an overview of the Multiplex Matrix: Multiplex matrix

By default (after reset or power on), MMIOs 0 -31 are mapped to GPIO 0 -31 and MMIOs 32-35 are mapped to UART0 (to allow the serial boot mode option to be used with UART0). A complete list of all MMIO signals can be found in chapter 4.5 , Multiplex Matrix Signals. Each MMIO pin has a corresponding configuration register, that allows to map any of the 148 internal signals to this pin. Further, input and output signals can be inverted independently. This also allows to

netX50

Ethernet status LEDs

Multiplexmatrix

2x XC channel

2x PHY status

2x MII

32x GPIO

8x PIO

3x UART

SPI

I2C

CCD-Controller

Misc

MMIO 0

MMIO 1

MMIO 2

MMIO 39

serial Flash

Realtime Ethernet Synchronisation

CCD Sensor

MMIO Configuration

Module

40 MMIOs

148

inte

rnal

con

nect

ions



map an internal signal to more than one MMIO pin. If the internal signal is an output signal, then this signal is simply replicated on the mapped MMIO Outputs. If the internal signal is an input signal, then the level of this signal is the result of a logical OR of all MMIOs that are mapped to this signal. As some interfaces have or may have certain timing requirements that can not be met by the Multiplex matrix, some of the MMIO pins are directly shared with those interfaces and allow a direct signal routing (like with the netX500). This applies to the ETM interface which always uses MMIO pins 17 – 39 when used, as well as the Ethernet PHYs when in Fiber optic mode (using MMIO 32 -35 (channel 0) and 36-39 (channel 1) and some XMAC signals (TX, ECLK and FBCLK). However for the XMAC signals this is optional (in common applications, they are routed through the Multiplex Matrix).



2.18 IO-Link Controller

2.18.1 Introduction

IO-Link is a new communication standard interface for sensors and actuators. IO-Link allows an inex-pensive point-to-point connection between sensor/actuator and the I/O assembly for the "last meter to the process". IO-Link allows Diagnosis and parameter information to be exchanged between sen-sor/actuator and the automation system in addition to the measurement signal through the specified communication mechanism, maximizing the performance of state-of-the-art intelligent sensors and ac-tuators. The “IO-Link working group” under the umbrella of PROFIBUS International (PI) has initiated the speci-fication for a “fieldbus-independent” communication interface for intelligent sensors and actuators in industrial automation. This document is based on version 0.96 of the IO-Link specification, which is still stable regarding hardware requirements. An IO-Link Interface always uses a point-to-point topology and supports two or three physical wire inter-face (incl. power). It supports the following baud rates: Port baud rates (fCLK) bit time (Tbit) Com1 4800 Baud 208,33 us Com2 38400 Baud 26,04 us Com3 230400 Baud 4,34 us

IO-Link Baud rates

IO-Link was designed as an open interface and can be integrated in all current communication systems in automation.

IO-Link: block diagram of a single port



2.18.2 Typical Application

The netX50 supports up to eight IO-Link ports.

netX50 with 8 IO-Link ports

Highlights of IO-Link: • Dynamical update of sensors parameters by an SPS • Service and online exchange of sensors • Uniform wiring of variable sensors / actuators • Uniform tools for parameterization

netx50 IO-Link master interfacing

Features: • 8 IO-Link ports (master) • TX-buffer size programmable to up to 8 byte • RX-buffer size programmable to up to 4 byte • Programmable interrupt capabilities (frame finished, tx finished, rx finished, wake up finished) • Loop frame transfer mode for continuous transmission of data • Single frame transfer mode for debug and analysis • Automatic wake up generation




The following chapter provides a detailed description of modes and features of IO-Link interface. For detailed IO-Link standard description, refer to the IO-Link communication specification (Profibus user organization PNO, version 0.96. October 2006) The IO-Link specification defines two kinds of physical interfaces. After power on, the master port is a digital input by default.

Physics 1

2-wire system, power line and communication on two wires (phy 1)

Phy. 1 connection block

Physics 2

3-wire system (phy 2), power L+, L- separated from communication wire C/Q

Phy. 2 connection block

IO-Link port mapping

Each IO-Link port uses four consecutive GPIO ports on the netx50. These ports control the physical driver including wake up and current control features.

Example connection diagram: netX50 to IO-Link node



The following table defines the coding of external IO-Link node logic for generation of wake up pulses. wake_up Txd Wake up request high Wake up request low 1 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0

IO-Link wake up generation

IO-Link node in detail

The wake up current (IQwu) is a generated current event from master device. The level of the event depends on the level of the C/Q line. Note: The IO-Link signals are shared with the GPIO signals, whereas each IO-Link channel uses four con-secutive GPIO signals (channel 0 : GPIO 0 -3, channel 1: GPIO 4-7, etc.). In order to use the netX50 IO-Link signals, the corresponding GPIOs must be routed to MMIOs by using the Multiplex Matrix (see chapter 2.17), and must be configured to IO-Link mode.



2.18.4 IO-Link datagram

The IO-Link has a UART like, half-duplex serial wire datagram: 1 start bit 8 data bits

Bit0 … Bit 7 1 parity bit 1 stop bit

IO-Link datagram format

IO-Link Frame Structure

Netx50 always operates as IO-Link master. The IO-Link protocol between master and slave device is frame based. The IO-Link frame consists of a master frame and slave frame. The serial wire is bidirec-tional and always driven by the master first followed by the slave.

octet 1 octet 2 ... octet n

T1T b8 T a

octet 1 octet 2 ... octet m

T2

T f

master frame slave frame

IO-Link frame next IO-Link frame

T idleT cycle

IO-Link frame structure

Abbr. Description Equation T bit period of one bit transfer T b8 period of one octet 8 * T bit T f period of IO-Link frame n * T b8 + T a + m * T b8 + (m-1) * T 2 + (n-1) * T 1 T 1 delay between two master octet's 0 T bit T 2 slave pause max. 3 T bit T a delay between master frame and

slave frame min. 1Tbit max. 10*T bit

T cyc cycle time typical 2ms - 5ms

Timing Definition

Notes: • Number (n) of octets in a master frame: max. 5 • Number (m) of octets in a slave frame: max. 4 • The IO-Link frame has max. 6 octets • Each IO-Link port processes the frame buffer in a cycle time T cyc.

Bit Coding

On the serial wire, IO-Link has a Non Return to Zero (NRZ) coding. A logical value of 1 corresponds to 24V voltage on a link port (voltage between L+ and C/Q). A logical value of 0 corresponds to 0V voltage on a link port.

Sending data

The netX50 ARM system and all modules of the system do not support big-endian format. However, to handle the big-endian data format (defined in the IO-Link communication specification) the IO-Link con-troller has a roll over feature. Data is sent in the following order by default:



IO-Link data mapping

IO-Link default sending data order

If the tx_lsb_first_r bit in the iolink_cfg register is set, the data will sent in the following order:

time

Byte 3Byte 2Byte 1Byte 0 Byte 4 Byte 5 Byte 6 Byte 7

IO-Link optional data sending order

Receiving data

The received data also formatted in the big-endian format. The IO-Link interface adapt the receive data to little-endian format automatically!

IO-Link data receiving order



2.19 CCD-Sensor Interface

The CCD interface unit collects the colour or brightness values from a CCD sensor byte stream. All CCD formats with single pixel information in one to four bytes like RGB 565, RGB 555, RGB 444x or YCbCr are supported. The CCD Controller can sample all pixel clocks up to 50 MHz. The collected col-our or brightness values can be transferred via DMA Controller to the system memory. Feature list: • Resolution up to 65536 x 65536 pixel • Pixel clock up to 50 MHz • Sampling related to rising or falling edge of pixel clock (one system clock before or up to 14 system

clocks after edge of pixel clock) • Brightness monitoring via counter for brightness control • Picture cropping • Three parallel pixel FIFOs. • Polarity of line sync and frame sync programmable by Multiplex matrix (different module)

CCD Controller block diagram




Typical CCD Sensor Timing and Signals

The CCD sensor interface contains the following signals: pixel clock, data byte, frame and line valid. The picture is transferred byte by byte, while the frame valid is active. The horizontal bytes of the picture are transferred, while the line valid is active.

Sensor data timing

Data Sampling

The sensor data und pixel clock sampling of the CCD data is done by the 100 MHz system clock. The pixel clock detection can be configured for negative or positive edge detection. The pixel data byte can be sampled at the detected edge, one to fourteen system clock cycles after the detected edge or one system cycle before the detected edge depending on the external CCD sensor.

Sampling example

(pixel data byte is sampled one clock cycle after the detection of a negative pixel clock edge).



Picture Cropping

Frame valid and line valid signals are controlling vertical and horizontal counters that define the position of every incoming pixel in the frame. Using these counters and programmable start and stop position registers, the CCD Controller can cut out a section of a picture. The CCD Controller then puts only pixel bytes in the sample FIFO that match horizontal and vertical start and stop conditions.

picture datafrom sensor

vertical stop

vertical start

horizontal start horizontal stop

cropped section of thepicture

00

Picture cropping

Brightness Control

Common CCD sensors can be adjusted for brightness sensitivity during runtime. This becomes neces-sary if the light conditions are changing. The CCD Controller adds up the values of all bytes (RGB) in the cutted section of the picture. This gives an approximation of the average illumination, which can be used by the system CPU to adjust the sensor. Notes: The brightness register (CCDC_BRIGHTNESS) is reset with the rising edge of frame valid. The soft-ware should read the value after the end of the cut picture section but before the next rising edge of frame valid. The CCD Controller adds incoming pixel data before distributing them to different FIFOs. Thus, this functionality will work fine with formats like RGB, but not with formats, where the sensor already calcu-lated the luminance and chrominance differences (e.g. YCrCb).



Pixel Collecting

The sampled byte data of the CCD sensor can be sorted by the CCD Controller to three byte oriented FIFOs. With these FIFOs, the most common protocols can be handled, as there are:

• YCbCr

• Swapped CrCb

• Swapped YC

• Swapped CrCb, YC

• RGB 565

• RGB 555

• RGB 444x

• RGB x444

The examples of RGB 565 and YCbCr illustrate the technical requirements of the pixel collect module. In RGB 565, the colours red, green, and blue are coded in two bytes per pixel. The LSBs of the color information are not transferred.

RGB 565

In YCbCr format, the information of one pixel is transferred with every fourth byte for Cb (blue chroma difference) and Cr (red chroma difference), while the information for Y (luminance) is transferred with every second byte.

YCbCr (no swap)

To allow maximum flexibility in programming, the collection of incoming video data to three different FIFOs, first of all the incoming data, is stored in four byte-registers. These register values are kept for at least four clock cycles, until this data is distributed to the FIFOs of the CCD Controller. Each FIFO of the CCD Controller can select up to four bytes from these registers. Each of these FIFO entries has an enable bit, a start position, and an AND-mask. This results in 3x4=12 enable bits, start positions, and AND-masks in registers CCDC_BYTE_0_POS, CCDC_BYTE_1_POS, and CCDC_BYTE_2_POS. Each enable bit defines, if a byte is written to the appropriate FIFO in one of four subsequent clock cycles. Start bit position and AND-mask allow the selection of any group of bits to be the FIFO entry. The following picture illustrates the functionality of this mechanism.



Byte 1 Byte 2

red green blue

r7

r6

r5

r4

r3

g7

g6

g5

g4

g3

g2

b7

b6

b5

b4

b3

Byte 3 Byte 4

red green blue

r7

r6

r5

r4

r3

g7

g6

g5

g4

g3

g2

b7

b6

b5

b4

b3

Pixel 1 Pixel 2

FIFO 1(for red)

FIFO 3(for blue)

FIFO 2(for green)

RGB 565 collecting

DMA Data Transfer

Each FIFO collects the bytes to Dwords (32 bit) and has a depth of two Dwords. The system DMA Con-troller (see DMA Controller documentation) can access each FIFO at different system addresses and gets the appropriate next signals used for automatic flow control. The DMA Controller should be programmed to transfer one complete picture. When the picture is fin-ished, the ARM system CPU gets a finish interrupt and can restart the DMA controller.

FIFO Reset

In case of incorrectly configured DMA or disabled DMA controller the FIFOs will overflow and set an overflow bit in the CCDC_CONFIG register.The system CPU can reset the FIFO by setting and reset-ting a reset bit in the same register. Each FIFO can be reset separately.



External Interface

The external interface of the CCD sensor to the CCD Controller contains an eight bit data bus, a pixel clock, a frame valid and a line valid signal.

CCD sensorCCD

Controller

netX

8data

pixel_clock

frame_valid

line_valid

External interface

Note: In order to use the CCD Sensor Interface signals, they must be routed to MMIOs by using the Multiplex Matrix (see chapter 2.17)



2.20 UART

The three UARTs are 16550-compliant with 16 bytes transmit and receive FIFOs. They can be configured to support speeds up to 3.125 MBaud. The interface supports configurations of: • five, six, seven, or eight data-bit transfers • one or two stop bits • even, odd, or no parity • IrDA SIR encoding and decoding The request-to-send (RTS) and clear-to-send (CTS) modem control signals also are available with the interface for hardware flow control. Special features like stick parity and adjustable FIFO trigger level are implemented. UART0 is commonly used as diagnostic port, it is hence not recommended to use this port for other purposes, especially when using loadable firmware from Hilscher. Block diagram of the UART The ARM CPU reads and writes data and control/status information via the peripheral bus interface. The UART module can generate four individually-maskable interrupts which are combined to a single interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. If a framing, parity or break error occurs during reception, the appropriate error bit is set, and is stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and FIFO data is prevented from being overwritten. Baud rate generator The baud rate generator contains free-running counters which generate the internal Baud16 or IrLP-Baud16 signal. Baud16 or IrLPBaud16 provide timing information for UART transmit and receive control. Baud16 is a stream of pulses with a width of 10 ns and a frequency of sixteen times the baud rate. Transmit FIFO The transmit FIFO is an 8-bit wide, 16-bit depth, first-in, first-out memory buffer. CPU data written across the bus interface is stored in the FIFO until read out by the transmit logic. The transmit FIFO can be disabled to act as a one-byte holding register.



Receive FIFO The receive FIFO is an 11-bit wide, 16-bit depth, first-in, first-out memory buffer. Received data, and corresponding error bits, are stored in the receive FIFO by the receive logic until read out by the CPU across the bus interface. The FIFO can be disabled to act as a one-byte holding register. Transmitter The transmit logic performs parallel-to-serial conversion on the data read from the transmit FIFO. Con-trol logic outputs the serial bit stream begins with a start bit, data bits, least significant bit (LSB) first, followed by parity bit, and then stop bits according to the programmed configuration in control registers. Receiver The receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. Parity, frame error checking and line break detection are also performed, and the data with associated parity, framing and break error bits is written to the receive FIFO. Interrupt logic Four individual maskable active HIGH interrupts are generated in the UART module and are combined to one interrupt output. This output is generated as an OR function of the individual interrupt requests. The single combined interrupt is used with the system interrupt controller that provides another level of masking on a per-peripheral basis. This allows use of modular device drivers which will always know where to find the interrupt source control register bits. IrDA SIR Endec The Transmitter and Receiver block contain an IrDA SIR protocol Endec. The SIR protocol Endec can be enabled for serial communication via signals nSIROUT and SIRIN to an infrared transducer instead of using the signals TXD and RXD. The SIR protocol Endec can both receive and transmit, but it is half-duplex only, so it cannot receive while transmitting, or vice versa. The SIR transmit encoder modulates the Non Return-to-Zero (NRZ) transmit bit stream. The IrDA SIR physical layer specifies use of a Return To Zero, Inverted (RZI) modulation scheme which represents logic 0 as an infrared light pulse. The modulated output pulse stream is transmitted to an external output driver and infrared Light Emitting Diode (LED). In normal mode the transmitted pulse width is specified as three times the period of the internal x16 clock (Baud16), that is, 3 / 16 of a bit period. Low-power mode of the transmit infrared pulse is set to 3 times the period of the internal generated IrLPBaud16 signal. The frequency of IrLPBaud16 signal is set by writing the appropriate divisor value to UARTILPR. The active low encoder output is normally LOW for the marking state (no light pulse). The encoder out-puts a high pulse to generate an infrared light pulse representing a logic 0 or spacing state. The SIR receive decoder demodulates the return-to-zero bit stream from the infrared detector and out-puts the received NRZ serial bit stream to the internal logic. The decoder input is normally HIGH (marking state) in the idle state (the transmit encoder output has the opposite polarity to the decoder input). A start bit is detected when the decoder input is LOW. Regardless of being in normal or low-power mode, a start bit is deemed valid if the decoder is still LOW, one period of IrLPBaud16 after the LOW was first detected.



UART communication Data received or transmitted is stored in two 16-byte FIFOs, the receive FIFO has an extra three bits per character for status information. For transmission, data is written into the transmit FIFO. This causes a data frame to start transmitting with the parameters indicated in UARTLCR. Data continues to be transmitted until there is no data left in the transmit FIFO. The BUSY signal goes HIGH as soon as data is written to the transmit FIFO (that is, the FIFO is non-empty) and remains asserted HIGH while data is being transmitted. BUSY is ne-gated only when the transmit FIFO is empty, and the last character has been transmitted from the shift register, including the stop bits. BUSY can be asserted HIGH even though the UART module may no longer be enabled. When the receiver is idle (RXD continuously 1, in the marking state) and a LOW is detected on the data input (a start bit has been received), the receive counter, with the clock enabled by Baud16, begins running and data is sampled on the eighth cycle of that counter (half way through a bit period). The start bit is valid if RXD is still LOW on the eighth cycle of Baud16, otherwise a false start bit is de-tected and it is ignored. If the start bit was valid, successive data bits are sampled on every 16th cycle of Baud16 (that is, one bit period later) according to the programmed length of the data characters. The parity bit is then checked if parity mode was enabled. Lastly, a valid stop bit is confirmed if RXD is HIGH, otherwise a framing error has occurred. When a full word has been received, the data is stored in the receive FIFO, with any error bits associated with that word. Error bits The three error bits are stored in bits 10:8 of the receive FIFO, and are associated to a particular char-acter. There is an additional error which indicates an overrun error but it is not associated with a particular character in the receive FIFO. The overrun error is set when the FIFO is full and the next character has been completely received in the shift register. The data in the shift register is overwritten but it is not written into the FIFO. FIFO bits 7:0 : received data FIFO bit 8 : framing error FIFO bit 9 : parity error FIFO bit 10 : break error Disabling the FIFOs Additionally, it is possible to disable the FIFOs. In this case, transmit and receive sides of the UART module have 1-byte holding registers (the bottom entry of the FIFOs). The overrun bit is set when a word has been received and the previous one was not yet read. Note: In order to use the UART 1 and UART 2 signals, they must be routed to MMIOs by using the Multiplex Matrix (see chapter 2.17). UART 0 is also routed to MMIOs, however there is a default routing on power up (see chapter 4.5 , Multiplex matrix signals).



2.21 USB

The integrated USB V 1.1 interface is fully compliant with the USB specification. It supports both full and low speed transfers and can act as a host or device. The USB unit includes an integrated transceiver and provides eight pipes. Their direction, transfer type and FIFO size can be configured at run-time. All low-level USB operations are realized in hardware. The software only has to manage the enumera-tion process and data transfer from and to the FIFOs.



2.22 I2C Interface

2.22.1 Overview

The I2C interface is a simple 2-wire interface providing a clock and a data line. Transfers are serial, 8-bit oriented and bidirectional between master and slaves. Each device connected to the I2C interface is addressable by a unique address.

Module Features

The netX50 I2C unit has full master and slave functionality. It provides SCL clock rates from 50 kHz up to 3.4 MHz. For high efficient data exchange, the module includes a standard ARM DMA interface together with a 16-byte master data FIFO and a 16-byte slave data FIFO. It provides interrupts for the most important events like slave selection, FIFO requests and errors, I2C bus collision detection and end-of-transfer. To keep the main processor load low, there is a state machine implemented, which can run complex I2C sequences like acknowledge polling or long data transfers. I2C features like 7- and 10-bit slave addressing and multi master arbitration are supported by this module. Note: This unit is not compatible with the netX100/netX500 I2C unit!

Typical Applications

There are many I2C devices on the market today. Typical are low bandwidth devices as: • EEPROMs • display controllers • card readers • various types of sensors • microcontrollers • various types of ICs with I2C configuration channel




For detailed I2C standard description, view Philips I2C-Bus specification (Version 2.1, 01.2001). The following section gives a brief overview. I2C devices are either master only, slave only or master-and-slave devices.The netX50 I2C unit is a master-and-slave device.

2.22.2.1 Block diagram

I2C module block diagram



2.22.2.2 I2C signals The I2C interface defines only two signals: • SCL: Serial Clock • SDA: Serial Data • To avoid signal driving conflicts, both signals are never actively driven to high level (high level is real-ized by (internal) pad pull-up resistors.

2.22.2.3 I2C Signal Conditions A transfer is initiated by a master with a start condition (START) or a repeated start condition (rSTART). The start condition is represented by a falling edge of SDA while SCL is high. At the end of a transfer, a stop condition (STOP) must be done by the master. The stop condition is represented by a rising edge of SDA while SCL is high. During data transfers, SDA is valid and must not change, while SCL is high.

I2Csignal conditions states

2.22.2.4 I2C Transfers An I2C transfer always transmits eight bits of data (MSB first) followed by an active low acknowledge bit generated by the receiving device. The first transferred byte after (r)START is always generated by a master. It contains a 7-bit slave ad-dress and an nWrite/Read bit, which indicates the transfer direction (0: write transfer master to slave, 1: read transfer master from slave). Every I2C slave device has its own slave ID. If any ID matches the address generated by the master during the first byte after (r)START, the appropriate slave acknowledges the first byte. For detailed I2C address range specification, see Philips I2C-Bus specification.

I2C 1 byte transfer



2.22.2.5 I2C Acknowledge Handling The low active acknowledge bit is always generated by the receiving device (during write transfers by the slave, during read transfers by the master) after each transferred byte. If a slave did not acknowledge a byte, the master has to generate either (r)START or STOP.

I2C write transfer

After the last byte of a read transfer the master (as receiver) must not generate an acknowledge to sign the end of the transfer to the slave. Otherwise the slave will continue sending data and produce a bus error.

I2C read transfer

Note: After an acknowledged (r)START with set read bit, at least one byte must be transferred from slave to master. In case of transfer direction change an rSTART condition must be issued.

I2C transfer with direction change



2.22.2.6 I2C 10-bit Addressing The Philips I2C specification describes an extended 10-bit addressing mode that is entered by a 2-byte start sequence. The first byte after (r)START contains a 7-bit address matching the reserved pattern “11110XX”, where “XX” are the both MSB bits of the requested 10-bit address. Note: For detailed I2C address ranges and pattern, view Philips I2C specification. If a 10-bit slave device is on the I2C-bus with appropriate MSB address bits, it will acknowledge the first byte. The master will then transfer the second start byte containing the lower eight address bits.

I2C 10-bit addressing

As the second byte of a 10-bit start sequence is always transferred from master to slave, the read-bit in the first transferred byte must always be 0. A read transfer from a 10-bit addressed slave is initiated by a write start sequence followed by an rSTART and the first start byte containing the 10-bit address pattern, the slave address MSBs and the read-bit set to 1. The second start byte will not be transferred again.

I2C initializing a read transfer from a 10-bit address slave

Various types of transfers can be combined as described in Philips I2C specification. E.g. a write data may be inserted before restarting in 0

2.22.2.7 I2C General Call I2C general call functionality is provided by the reserved 7-bit address pattern “0000000” transferred after START initiating a write transfer (read-bit set to 0). Note: For detailed I2C address ranges and pattern, view Philips I2C specification.



2.23 SPI

2.23.1 Overview

Beside the I2C, the SPI is the most common serial interface for peripheries and memory components. SPI (Serial Peripheral Interface) is a full-duplex 4-wire interface defined by Motorola. Transfers are se-rial, typically 8-bit oriented and bidirectional between master and slaves. Slave devices are selected by a Chip Select signal. The netX50 provides two identical SPI units with the following features:

• Full master and slave functionality.

• SPI_CLK clock rates up to:

o 50MHz in master mode

o 33 MHz in slave mode.

• All four Motorola SPI modes supported in master and slave mode:

o Clock polarity high or low

o Clock phase 0 or 1.

• Flexible data frame size from 4 to 16bit data words.

• 16-word deep FIFO for transmit data.

• 16-word deep FIFO for receive data.

• IRQ generation FIFO interaction.

• DMA interface for receive and transmit data to minimize system CPU load.

• Input signal oversampling and filtering for hazard suppression.

• Extended chip select controlling:

o Three individual external chip selects (may be demultiplexed externally to 8 signals)

o Static or dynamic chip select handling configurable.

• netX100 compatibility mode and register set.

Note: While the signals of SPI unit 0 are directly available on dedicated pins (except Chip Select 2), the sig-nals of SPI unit 1 and the CS2 of SPI unit 0 must be routed to MMIOs, using the Multiplex matrix (see chapter 2.17) if unit 1 or CS2 of unit 0 is to be used.



2.23.2 Functional description

2.23.2.1 Block diagram

Block diagram of SPI Unit

2.23.2.2 SPI signals The Motorola SPI interface defines four signals:

• Clock signal (SPI_CLK, SPI_SCK)

• Master transmit, slave receive data signal (SPI_MOSI)

• Master receive, slave transmit data signal (SPI_MISO)

• Low active chip select signal (SPI_FSS, SPI_CS_N)

Data transfers are full duplex bidirectional. Data is always serialized MSB first.



2.23.2.3 SPI Transfer Format SPI data transfer is activated by low active chip select signal. SPI signal generation and sampling states and timing can be selected by programmable SPO and SPH. Note: For more flexibility in master mode, chip select can be dynamically generated by the SPI module state machine or can be static, generated by spi_cr1 register bit fss_static.

SPI Clock Polarity (SPO)

SPI clock polarity is the idle state of SPI clock signal SPI_CLK when no data is transferred.

SPI Clock Phase (SPH)

SPI clock phase controls SPI data generation and sample timing. If SPH 0 is selected, data on SPI_MOSI and SPI_MISO is sampled on the first clock edge of SPI_CLK, if SPH 1 is selected sampling is done on the second edge. Data is generated on edge prior.

SPI Frame Format with SPO=0 and SPH=0

Clock idle state is low and data is sampled on the first (rising) edge of any SPI_CLK period. MSB data is generated when chip select is activated. Slave devices need chip select toggling at start of transfer to generate MSB data bit. SPI transfer, SPO=0 and SPH=0


Clock idle state is low and data is sampled on the second (falling) edge of any SPI_CLK period. MSB data is generated on the first (rising) SPI_CLK edge. Slave devices do not need chip select toggling at start of transfer to generate MSB data bit. SPI transfer, SPO=0 and SPH=1

SPI_CLK

SPI_CS_N

MSBSPI_MOSI

SPI_MISO LSB

LSB

MSB

MSB

LSB

LSB

MSB

4 to 16 bit 4 to 16 bit




Clock idle state is high and data is sampled on the first (falling) edge of any SPI_CLK period. MSB data is generated when chip select is activated. Slave devices need chip select toggling at start of transfer to generate MSB data bit. SPI transfer, SPO=1 and SPH=0


Clock idle state is high and data is sampled on the second (rising) edge of any SPI_CLK period. MSB data is generated on the first (falling) SPI_CLK edge. Slave devices do not need chip select toggling at start of transfer to generate MSB data bit. SPI transfer, SPO=1 and SPH=1

2.23.3 Typical Applications

There are many SPI devices on the market today. Typical are low bandwidth devices as:

• Serial FLASHs

• MMC cards

• Various types of sensors

• Microcontroller Interface

The following figures show different possibilities of external SPI interconnection to SPI slave and master devices.

SPI_CLK

SPI_CS_N

MSBSPI_MOSI

SPI_MISO LSB

LSB

MSB

MSB

LSB

LSB

MSB


SPI_CLK

SPI_CS_N

MSBSPI_MOSI

SPI_MISO LSB

LSB

MSB

MSB

LSB

LSB

MSB




Standard external SPI master interconnection

Extended external SPI master interconnection with DMUX

netX50 as SPI slave



2.24 GPIO

The netX50 provides a total of 32 general purpose IOs, which are are shared with the IO-Link interface and are also used as input or output signal along with the internal timers. Using an IO-Link channel, will always use 4 consecutive GPIOs, which are then not available for use in GPIO mode. The GPIOs provide the following features: • Can be programmed individually as input or output, inverted or non inverted • Outputs can be set by individual registers as well as by a common register • Each GPIO can be assigned to a System Timer, to be used as capture input or PWM output • Each GPIO can generate an interrupt Each GPIO has its own configuration register GPIO_CFGi to configure these functions and to read and write the IO individually. All inputs can be read together in the GPIO_IN register, respectively can be written through the GPIO_OUT register. Block diagram showing GPIO functionality



2.25 PIO

The netX50 provides several programmable input / output lines. Each of the 62 PIO signals can be used as simple input or output without any additional features. PIO0 -PIO7 are accessible through the Multi-plex Matrix and usually drive Fieldbus and RT Ethernet status LEDs. The remaining 54 PIOs (PIO32-PIO84) are shared with Host Interface Pins. (PIOs 8 - 31 do not exist in the netX50).

PIO 0-7

The first 8 PIO signals are controlled by three registers: 'PIO_IN - PIO Input Register', 'PIO_OUT - PIO Output Register' and 'PIO_OE - PIO Output Enable Register'. In order to use PIOs 0 – 7, they need to be mapped to MMIO pins'.

PIO 32-85

These programmable input / output pins are multiplexed with the host interface and are hence also ref-erenced as “HIF-PIOs”. When the host interface is switched to 'I/O Mode' , all pins work as normal input / output lines. When the Extension Bus or Dual-Port memory mode is selected, unused interface lines can be used as programmable input / output pins. It is possible to switch each pin between host inter-face operation and programmable input / output pin via the mode registers. The following list shows all netX control registers for programming. For a detailed description of all registers see the 'netX50 Pro-gram Reference Guide'. DPM_ARM_IF_CFG0 This register selects the different operating modes for the host inter

face. The interface may be switched to 'Disable', 'Extension Bus', Dual- Port Memory' or 'IO Mode' operation.

DPM_ARM_IO_DATA0 These data registers set the output data for all HIF-PIOs with enabled DPM_ARM_IO_DATA1 output drivers, respectively contain the sampled input data of all HIF-

PIOs. DPM_ARM_IO_DRV_EN0 The driver enable register controls the output drivers of each pin. When DPM_ARM_IO_DRV_EN1 the Dual-Port memory or Extension Bus function is enabled, the setting

of the driver enable bit is ignored. After power on reset all drivers are disabled.

DPMAS_IO_MODE0 The mode registers allow to configure each pin to either I/O mode or DPMAS_IO_MODE1 Host interface mode. When the 'I/O Mode' is selected in Register

DPM_ARM_IF_CFG0 (switches all pins to I/O mode), the settings of these mode registers have no effect. The mode of each pin can be changed anytime, also during operation. The IN_CONTROL[1:0] flags control the sampling of the input pin signal. Four modes can be selected.

Mode '00' (reset condition) samples all input signal lines shortly after the rising edge of the power on reset signal allowing configuration by external pull-up or pull-down resistors. The firmware can read the input data register after starting.In mode '01' the input latches are always enabled and the data is stored in internal flip flops, clocked by the system clock. When mode '1x' is selected the input flip flops are only enabled when the PIO77 pin has a high (mode 11) or low (mode 10) level. Data will be stored in the input flip flops, controlled by the internally synchronized PIO77 pin.



Power-On-Reset Sampling of PIO 32-85 Pins

After the Power On Reset signal is being released, the state of all 54 host interface pins is sampled and stored in two registers. This provides the possibility to select different device configurations by using pull-down resistors (pins have weak internal pull-ups) and implementing the corresponding configura-tions in the firmware . The following figure shows the power on reset schematic of data sampling. Input sampling during power on reset

Parameter Description Value Dimension tDON Maximum time between deassertion of the Power On Reset Signal

and valid (external) data supplied to the PIOs 11 ms

tDOFF Minimum time between deassertion of the Power On Reset signal and deactivation of (external) data supplied to the PIOs

11.5 ms

Note: The Timing values and the figure above are only relevant when driving data signals from an external data source instead of using (the internal) pull-up or (external) pull-down resistors. In that case, users must take care, that the host interface configuration that might be done by the firmware or the boot loader (DPM boot mode or Extension Bus boot mode) will not collide with the data source connected to the PIOs!



Input Sampling of PIO 32-84 Pins

All input pins are synchronized to the internal system clock. Besides continuous data sampling, it is also possible to enable/disable all input flip flops via the PIO77 pin and initiate data sampling. When this external signal is active, the input flip flops are enabled. The signal will be synchronized to the system clock as well. The following figure shows the input signal delay at the two different sampling modes. Input Sampling and Timing Diagram

Parameter Description Value Dimension tCYC Internal 100 MHz clock cycle 10 ns tsu Input setup time before internal rising clock edge < 1 CYC tDH Hold time after internal rising clock edge < 1 CYC tIN Synchronization delay for input signals until valid internal sampling

data 3…4 CYC



2.26 Ethernet Interface

The netX50 contains two Ethernet MACs with integrated PHYs. They support: • 10Base-T / 100Base-TX • 100Base-FX with external drivers • Auto-Negotiation • Auto-Crossover • Auto-Polarity They are fully compliant with IEEE 802.3 / 802.3u to run the protocols: • PROFINET RT and IRT • Ethernet/IP • Open Modbus on TCP/IP Additional the Ethernet MAC includes special logic to support: • Time synchronization based on IEEE 1588 • Powerlink • EtherCAT • SERCOS-III Basic circuit for netX Ethernet interface (100Base-T, only one channel shown)



With applications that do not make use of the Ethernet interface, the PHY signals must be con-

nected according to the following schematic (power must be supplied and reference resistor must be connected):

Circuit when netX Ethernet interface is not used

netX

PHY0_TXP

PHY0_TXN

PHY0_RXP

1.5V

12.4k

PHY0_RXN

PHY_EXTRES

PHY_ATP

C5

C7PHY_VDDIOATPHY_VDDIOAC

PHY_VDDCAPPHY0_VDDCARTPHY1_VDDCART

3.3V

PHY1_TXP

PHY1_TXN

PHY1_RXP

PHY1_RXN

PHY_VSSATPHY_VSSACPPHY0_VSSAR

PHY0_VSSAT1PHY0_VSSTA2PHY1_VSSAR

PHY1_VSSAT1PHY1_VSSTA2

GND

GND



2.26.1 Real Time Ethernet

Besides standard Ethernet functionality, the netX Ethernet channels also support all current Real Time Ethernet protocols. The different protocols make use of special functionality: POWERLINK uses HUB-Functionality to forward the Ethernet-Telegrams. The access conflicts on the Ethernet are prevented with the help of the protocol stack running on the ARM CPU. To increase per-formance, the xPEC answers a Poll-Request-Telegram immediately with a PollResponse-Telegram, without the interrupt latency that would be encountered, when the ARM CPU would be involved. EtherCAT forwards the Ethernet data immediately from one port to the other and takes out, respectively fills in the local data. Therefore the xMACs have direct connection between each other and have a spe-cial filter function to identify the local data inside Ethernet-Frames. The xPEC is responsible for the transfer in and out of the memory of the ARM. Current Features: • Slave implementation • 6.5 kByte Process Data Memory • 8 SyncManager units • 8 FMMUs (Fieldbus Memory Management unit, support only byte-wise mapping) • Mailbox-Functionality for CANopen over EtherCAT, Ethernet over EtherCAT • Powerful AL Controller integrated SERCOS-III uses the same filters and the state machines which are defined by the IGS e.V.. EtherNet/IP uses only the standard Ethernet-Functions of one channel. However for motion control with synchronization down to a microsecond, the distributed time according to the international Standard IEEE 1588 is used. This means to measure transmit and receive time by hardware at the MII interface between xMAC and PHY, using a special protocol, this information is exchanged between the network devices and the local system time is adjusted to a common network time. The Real-Time-Communication of PROFINET uses a Switch function and priority control according IEEE 802.1Q. For this the xPECs owns local memory to manage the routing data and a state machine to control the telegram transfers. The transfer time through the internal switch is less than 3 µs. For Motion Control, PROFINET uses isochronous transmission. This requires synchronization of the local time by IEEE 1588 and transmission of the telegrams results according to a time table. This time control is another mode of the xPEC state machine.The netX is fully compliant to the PROFINET IRT specification. These features allow device manufactures to use a unified Hardware, activating the several special Real-Time-Ethernet functions by appropriate software as needed.



Block diagram of the special Real-Time Ethernet Features Note: For better understanding, the data switch is not shown.



2.27 Fieldbus Interface

The XMAC/XPEC units of the netX can operate as fieldbus controllers (one XMAC and one XPEC per fieldbus channel), for virtually any existing and future fieldbus system, like: • AS interface Master • CANopen Master and / or Slave • CC-Link Slave • DeviceNet Master and / or Slave • PROFIBUS-DP Master and / or Slave Different systems can be combined. The following sub chapters show the typical external circuitry required for the implementation of a cer-tain fieldbus interface with the netX. These schematics are for demonstration only. For detailed hardware design information, please consult the latest revisions of the reference schematics, available through the netX Download section at www.hilscher.com as well as the latest revisions of the appropri-ate fieldbus interface specifications.

http://www.hilscher.com/



2.27.1 AS interface Master

Basic circuit for netX AS interface Master Please note, that the A2SI chip is about to be discontinued! This section will be updated as soon as a substitute has been selected and evaluated!

VDD

GND

ADuM1301

netX

XMi_RX

XMi_TX

XMi_IO0

VDD

GND

Asi+1

Asi-2

-+ Umin

Powerfail

RXD

TXD

USR

+ASi

-ASi

0V

+5VA2SI (Master Mode)

+3.3V

GND

For details, consultA2SI data sheet

UINUOUT

ASI_RX

ASI_TX

ASI_PF



2.27.2 CANopen Interface

Basic circuit for netX CANopen interface



2.27.3 CC-Link Interface

Basic circuit for netX CC-Link interface



2.27.4 DeviceNet Interface

Basic circuit for netX DeviceNet interface



2.27.5 PROFIBUS Interface

Basic circuit for netX PROFIBUS interface

netX50 Technical Data Reference Guide Electrical Specifications • 106


3 Electrical Specifications

3.1 Absolute Maximum Ratings

Stresses beyond the following ratings may cause permanent damage to the device. Please note, that these stress ratings do not imply functional operation of the device and that exposure to these ratings for extended periods of time may affect device reliability.

Symbol Parameter Conditions Ratings Unit VDDC Power supply, core voltage -0.5 to 2.0 V VDDIO Power supply, IO voltage -0.5 to 4.6 V USB_VDDC USB power supply, core voltage -0.5 to 2.0 V USB_VDDIO USB power supply, IO voltage -0.5 to 4.6 V OSC_VDDC Oscillator power supply, core voltage -0.5 to 2.0 V PHY_VDDCART PHY power supply -0.5 to 2.0 V PHY_VSSACP PHY power supply -0.5 to 2.0 V PHY_VDDIOAC PHY power supply -0.5 to 4.6 V PHY_VDDIOAT PHY power supply -0.5 to 4.6 V PHY_VDDD PHY digital power supply -0.5 to 2.0 V VI Input voltage VI < VDDIO + 0.5

V -0.5 to 4.6 V

VO Output voltage VO< VDDIO + 0.5 V

-0.5 to 4.6 V

6 mA type ±21 mA 9 mA type ±29 mA

IO Output current

USB type ±37 mA TA Operating ambient temperature Note 1) -40 to +85 °C Tj Junction temperature Note 1) -40 to +125 °C Tstg Storage temperature Note 2) -65 to +150 °C

Notes:

1) See also chapter 4.1.

2) This temperature range has no relation to soldering conditions or solderability of the compo-nents. Please check chapter 4.3 for storage conditions that assure solderability.



3.2 Power Up Sequencing

All power supplies of the netX chip must ramp up or down within 100 ms time. There is no prescribed order in which the supplies must be applied, however all voltages should have reached the 0.9 * VDD condition not later than 100ms after the first supply started to ramp up (time measured from 0.1 * VDD condition). The following figure shows details of powering up and down. Note: All power supply voltage pins have to be connected to the power supplies, even when certain periph-eral parts of the netX chip are not used!



3.3 Power Consumption / Power Dissipation

The typical power consumption of the netX50 is approximately 1.3 Watts (integrated PHYs in use) or 0.8 Watts (PHYs turned off).The following tables provide an overview of power consumption of single modules of the chip and some standard applications. Power consumption of netX50 chip:

Symbol Unit Min. Typ. Max. Unit PBASE Ground consumption, chip in idle state 0.4 W PARM ARM CPU 0.01 0.08 0.1 W PSDRAM SDRAM Note 1) 0.02 0.1 0.2 W PHIF Host interface, DPM mode, 32 Bit Note 2) 3) 0 0.05 0.15 W PXC Two communication channels (XMAC and XPEC) Note 2) 4) 0 0.12 0.14 W PPHY Two Ethernet PHY’s (100Base-TX) Note 5) 0 0.49 W PMAX Max. chip power consumption Note 6) 1.5 W PRES Max. chip power consumption while PORn is active 0.02 W

All values above assume nominal supply voltages ( VDDC = 1.5V , VDDIO = 3.3V). Increasing the supply voltages to their maximum (1.65V and 3.6V) will increase power consumption by appr. 25% Notes:

1) SDRAM IO power consumption strongly depends on capacitive load, access rate and type of access (write consumes significantly more power than read). Max. value is valid for a single SDRAM component, located close to the (trace length <= 2cm) at stress test condition (maxi-mum possible (write) access rate, which can not be reached in a useful application).

2) Min. values apply when modules are idle (not used). 3) Max. value is at maximum possible access rate (reading) and maximum allowed load capacity

of 50pF on all host interface data signals. 4) If only one communication channel (fieldbus or Ethernet) is used, power consumption is 50% of

stated values. 5) Each Ethernet port requires one communication channel and one PHY. If only one PHY is en-

abled, power consumption is 50% of stated value (max. value). Min. value applies when both PHYs are disabled.

6) At preceding conditions.

netX power consumption at typical setups:

Symbol Parameter Typ. Unit PBOOT Serial boot mode, no external communication 0.5 W P2ETH 2 Port Full Duplex Ethernet, SDRAM 1.2 W P1ETH 1 Port Full Duplex Ethernet, SDRAM 1 W PFB_SPI Fieldbus 12 MBaud, one channel, DPM, SPI-FLASH, SDRAM 0.7 W PFB_PFLASH Fieldbus 12 MBaud, one channel, DPM, PFLASH, no SDRAM 0.7 W



Power supply surrent overview:

Symbol Parameter Conditions Min. Typ. Max. Unit IDD_3V3 complete power supply 3.3V Note 1) 3.3 V 300 mA IDD_1V5 complete power supply 1.5V Note 2) 1.5 V 600 mA IDDC Power supply current, netX core 1.5 V 2 400 mA IDDIO Power supply current, netX IO Note 3) 3.3 V 5 150 mA USB_IVDDC USB core current 1.5 V 5 mA USB_IVDDIO USB IO current Note 4) 3.3 V 5 mA OSC_IVDDC Oscilator core current 1.5 V 6 mA PHY_IVDDC PHY core current, includes IVDDCART

and IVDDCAP Note 5) 1.5 / 1.65 V 150 180 mA

PHY_IVDDIO PHY IO current, includes IVDDIOAC and IVDDIOAT Note 6)

3.3 / 3.6 V 130 150 mA

PHY_IEXTPU PHY IO ext. pull-up resistor current Note 6)

3.6 V 100 mA

Notes:

1) Assuming standard setup (1 * SDRAM, 1* ser. FLASH, 2 Ethernet Ports at 100Base-TX). It is recommended to design the power supply for a worst case current of 0.35A @ 3.3V (see also Note 3!).

2) Assuming that no other components than the netX50 are powered by the 1.5V core supply. It is

recommended to design the power supply for a worst case current of 0.8A @ 1.5V. 3) Actual max. value is widely application specific. Stated value does not include applications that

drive current through a large number of IO pins (e.g. for directly driving LEDs). 4) The max. value does not include short circuit conditions with a worst case value of 170mA (as-

suming the short circuit is behind the serial resistors of D- / D+). If the system is to keep running during such conditions, the 3.3V system power supply must either be able to source the addi-tional current or the USB IO power supply must be powered by a separate supply.

5) Stated current values apply, when both PHYs are enabled and operate in 100Base-TX mode

(worst case for core power consumption). Max. current applies at max. voltage conditions. 6) The stated current values apply, when both PHYs are enabled and operate in 10Base-T mode

(worst case for IO power consumption). Max. current applies at max. voltage conditions.



3.4 AC / DC Specifications

3.4.1 DC Parameters

The following table describes the standard pad cells of the netX50. The special pad cells for crystal, USB and PHYs are described in the following chapters.

Symbol Parameter Conditions Min. Typ. Max. Unit VDDC Power supply voltage, core 1.425 1.5 1.65 V VDDIO Power supply voltage, IO 3.0 3.3 3.6 V VN Negative trigger voltage 0.6 1.8 V VP Positive trigger voltage 1.2 2.4 V VH Hysteresis voltage 0.3 1.5 V VIL Input voltage, low 0 0.8 V VIH Input voltage, high 3.3 V 2.0 VDDIO V slewri Input rise (normal input) 0.015 V/ns slewfa Input fall time (normal

input) 0.015 V/ns

slewri Input rise (Schmitt input) 0.27 V/ms slewfa Input fall time (Schmitt

input) 0.27 V/ms

IOZ Off-state current VO = VDDIO or GND ±10 µA IOS Output short circuit current -250

Note 1) mA

VI = VDDIO or GND

Normal input

±0.1 ±10 Note 2)

µA

VI = GND pull-up 50 kΩ

-37 -103 -253 µA

ILI Input leakage current

VI = VDDIO pull-down 50 kΩ

26 73 175 µA

VOL = 0.4V 6 mA type 6.0 mA IOL Output current, low 9 mA type 9.0 mA VOH =2.4V 6 mA type -6.0 mA IOH Output current, high 9 mA type -9.0 mA IOL = 0 mA 0.1 V IOL = 6 mA (6 mA type) 0.4 V

VOL Output voltage, low

IOL = 9 mA (9 mA type) 0.4 V IOH = 0 mA VDDIO-

0.1 V VOH Output voltage, high

IOH = 6 mA (6 mA type) 2.4 V CIN Pin capacitance Input buffer 2 4 6 pF CIO Pin capacitance Output and bidirectional

buffer 2 4 6 pF

RPU Resistance of internal 50k pull-up resistor

VDDIO = 3.3 ± 0.3V TA = -40 to +85°C

14.2 31.9 80.7 kΩ

RPD Resistance of internal 50k pull-down resistor

VDDIO = 3.3 ± 0.3V TA = -40 to +85°C

20.6 44.9 116.4 kΩ

Notes: 1) Output short circuit time no longer than one second and only one pin of the chip! 2) This value only applies to (also internally) unconnected standard pad cells. As most netX pins are equipped with internal pull-up or pull-down resistors, please also consider chapter 2.3 (Signal Definitions) to determine actual leakage current of a specific pin!



Symbol definition: VDDC , VDDIO: Indicates the voltage range for normal logic operations that occur when VSS = 0 V. VN : Indicates the input level at which the output level is inverted when the input is changed from the high-level side to the low-level side. VP : Indicates the input level at which the output level is inverted when the input is changed from the low-level side to the high-level side. VH : Indicates the differential between the positive trigger voltage and the negative trigger voltage. VIL : Indicates the voltage which must be applied to the input pins to guarantee a logical low input level. VIH : Indicates the voltage which must be applied to the input pins to guarantee a logical high input level. slewri : slew rate rise time slewfa : slew rate fall time IOZ : Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. IOS : Indicates the current that flows when the output pins are shorted (to GND pins) when output is at high level. The output short circuit must not exceed more than one second and is only for one pin. ILI : Indicates the current that flows via an input pin when a voltage is applied to that pin. IOL : Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. IOH : Indicates the current that flows from the output pins when the rated high-level output voltage is being applied. VOL : Indicates the output voltage at low level and when the output pin is open. VOH : Indicates the output voltage at high level and when the output pin is open.

http://dict.leo.org/se?lp=ende&p=/Mn4k.&search=slew

http://dict.leo.org/se?lp=ende&p=/Mn4k.&search=rate

http://dict.leo.org/se?lp=ende&p=/Mn4k.&search=slew

http://dict.leo.org/se?lp=ende&p=/Mn4k.&search=rate



Output buffer output current (IOL, IOH) The cell base IC output current is defined at the conditions of VOL = 0.4 V and VOH = 2.4 V in a 3.3 V output buffer. However, since it is possible to use different VOL and VOH values in actual applications, the following coefficient should be used to estimate the IOL and IOH characteristics according to the use con-ditions. VOL = 0.4 to 0.6 V, VOH = (VDD – 0.4 V) to (VDD – 0.6 V) Since IOL and IOH change almost in proportion to the output voltage, direction approximation can be used. Approximation method: IOL’ = IOL × VOL / 0.4 (mA) IOH’ = IOH × (VDD – VOH) / 0.6 (mA) IOL: IOL specification when VOL = 0.4 V VOL: VOL value being used IOH: IOH specification when VOH = 2.4 V (3.3 V output buffer) VOH: VOH value being used The MIN , TYP and MAX designators in the graph show the curve under the following conditions: Min.: VDD = 3.0 V (3.3 V output buffer), TJ = 125°C Typ.: VDD = 3.3 V (3.3 V output buffer), TJ = 25°C Max.: VDD = 3.6 V (3.3 V output buffer), TJ = –40°C 6mA output driver: (typical block type: TDOPAC33NN06, TDOPAC33NL06) (a) IOL vs. VOL (b) IOH vs. VOH IOL(mA) VOH(V)

VOL(V)

IOH(mA) 9ma output driver: (typical block type: TDOPAC33NN09, TDOPAC33NL09) (a) IOL vs. VOL (b) IOH vs. VOH IOL(mA) VOH(V)

VOL(V)

IOH(mA)



3.4.2 System Oscillator / PLL

The system oscillator circuit along with the internal PLL, generates all internal clocks of the netX50 chip. For clock generation, either a quartz crystal (oscillation mode: fundamental) with the internal oscillator circuit or a quartz oscillator connected to the clock input pin may be used.

Symbol Parameter Conditions Min. Typ. Max. Unit OSC_VDDC Oscillator power supply core 1.425 1.5 1.65 V VIL Input voltage, low Note 1) 0 0.8 V VIH Input voltage, high Note 1) 2.0 VDDIO + 0.5 V VOL Output voltage, low Note 1) 0.4 V VOH Output voltage, high Note 1) 2.0 3.0 VDDIO V fCLK System clock frequency 25 MHz System clock tolerance -100 +100 ppm System clock duty cycle 40 50 60 % System jitter tolerance 20 ps [RMS] TCYC System clock cycle time 40 ns Thigh System clock high time 14 20 ns Tlow System clock low time 14 20 ns System clock slew rate 0.5 V/ns CIN Pin capacitance input buffer 2.5 3.5 4.5 pF COUT Pin capacitance output buffer 2.7 3.7 4.7 pF OSC_IVDDC Oscillator current 1.5 V 6 mA

Notes:

1) These values are DC parameters, that do not apply to the dynamical system of a crystal circuit. When using crystals, the circuit should be designed in a way that keeps the levels within the absolute maximum ratings (-0,5V to Vddio + 0,5V).



3.4.3 Power On Reset / Reset Input

The netX provides two reset inputs, one asynchronous reset input with a Schmitt-trigger input cell that is to be used for the mandatory Power On Reset of the chip and one (optional) synchronous reset input that can be used to perform a system reset on the powered up and running chip. The picture and table below show the behavior of the reset system and the timing requirements for the reset input signals. 1)

Parameter Description Value Dimension tOSC Startup time for the internal oscillator system (25 MHz) < 10 ms 2) tPOR Minimum duration of external Power On Reset signal > tosc 2) tPLL Time between deassertion of PORn and start of internal PLL 10,5 ms tIRR Time between deassertion of PORn and release of internal Reset 11,5 ms tRES Minimum Reset pulse width for running chip 10 ns tRESi Active time of internal Reset after releasing RESET_INn 640 ns (64 clks)

Notes:

1) The use of RESET_INn is optional and shown in this diagram for reference only. It is not a required part of the startup reset sequence.

2) The Oscillator startup time depends on environment temperature and crystal type. The

given values are typical values that have been evaluated with a certain crystal and may dif-fer from the values experienced with the user’s application. The external reset signal source (reset generator) may release the PORn signal before the System oscillator has settled completely, however the values for tPLL and tIRR may diverge from the values above in that case, since they derive from counter values and the counters are clocked by the system oscillator.



3.4.4 MMIOs

For relationship between different netX50 MMIO signals, MMIO output timing is related to a virtual inter-nal clock root and MMIO input timing is related to a virtual external clock. MMIO relation calculation can be done as described in the example below. MMIO level change

MMIO output enable

MMIO output disable

MMIO output timing relationship calculation example

In this example, MMIO12 and MMIO16 are used in relation to each other. Scope of interest is rising edge output timing. The timing table at the end of this chapter provides the following tLH –values:

MMIO12: tLH_MMIO12 10.6ns MMIO16: tLH_MMIO16 12.5ns

That means: If MMIO12 and MMIO16 change from low to high by netX50 configuration register setting at the same moment (i.e. the same internal system clock cycle, e.g. by a single configuration register access), MMIO12 changes externally 1.9ns earlier from low to high than MMIO16 (tLH_MMIO16 - tLH_MMIO12) under maximum timing operating conditions.



MMIO input sampling

MMIO input timing relationship calculation example

MMIO12 and MMIO16 are used in relation to each other. Scope of interest is high level input timing of MMIO12 and the low level input timing of MMIO16. The timing table at the end of this chapter provides the following tSH – and tSL values:

MMIO12: tSH_MMIO12 1.9ns MMIO16: tSL_MMIO16 1.3ns

That means: If MMIO12 is to be sampled high and MMIO16 is to be sampled low by the same netX50 internal clock cycle, MMIO12 can change from low to high 1.9ns after a virtual external clock and MMIO16 can change from high to low 1.3ns after that virtual clock (maximum timing operating condi-tions). Or in other words, the external signal on MMIO16 must change from high to low at least 0.6ns before MMIO12 changes from low to high to have both states being sampled by the same netX50 inter-nal clock edge.

MMIO output-input timing relationship calculation example

MMIO12 is used as output pin (e.g. active low request signal) and MMIO16 is used as input pin (e.g. active high acknowledge signal) with some external logic in between. If the external access time be-tween request and acknowledge tac (e.g. 8.7ns) is known, the minimum number of cycles for sampling valid active high acknowledge on MMIO16 must match the following expression:

10ns * n - 5ns - tHL_MMIO12 + tSL_MMIO16 > tac 10ns * n - 5ns – 8.9ns + 1.3ns > 8.7ns n > 3

That means the value sampled from MMIO16 can be used netX50 internally 3 system clocks after MMIO12 signal generation.



Parameter Description Signal Min Typ Max Unit

tLH Output low to high level change time MMIO0 MMIO1 MMIO2 MMIO3 MMIO4 MMIO5 MMIO6 MMIO7 MMIO8 MMIO9 MMIO10 MMIO11 MMIO12 MMIO13 MMIO14 MMIO15 MMIO16 MMIO17 MMIO18 MMIO19 MMIO20 MMIO21 MMIO22 MMIO23 MMIO24 MMIO25 MMIO26 MMIO27 MMIO28 MMIO29 MMIO30 MMIO31 MMIO32 MMIO33 MMIO34 MMIO35 MMIO36 MMIO37 MMIO38 MMIO39

6.3 6.8 7.2 6.8 6.8 6.8 6.9 6.5 6.0 6.0 6.0 6.0 6.0 6.0 6.3 6.7 7.0 7.0 7.1 6.9 7.1 6.9 7.0 7.1 7.0 7.0 6.9 7.2 7.0 7.1 7.0 7.0 7.1 7.0 7.2 7.1 7.2 6.8 6.9 7.1

11.1 12.1 12.8 12.0 12.1 12.1 12.2 11.5 10.7 10.6 10.6 10.6 10.6 10.7 11.1 11.8 12.5 12.4 12.5 12.2 12.7 12.3 12.3 12.6 12.5 12.5 12.2 12.9 12.4 12.5 12.4 12.4 12.5 12.4 12.8 12.6 12.8 12.1 12.3 12.6

ns

tHL Output high to low level change time MMIO0 MMIO1 MMIO2 MMIO3 MMIO4 MMIO5 MMIO6 MMIO7 MMIO8

5.9 6.5 6.8 6.4 6.5 6.5 6.6 6.2 5.6

9.4 10.6 11.1 10.3 10.6 10.5 10.7 10.0 8.9

ns



MMIO9 MMIO10 MMIO11 MMIO12 MMIO13 MMIO14 MMIO15 MMIO16 MMIO17 MMIO18 MMIO19 MMIO20 MMIO21 MMIO22 MMIO23 MMIO24 MMIO25 MMIO26 MMIO27 MMIO28 MMIO29 MMIO30 MMIO31 MMIO32 MMIO33 MMIO34 MMIO35 MMIO36 MMIO37 MMIO38 MMIO39

5.6 5.6 5.6 5.6 5.7 5.8 6.3 6.7 6.6 6.8 6.5 6.8 6.6 6.7 6.7 6.6 6.7 6.6 6.9 6.7 6.7 6.6 6.7 6.8 6.6 6.9 6.7 6.9 6.5 6.6 6.7

8.9 8.9 8.9 8.9 9.0 9.2 10.2 10.9 10.8 11.1 10.5 11.1 10.6 10.9 10.8 10.7 10.9 10.7 11.3 10.8 10.9 10.7 11.0 10.9 10.7 11.3 10.9 11.3 10.5 10.7 10.9

tenH Output enable hiZ to high level time MMIO0 MMIO1 MMIO2 MMIO3 MMIO4 MMIO5 MMIO6 MMIO7 MMIO8 MMIO9 MMIO10 MMIO11 MMIO12 MMIO13 MMIO14 MMIO15 MMIO16 MMIO17 MMIO18 MMIO19 MMIO20

6.3 7.1 6.9 6.5 7.0 7.0 7.0 7.1 6.1 6.1 6.1 6.1 6.1 6.1 6.2 6.8 7.1 7.1 7.1 7.4 7.1

11.6 13.0 12.8 11.9 12.8 12.8 12.8 13.1 11.2 11.2 11.2 11.2 11.3 11.3 11.5 12.5 13.0 12.9 13.0 13.6 13.1

ns



MMIO21 MMIO22 MMIO23 MMIO24 MMIO25 MMIO26 MMIO27 MMIO28 MMIO29 MMIO30 MMIO31 MMIO32 MMIO33 MMIO34 MMIO35 MMIO36 MMIO37 MMIO38 MMIO39

7.1 7.2 7.1 7.1 7.0 7.0 7.2 7.2 7.2 7.1 7.1 7.1 7.2 7.1 7.2 7.1 7.3 7.2 7.0

13.1 13.3 13.1 12.9 12.8 12.9 13.2 13.4 13.2 13.1 13.1 13.1 13.2 13.1 13.1 13.1 13.3 13.2 12.8

tenL Output enable hiZ to low level time MMIO0 MMIO1 MMIO2 MMIO3 MMIO4 MMIO5 MMIO6 MMIO7 MMIO8 MMIO9 MMIO10 MMIO11 MMIO12 MMIO13 MMIO14 MMIO15 MMIO16 MMIO17 MMIO18 MMIO19 MMIO20 MMIO21 MMIO22 MMIO23 MMIO24 MMIO25 MMIO26 MMIO27 MMIO28 MMIO29 MMIO30 MMIO31 MMIO32

6.0 6.8 6.6 6.1 6.7 6.6 6.6 6.8 5.8 5.8 5.8 5.8 5.8 5.8 5.9 6.5 6.8 6.7 6.7 7.0 6.8 6.8 6.9 6.8 6.7 6.7 6.7 6.9 6.9 6.9 6.8 6.8 6.8

9.9 11.3 11.0 10.1 11.1 11.0 11.0 11.3 9.5 9.5 9.4 9.4 9.6 9.6 9.8 10.7 11.2 11.2 11.2 11.8 11.3 11.3 11.5 11.4 11.2 11.1 11.1 11.5 11.6 11.4 11.3 11.3 11.3

ns



MMIO33 MMIO34 MMIO35 MMIO36 MMIO37 MMIO38 MMIO39

6.8 6.8 6.8 6.8 6.9 6.8 6.7

11.4 11.4 11.4 11.3 11.6 11.4 11.1

tdisH Output disable high level to hiZ time MMIO0 MMIO1 MMIO2 MMIO3 MMIO4 MMIO5 MMIO6 MMIO7 MMIO8 MMIO9 MMIO10 MMIO11 MMIO12 MMIO13 MMIO14 MMIO15 MMIO16 MMIO17 MMIO18 MMIO19 MMIO20 MMIO21 MMIO22 MMIO23 MMIO24 MMIO25 MMIO26 MMIO27 MMIO28 MMIO29 MMIO30 MMIO31 MMIO32 MMIO33 MMIO34 MMIO35 MMIO36 MMIO37 MMIO38 MMIO39

3.5(1) 4.3(1) 4.1(1) 3.6(1) 4.3(1) 4.1(1) 4.2(1) 4.4(1) 3.3(1) 3.3(1) 3.3(1) 3.3(1) 3.3(1) 3.3(1) 3.3(1) 4.0(1) 4.2(1) 4.2(1) 4.3(1) 4.5(1) 4.3(1) 4.3(1) 4.4(1) 4.3(1) 4.3(1) 4.2(1) 4.3(1) 4.4(1) 4.3(1) 4.4(1) 4.2(1) 4.3(1) 4.3(1) 4.5(1) 4.3(1) 4.4(1) 4.3(1) 4.4(1) 4.2(1) 4.2(1)

6.3(1) 7.8(1) 7.4(1) 6.5(1) 7.7(1) 7.5(1) 7.6(1) 7.9(1) 5.8(1) 5.8(1) 5.8(1) 5.8(1) 5.9(1) 5.9(1) 6.0(1) 7.1(1) 7.6(1) 7.6(1) 7.7(1) 8.1(1) 7.8(1) 7.7(1) 7.9(1) 7.9(1) 7.7(1) 7.6(1) 7.7(1) 7.8(1) 7.8(1) 7.9(1) 7.6(1) 7.8(1) 7.7(1) 8.1(1) 7.8(1) 7.9(1) 7.8(1) 8.0(1) 7.6(1) 7.5(1)

ns

tdisL Output disable low level to hiZ time MMIO0 MMIO1 MMIO2 MMIO3

3.4(1) 4.2(1) 4.0(1) 3.5(1)

6.2(1) 7.6(1) 7.3(1) 6.4(1)

ns



MMIO4 MMIO5 MMIO6 MMIO7 MMIO8 MMIO9 MMIO10 MMIO11 MMIO12 MMIO13 MMIO14 MMIO15 MMIO16 MMIO17 MMIO18 MMIO19 MMIO20 MMIO21 MMIO22 MMIO23 MMIO24 MMIO25 MMIO26 MMIO27 MMIO28 MMIO29 MMIO30 MMIO31 MMIO32 MMIO33 MMIO34 MMIO35 MMIO36 MMIO37 MMIO38 MMIO39

4.1(1) 4.0(1) 4.0(1) 4.2(1) 3.1(1) 3.1(1) 3.1(1) 3.1(1) 3.1(1) 3.1(1) 3.2(1) 3.8(1) 4.1(1) 4.1(1) 4.1(1) 4.4(1) 4.2(1) 4.1(1) 4.2(1) 4.2(1) 4.1(1) 4.1(1) 4.1(1) 4.2(1) 4.2(1) 4.2(1) 4.1(1) 4.2(1) 4.1(1) 4.3(1) 4.1(1) 4.2(1) 4.2(1) 4.3(1) 4.1(1) 4.0(1)

7.6(1) 7.4(1) 7.4(1) 7.8(1) 5.7(1) 5.7(1) 5.7(1) 5.7(1) 5.8(1) 5.8(1) 5.8(1) 7.0(1) 7.5(1) 7.5(1) 7.6(1) 8.0(1) 7.6(1) 7.6(1) 7.8(1) 7.8(1) 7.6(1) 7.5(1) 7.6(1) 7.7(1) 7.7(1) 7.7(1) 7.5(1) 7.7(1) 7.6(1) 8.0(1) 7.6(1) 7.8(1) 7.7(1) 7.8(1) 7.5(1) 7.4(1)

tSH High level input sampling time MMIO0 MMIO1 MMIO2 MMIO3 MMIO4 MMIO5 MMIO6 MMIO7 MMIO8 MMIO9 MMIO10 MMIO11 MMIO12 MMIO13 MMIO14 MMIO15

0.8 0.8 0.8 0.9 0.9 0.8 0.8 0.8 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.8

1.8 1.8 1.8 1.8 1.8 1.7 1.8 1.7 1.8 1.8 1.8 1.8 1.9 1.9 1.9 1.7

ns



MMIO16 MMIO17 MMIO18 MMIO19 MMIO20 MMIO21 MMIO22 MMIO23 MMIO24 MMIO25 MMIO26 MMIO27 MMIO28 MMIO29 MMIO30 MMIO31 MMIO32 MMIO33 MMIO34 MMIO35 MMIO36 MMIO37 MMIO38 MMIO39

0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.7 0.8 0.8 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9 0.9

1.6 1.7 1.7 1.6 1.6 1.7 1.7 1.7 1.4 1.7 1.7 1.9 1.9 1.9 1.9 1.9 1.9 1.9 1.8 1.8 1.8 1.8 1.8 1.8

tSL Low level input sampling time MMIO0 MMIO1 MMIO2 MMIO3 MMIO4 MMIO5 MMIO6 MMIO7 MMIO8 MMIO9 MMIO10 MMIO11 MMIO12 MMIO13 MMIO14 MMIO15 MMIO16 MMIO17 MMIO18 MMIO19 MMIO20 MMIO21 MMIO22 MMIO23 MMIO24 MMIO25 MMIO26 MMIO27

0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.8 0.9 0.9 0.8 0.8 0.7 0.8 0.8 0.7 0.7 0.8 0.8 0.8 0.7 0.8 0.8 0.9

1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.4 1.5 1.5 1.4 1.5 1.5 1.5 1.4 1.3 1.3 1.4 1.3 1.3 1.3 1.3 1.4 1.1 1.3 1.3 1.5

ns



MMIO28 MMIO29 MMIO30 MMIO31 MMIO32 MMIO33 MMIO34 MMIO35 MMIO36 MMIO37 MMIO38 MMIO39

0.9 0.9 0.9 0.9 0.9 0.9 0.8 0.8 0.8 0.8 0.8 0.8

1.5 1.5 1.5 1.5 1.5 1.5 1.4 1.4 1.5 1.4 1.4 1.5

Notes:

1. Output driver disabling is externally propagated after tdisH (or tdisL). If no other device drives the appropriate MMIO line, a previously driven high level will persist for some time due to capaci-tive loads (depending on pull-up / pull-down resistors).



3.4.5 USB

Symbol Parameter Conditions Min. Typ. Max. Unit USB_VDDC USB power supply, core 1.425 1.5 1.65 V USB_VDDIO USB power supply, IO 3.0 3.3 3.6 V USB_IVDDC USB core current 1.5 V 5 mA USB_IVDDIO USB IO current 3.3 V 5 mA VIH Input-high voltage single end 2.0 VDDIO+0.5 V VIL Input-low voltage single 0 0.8 V VDI Differential input voltage 0.8 V < VIN < 2.5 V 200 mV VOH Output-high voltage ext. 15 kΩ pull-up to VDDIO 2.8 VDDIO V VOL Output-low voltage ext. 1.5 kΩ pull-down to GND 0 0.3 V CPIN Pin capacitance 5 7 pF



3.4.6 PHY

The power supplies of the PHYs must always be connected, even when they are not used.

Symbol Parameter Conditions Min. Typ. Max. Unit PHY_VDDCART PHY power supply 1.425 1.5 1.65 V PHY_VDDCAP PHY central analog power supply 1.425 1.5 1.65 V PHY_VDDIOAC PHY central analog power supply 3.0 3.3 3.6 V PHY_VDDIOAT PHY analog test power supply 3.0 3.3 3.6 V

1.5 V 120 140 mW P10BT for both Phy's 3.3 V 420 500 mW 1.5 V 230 270 mW P100BT for both Phy's 3.3 V 260 300 mW 1.5 V 100 120 mW P100FX for both Phy's 3.3 V 5 6 mW

PHY_REXTRES Reference resistor Must always be connected, 12.4 kΩ / 1% PHY_IVDDC PHY core current,

includes IVDDCART and IVDDCAP 1.5 V 2 150 180 mA

PHY_IVDDIO PHY IO current, includes IVDDIOAC and IVDDIOAT

3.3 V 1 130 150 mA

Max. power and current values apply at max. voltage conditions

100BASE-TX:

Symbol Parameter Conditions Min. Typ. Max. Unit V100OUTH TX Output, High Level

Differential Signal, TXP/TXN 0.95 1.05 V

V100OUTL TX Output, Low Level Differential Signal, TXP/TXN

-0.95 -1.05 V

V100OUTM TX Output, Mid. Level Differential Signal, TXP/TXN

-0.05 +0.05 V

VOVS TX Output, Overshoot Differential Signal, TXP/TXN

0 5 %

V100INTHON RX Input, Turn-on Threshold Level Differential Signal, RXP/RXN

1.0 V

V100INTHOFF RX Input Turn-off Threshold Level Differential Signal, RXP/RXN

0.20 V

tr Rise time, TXP/TXN 3 5 ns tf Fall time, TXP/TXN 3 5 ns Duty cycle distortion, TXP/TXN 0 0.5 ns(pp) Transmit Jitter, TXP/TXN 0 1.4 ns(pp)

These specs are compliant with ANSI/IEEE802.3 Std. 10BASE-T:

Symbol Parameter Conditions Min. Typ. Max. Unit V10OUT TX Output Amplitude

Differential Signal, TXP/TXN 2.2 2.8 V

V10INTH RX Input Threshold Level Differential Signal, RXP/RXN

0.30 0.585 V

These specs are compliant with ANSI/IEEE802.3 Std.



3.4.7 SDRAM

Initialization Auto refresh cycles



Self refresh mode, entry and exit



Write access SDRAM Write Timing, single bank write (MEM_SDCKE is always high and is hence not shown) Read access SDRAM Read Timing, single bank write (MEM_SDCKE is always high and is hence not shown)



All Timings are related to the following SDRAM clock phase settings ( sdram_timing_ctrl register): mem_sdclk_phase: 3 data_sample_phase: 1 Electrical Characteristics of netX50 SDRAM Memory Interface Part (CL MEM_D0..31: 15pF, all other signals 10pF):

Symbol Parameter Min Typ Max Unit

tCP SDRAM Clock (MEM_SDCLK) cycle time 10.0(1) 10.0(1) (1) ns

tCH SDRAM Clock (MEM_SDCLK) high level width 3.5 4.7 ns

tCL SDRAM Clock (MEM_SDCLK) low level width 3.8 4.8 ns

tCKS Clock Enable (MEM_SDCKE) setup time 4.5(2) 5.3(2) ns

tCKH Clock Enable (MEM_SDCKE) hold time 2.3(2) 2.9(2) ns

tCMS Command setup time MEM_SDCS_N MEM_SDWE_N MEM_SDRAS_N MEM_SDCAS_N

4.6 4.2 4.2 4.3

5.4 5.2 5.2 5.3

ns

tCMH Command hold time MEM_SDCS_N MEM_SDWE_N MEM_SDRAS_N MEM_SDCAS_N

2.2 2.5 2.5 2.3

2.8 3.0 3.0 2.9

ns

tAS Address (without MEM_A10) setup time 4.2 5.2 ns

tAH Address (without MEM_A10) hold time 2.3 2.9 ns

tA10S MEM_A10 setup time 4.4 5.3 ns

tA10H MEM_A10 hold time 2.4 2.9 ns

tDQMS Data Qualifier Mask (MEM_DQM*) setup time 4.2 5.2 ns

tDQMH Data Qualifier Mask (MEM_DQM*) hold time 2.3 2.9 ns

tDS netX Data-out setup time 3.6 4.8 ns

tDH netX Data-out hold time 2.2 3.0 ns

tDE netX Data-out enable (Low Z) time 4.1 5.1 ns

tDD netX Data-out disable (High Z) time 2.6 3.3 ns

tAC SDRAM Access time 7.3 ns

tOH SDRAM Data-out hold time 0.0 ns

tLZ SDRAM Data-out enable (Low Z) time 0.0 ns

tHZ SDRAM Data-out disable (High Z) time 14.9 ns Notes:

2. MEM_SDCLK is always running at the same frequency as netX internal system clock.

3. MEM_SDCKE is only used for SDRAM power down (Self Refresh mode or SDRAM disabled).



Timing Characteristics configurable by sdram_timing_ctrl configuration register.


tRAS ACTIVE to PRECHARGE time 3..10 tCP

tRC ACTIVE to ACTIVE (same bank) time 4..13(1) tCP

tRCDR ACTIVE to READ (same bank) time 1..3(2) tCP

tRCDW ACTIVE to WRITE (same bank) time 2..4(2) tCP

tREFI Average periodic REFRESH interval (Refresh period di-vided by rows to refresh within refresh period)

3.9(3) 7.8(3) 15.6(3)

31.2(3) us

tRFC AUTO REFRESH period 4..19 tCP

tRP PRECHARGE command period 1..3 tCP

tRRD ACTIVE to ACTIVE different bank time 1..3(4) tCP

tWR WRITE recovery time 1..3 tCP

tSR Self Refresh period 1 tCP

tXSRP Self Refresh Clock active to exit period exit 4 tCP

tXSR Self Refresh exit to command period 4..19(5) tCP

tCL CAS Latency 2 3 tCP Notes:

1. Minimum tRC is tRAS + tRP.

2. ACTIVE to WRITE (same bank) time is ACTIVE to READ (same bank) time plus 1 additional cycle form memory controller internal arbitration.

3. At 100MHz system clock.

4. SDRAM Controller uses a common parameter for tRP and tRRD.

5. SDRAM Controller uses a common parameter for tRFC and tXSR.

SDRAM Initialisation and Power Up Timing Characteristics.


tinit Whole SDRAM initialisation time till first ACTIVE 20317 20317 tCP

tinitP SDRAM Power Up time (NOP till first PRECHARGE) 20050 20050 tCP

tinitRP Initialisation PRECHARGE command period 16 16 tCP

tinitRFC Initialisation AUTO REFRESH period 23 32 tCP

tinitMRD Load MR to first command period 4(1) tCP Notes:

1. If longer tinitMRD time is required, software can wait until sdram_ready flag is set in sdram_general_ctrl register before running first SDRAM memory access.



3.4.8 SRAM / FLASH

Read access: Write access:



Parameter Notes min max Unit

Tadsr (address setup time, read): Time between assertion of CSn and valid address 1) 0.2 0.5 ns

Tadsw (address setup time, write): Time between valid address and assertion of CSn 1) 9.5 9.7 ns

Tdsr (data setup time, read): Time between assertion of RDn (+ Tws) and valid data from memory 1), 3) 0 8.2 ns

Tdsw (data setup time, write): Time between assertion of WRn and valid data to memory - 0.7 1.1 ns

Tdhw (data hold time, write): Time between deassertion of WRn and deactivation of output buffers - 0.6 1.1 ns

Tdhr (data hold time, read): Required hold time of memory data after deassertion of RDn 1), 3) 0 - ns

Twtc (write to chip select time) 2) 0.9 1.1 ns

Twspre: pre cycle waitstates, configurable in 10ns steps - 0 30 ns Tws: waitstates, configurable in 10ns steps - 0 310 ns Twspst: post cycle waitstates, configurable in 10ns steps - 0 30 ns Notes: 1) All timings are based on the following load conditions:

- control signals (RDn, WRn, CSn, DQM) loaded with 10 pF - address and data signals loaded with 15 pF Since the significant factor in signal delay variation is the pad cell delay rather than the internal sig-nal path delay, the actual timing is highly dependant on the actual capacitive signal load.

2) Twtc reflects the special clock path the write signal has been assigned to, to allow this signal (which

causes data sampling in the accessed memory on its rising edge) to become inactive earlier than all other signals. While CSn and address will be extended by post cycle waitstates, data lines will al-ways be deactivated with the write signal. Hence, scenarios, putting a capacitive load to WRn that is considerably high (WRn delay increases) while at the same time putting a considerably low capaci-tive load to the data lines (effective data hold time decreases), should be avoided, but are however very unlikely anyway (data inputs of memories usually have a higher input capacity than their con-trol signal inputs)

3) Internal data sampling during read accesses is initiated on the next rising edge of the internal 100MHz system clock after assertion of the read signal (no waitstates, Tws = 0) or after the last waitstate cycle (Tws) has ended. The allowed maximum data setup time is influenced by the signal delay of the external RDn signal and the internal (read data) sampling delay (which partly compen-sates the RDn delay) as well as the data signal input delay (which enhances the effect of the RDn delay) and is hence shorter than 10ns (one clock cycle); on the other hand, sampling has already happened on deassertion of the external RDn, hence the required data hold time is 0. (please also mind the delay between assertion of RDn and valid address, which will lead to a lower effective setup time in 0 waitstate scenarios, as with common memory components, the time from address to valid data is usually longer than the output enable time!)



3.4.9 SPI

3.4.9.1 Master mode

SPI master signal timing (SPO=0 and SPH=0)








SPI master timing for worst case operating conditions: VDD: 3.0..3.6V, Tj: -40..+125°C, CL: 20pF. Values in brackets apply if input filtering is enabled.

Symbol Master Mode Parameter Min Typ Max Unit

tCP SPI_CLK period 20.0(1) 40960/N(1)

40960(1) ns

tCH SPI_CLK high phase 0.5*tCP-3.0 ns

tCL SPI_CLK low phase 0.5*tCP-3.0 ns

tR Signal rise time 0.4(2) 3.4(2) ns

tF Signal fall time 0.3(2) 2.0(2) ns

tCSS SPI_CS_N to first SPI_CLK edge setup time 0.5*tCP ns

tCSH last SPI_CLK edge to SPI_CS_N inactive time - SPH 0 Modes - SPH 1 Modes

10.0 0.5*tCP+10.0

11.5 0.5*tCP+11.5

ns

tCSW SPI_CS_N minimum high pulse width 0.5*tCP-3.0(3,4)

ns

tMOSIS SPI_MOSI to SPI_CLK setup time 0.5*tCP-3.4 ns

tMOSIH SPI_MOSI hold time 0.5*tCP ns

tMOSIHZ SPI_MOSI High-Z time 3.5 ns

tMISOS SPI_MISO to SPI_CLK setup time 2.5(12.5)(5) ns

tMISOH SPI_MISO hold time 6.5(16.5)(5) ns

tSPW Tolerated spike pulse width - with input filtering - without input filtering

9.0 0.0

ns

Notes:

4. N is programmed by spi_cr0 register sck_muladd bits. N = 1..2048

5. Signal rise and fall times differ greatly depending on external capacitive load. Approximation can be done by:

rise times: tr = 0.350 + 0.150 * CL [ns]; CL: external capacitive load fall times: tf = 0.237 + 0.087 * CL [ns]; CL: external capacitive load

6. If fss_static bit is set in spi_cr1 register, SPI_CS_N will not toggle between data words but half clock pause before next word MSB will be inserted anyway.

7. In SPH=1 modes SPI_CS_N does not become inactive during continuous transfers between LSB and next word MSB.

8. Input filtering can be enabled / disabled by filter_in bit in spi_cr0 register.



3.4.9.2 Slave Mode

SPI slave signal timing (SPO=0 and SPH=0)

SPI slave signal timing (SPO=0 and SPH=1)



SPI slave signal timing (SPO=1 and SPH=0) SPI slave signal timing (SPO=1 and SPH=1)



SPI slave timing for worst case operating conditions: VDD: 3.0..3.6V, Tj: -40..+125°C, CL: 20pF. Values in brackets apply if input filtering is enabled.

Symbol Slave Mode Parameter Min Typ Max Unit

tSCP SPI_CLK high phase 30.0(60.0)(1,4) ns

tSCH SPI_CLK high phase 10.0(30.0) ns

tSCL SPI_CLK low phase 10.0(30.0) ns

tR Signal rise time 9.0(9.0) ns

tF Signal fall time 9.0(9.0) ns

tSMOSIS SPI_MOSI to SPI_CLK setup time 2.0(12.0) ns

tSMOSIH SPI_MOSI hold time 12.0(22.0) ns

tSMISOS SPI_CLK to SPI_MISO setup time 29.9(39.9)(3) ns

tSMISOS1 SPI_CS_N to SPI_MISO MSB setup time 33.9(43.9) ns

tSMISOH SPI_MISO hold time 17.3(27.3)(3) ns

tSMISOLZ SPI_CS_N to SPI_MISO MSB Low-Z time 17.5(27.5) ns

tSMISOHZ SPI_CS_N to SPI_MISO LSB High-Z time 28.5(38.5) ns

tSCSS SPI_CS_N to SPI_CLK setup time - SPH=0 modes - SPH=1 modes

tSMISOS1 0.5

ns

tSCSDH SPI_CS_N hold from deselected SPI_CLK edge time 40.0 ns

tSCSH SPI_CS_N hold time 10.5 ns

tSPW Tolerated spike pulse width - with input filtering - without input filtering

9.0 0.0

ns

Notes:

1. Minimum SPI_CLK period results from maximum MISO data setup time (tSMISOS) for valid read data.

2. Using SPH=0 modes SPI Chip Select falling edge is MSB data out trigger. Hence SPI Chip Se-lect must toggle between each transferred word. Using SPH=1 modes SPI Chip Select may remain active between transferred words.

3. For fast SPI clock rates early SPI_MISO signal generation can be enabled by slave_sig_early bit in spi_cr0 register. SPI_MISO will then be generated one SPI_CLK edge prior. For SPH=0 modes tSMISOS and tSMISOH will be related to SPI_CLK edges 1, 3, 5,... instead of 2, 4, 6,… (SPH=1 modes: SPI_CLK edges 2, 4, 6,... instead of 3, 5, 6,…).



3.4.10 I2C

The I2C Module IO timing depends on pad delays and internal module structure. All timings are related to an internal system clock running at 100MHz.


fSCL SCL clock frequency 50 (1) - 3333 (1) kHz

tSCL SCL clock period (1/ fSCL) 300 (1) - 20000 (1) ns

tfCL SCL fall time 3.1(2) ns

trCL SCL rise time 15.9 - 250 (3) ns

tfDA SDA fall time 3.1(2) ns

trDA SDA rise time 15.9 - 250 (3) ns

tLOW Low period of SCL clock tSCL/2 - tfCL - -(1) ns

tHIGH High period of SCL clock tSCL/2 - trCL - tSCL/2 ns

tHD;DAT SDA hold time 0.0 - 0.0 ns

tSU;DAT SDA setup time tSCL/2 - trDA - - ns

tHD;STA SCL hold time after (repeated) START condition tSCL/2 - - ns

tSU;STA SCL setup time before repeated START condition tSCL/2 - trCL - - ns

tSU;STO SCL setup time before STOP condition tSCL/2 - trCL - - ns

tBUF I2C bus idle time between STOP and START tSCL/2 - trDA - - ns

tSP Pulse width of spikes suppressed by input filters - - tSCL/32 ns Notes:

1. SCL Clock frequency may decrease (period may increase) if SCL is held low by other devices. SCL frequency is set by mode-bits of i2c_mcr register.

2. Signal fall times are only typical. Approximation can be done by following formula:

fall times: tf = 0.197 + 0.058 * CL [ns]; CL: external capacitive load

3. Signal rise times depend on pullup resistor and capacitive bus load. Specified rise times are for 500 Ohms pull-up resistor and 400pF load. For I2C High-speed mode and high capacitive load external driver devices can be used to reach faster rise times.



3.4.11 UART

Symbol Description Condition Min Max Unit Bit Time 0 255 Bit Times t1 Programmable leading time

System Time 0 2.55 µs

Bit Time 0 255 Bit Times t2 Programmable trailing time

System Time 0 2.55 µs

t3 Setup Time before the end of stop bit 70 ns Note: This example uses the following settings: - 1 Start Bit - 1 Stop Bit - 8 Data Bits - Mode = '1'



3.4.12 Dual-port memory

„IntelTM mode“, RDn controlled read access „IntelTM mode“, CSn controlled read access „IntelTM mode“, write access




tAS Address setup time nCS controlled nRD controlled

0.1 0.2

ns

tAH Address hold time 0.0 ns tDEN Data line enable time

nCS controlled nRD controlled

7.1 7.3

ns

tDVAL Data valid time tsys * 5 + tRA (1) (2) ns tDVR Data valid to Ready time tsys * n -1.4 (1) (3) ns tDH Data hold time

nCS controlled nRD controlled

4.6 4.8

ns

tCSI Chip select signal inactive time tsys (1) ns

tRDI Read signal inactive time tsys (1) ns

tRA Ready active time tsys * 2 + 3.5 (1) tsys * 3 + 5.5 (1) ns Notes:

1. Depending on internal system clock running with 100MHz by default (tsys=10.0ns).

2. Depending on netX internal wait states. This value shows timing for access to internal SRAM running with 0 wait states. Add 10.0ns for each wait state if access goes to wait state memory area (e.g. xPEC RAM). Access time to SDRAM is not predictable.

3. n is programmable by HIF config register: n=0..3.



3.4.13 JTAG

Symbol Parameter Min. Typ. Max. Unit t1 Clock Period 90 ns fTCLK JTAG Clock frequency Note 1 11.11 MHz t2 Clock Low Time 40 ns t3 Clock High Time 40 ns t4 Setup Time before rising edge 0 ns t5 Hold Time after rising edge 15 ns t6 TCLK to TDO delay 12 17 ns t7 TCLK to High-Z delay 12 17 ns

Note: The maximum frequency is CLOCKARM / 18 = 200 MHz / 18 = 11.11 MHz.



3.5 Failure Rate (FIT)

Due to the comparatively low volume of netX controller production, Failure Rates for the complete chip are not available. However, as a guideline value, the known FIT values (as at August 2007) for the CB-12 process, the netX50, netX100 and netX500 are based on, can be used:

Failure Rate (FIT), Confidence Level = 60%

Junction Temperature Ea = 0.3eV Ea = 0.5eV (Typ.) Ea = 0.7eV

55 °C 26 5 1 70 °C 41 12 3 80 °C 55 19 7 90 °C 72 31 13 100 °C 94 48 24 125 °C 168 127 95

netX50 Technical Data Reference Guide Package and Signal Information • 146


4 Package and Signal Information

4.1 Thermal Package Specification

Absolute maximum junction temperature: Tj_max = 125 °C Absolute minimum junction temperature: Tj_min = -40 °C Recommended operating ambient temperature: Operating ambient temperature: -25 °C … +85 °C @ typ. 1.3 Watt (with heat sink Rth ≤ 10 K/W) Operating ambient temperature: -25 °C … +70 °C @ typ. 1.3 Watt (without heat sink) Thermal Characterization (based on JEDEC 4 Layer PCB with vias):

Air Flow [m/s] Symbol Parameter 0 0.2 1 2 Unit

θja Thermal resistance, junction-to-ambient 23.0 20.8 18.3 17.0 °C/W

ψjt Thermal parameter, junction to the top center of the package surface 0.09 0.17 0.32 0.43 °C/W

ψta Thermal parameter, the top center of the package surface to ambient 22.9 20.6 18.0 16.6 °C/W

θjc Thermal resistance, junction-to-case 5.76 °C/W

Case 1 - Without external heat sink: Case 2 - With external heat sink: Heat flow path exist not only on package top Package surface dominates heat flow path via heat sink Tt = Ta + ψta x PnetX Tj = Ta + (θjc + Rth) x PnetX Tj ≈ Tt

Notes:

1) The heat sink used by Hilscher for the netX50 (ICK S 18x18x6.5 SA, Fischer Elektronik) has a thermal resistance of 7 K/W



4.2 Soldering Conditions

The following soldering parameters are recommended for infrared reflow soldering. The netX package is suitable for a Pb-free soldering process.

4.2.1 Infrared Reflow Soldering Characterization

Symbol Parameter Value TPSTmax Maximum temperature, package´s surface temperature 260 °C t1 Preheating time at 160 to 180 °C 60 … 120 s t2 Maximum time of temperature higher than 220 °C ≤ 60 s t3 Maximum time at maximum temperature ≤ 10 s Maximum chlorine content of rosin flux 0.2 %



4.2.2 Vapour Phase Reflow Soldering (VPS) Characterization

Symbol Parameter Value TPSTmax Maximum temperature, package´s surface temperature 215 °C t1 Preheating time 30s - 60s t2 Time of temperature > 200°C 25s - 40 s Maximum chlorine content of rosin flux 0.2 %

4.3 General storage conditions

Parameter Conditions Min. Max. Unit Storage temperature Note 1) Sealed Drypack 5 30 °C Storage humidity Note 1) Sealed Drypack 20 70 %RH Storage time Note 2) Sealed Drypack 2 years

Storage temperature Note 3) Open Drypack < 25 °C Storage humidity Note 3) Open Drypack < 65 %RH Storage time after opening dry pack Note 3) Open Drypack 7 days

Baking time 125°C 20 72 hours Number of times of mounting 3 times

Notes:

1) Storing the sealed Drypacks at other conditions, may affect solderability of the components. 2) When storing sealed Drypacks for more than two years, it is recommended to check for oxida-

tion of the solder balls and perform tests to approve solderability prior to using the components for production. The two year period starts at the seal date, printed on the Drypack label.

3) Open Drypacks / unpacked components may be stored at these conditions for 7 days before

soldering. When exceeding one of the parameters temperature, humidity or time after opening a sealed Drypack, components must be tempered according to parameter “Baking time” before soldering.



4.4 Signal Definitions

Signal PAD Type Description General PORn IUS Power on Reset RSTINn IUS Reset Input RSTOUTn OZ6 Reset Output RDY IOD6 RDY-LED / Boot start option RUN IOD6 RUN-LED / Boot start option WDGACT IOU9 (’OZU9’) Watch dog active DPM_D19

shared IOU9 Data line D19 with 32 Bit DPM interface

CLKOUT OZ6 Clock out XTAL OSC_XTI XTAL 25 MHz Crystal Input OSC_XTO XTAL 25 MHz Crystal Output OSC_VSS GND Oscillator Ground Supply OSC_VDDC PWR Oscillator Power Supply 1.5 V JTAG JT_TRSTn IDS JTAG Test Reset JT_TMS IUS JTAG Test Mode Select JT_TCLK IUS JTAG Test Clock JT_TDI IUS JTAG Test Data Input JT_TDO OZ6 JTAG Test Data Output SPI SPI_CLK IOD6 SPI Clock SPI_CS0n IOD6 SPI Chip Select 0 SPI_CS1n IOD6 SPI Chip Select 1 SPI_MISO IOD6 SPI Master Input Slave Output Data SPI_MOSI IOD6 SPI Master Output Slave Input Data I2C I2C_SCL IOZUS9 (5k pu) I2C Serial Clock Line I2C_SDA IOZUS9 (5k pu) I2C Serial Data Line USB USB_DNEG USB USB D- Line USB_DPOS USB USB D+ Line USB_VSS GND USB Ground Supply USB_VDDIO PWR USB Power Supply 3.3 V Test function TEST ID Activate Test Mode TMC1 ID Test Mode 1 TMC2 ID Test Mode 2 TACT_TRST IDS Reset Test Controller TCLK IDS Test Clock

Leave open for normal operating mode

MEM_IF_OM IUS Mem Interface Output Mode Connect to GND for normal operating mode



Signal PAD Type Description MMIOs shared with ETM, Fiberoptic Interface and ‘direct’ XMAC signals MMIO0 IODS6 Multiplex Matrix IO 0 MMIO1 IODS6 Multiplex Matrix IO 1 XM0_TX IODS6 (’OD6’) XMAC0 Transmit Data XM0_TX_ECLK

shared

IODS6 (’OD6’) XMAC0 Transmit Data, clocked with external clock MMIO2 IODS6 Multiplex Matrix IO 2 XM0_ECLK IODS6 External Clock input for XM0_TX / output from XMAC0 FB0_CLK

shared

IODS6 (’OD6’) Clock output of fb0_clk MMIO3 IODS6 Multiplex Matrix IO 3 MMIO4 IODS6 Multiplex Matrix IO 4 XM1_TX IODS6 (’OD6’) XMAC1 Transmit Data XM1_TX_ECLK

shared

IODS6 (’OD6’) XMAC1 Transmit Data, clocked with external clock MMIO5 IODS6 Multiplex Matrix IO 5 XM1_ECLK IODS6 External Clock input for XM1_TX / output from XMAC1 FB1_CLK

shared

IODS6 (’OD6’) Clock output of fb1_clk MMIO6 IODS6 Multiplex Matrix IO 6 FB0_CLK

shared IODS6 (’OD6’) Clock output of fb0_clk

MMIO7 IODS6 Multiplex Matrix IO 7 FB1_CLK

shared IODS6 (’OD6’) Clock output of fb1_clk

MMIO8 -16 IODS6 Multiplex Matrix IOs 8 -16 MMIO17 IODS6 Multiplex Matrix IO 17 ETM_TCLK

shared IODS6 (’OD6’) ETM Trace clock

MMIO18 IODS6 Multiplex Matrix IO 18 ETM_TSYNC

shared IODS6 (’OD6’) ETM Trace synchronization

MMIO19 IODS6 Multiplex Matrix IO 19 ETM_DRQ

shared IODS6 (’OD6’) ETM Debug request

MMIO20 IODS6 Multiplex Matrix IO 20 ETM_DACK

shared IODS6 (’OD6’) ETM Debug acknowledge

MMIO21 IODS6 Multiplex Matrix IO 21 ETM_PSTAT0

shared IODS6 (’OD6’) ETM Pipe status 0





MMIO24 IODS6 Multiplex Matrix IO 24 ETM_TPKT00

shared IODS6 (’OD6’) ETM Trace packet 0

















Signal PAD Type Description MMIO32 IODS6 Multiplex Matrix IO 32 ETM_TPKT08 IODS6 (’OD6’) ETM Trace packet 8 FO0_EN

shared

IODS6 (’OD6’) Fiberoptic Ethernet channel 0, Enable MMIO33 IODS6 Multiplex Matrix IO 33 ETM_TPKT09 IODS6 (’OD6’) ETM Trace packet 9 FO0_RD

shared

IODS6 (’IDS’) Fiberoptic Ethernet channel 0, Receive Data MMIO34 IODS6 Multiplex Matrix IO 34 ETM_TPKT10 IODS6 (’OD6’) ETM Trace packet 10 FO0_SD

shared

IODS6 (’IDS’) Fiberoptic Ethernet channel 0, SD MMIO35 IODS6 Multiplex Matrix IO 35 ETM_TPKT11 IODS6 (’OD6’) ETM Trace packet 11 FO0_TD

shared

IODS6 (’OD6’) Fiberoptic Ethernet channel 0, Transmit Data MMIO36 IODS6 Multiplex Matrix IO 36 ETM_TPKT12 IODS6 (’OD6’) ETM Trace packet 12 FO1_EN

shared

IODS6 (’OD6’) Fiberoptic Ethernet channel 1, Enable MMIO37 IODS6 Multiplex Matrix IO 37 ETM_TPKT13 IODS6 (’OD6’) ETM Trace packet 13 FO1_RD

shared

IODS6 (’IDS’) Fiberoptic Ethernet channel 1, Receive Data MMIO38 IODS6 Multiplex Matrix IO 38 ETM_TPKT14 IODS6 (’OD6’) ETM Trace packet 14 FO1_SD

shared

IODS6 (’IDS’) Fiberoptic Ethernet channel 1, SD MMIO39 IODS6 Multiplex Matrix IO 39 ETM_TPKT15 IODS6 (’OD6’) ETM Trace packet 15 FO1_TD

shared

IODS6 (’OD6’) Fiberoptic Ethernet channel 1, Transmit Data



Signal PAD Type Description Memory Interface MEMSR_CS0 - 2n O6 SRAM Chip Select MEMSR_OEn O6 SRAM Output Enable MEMSR_WEn O6 SRAM Write Enable MEMDR_CSn O6 SDRAM Chip Select MEMDR_WEn O6 SDRAM Write Enable MEMDR_RASn O6 SDRAM RAS MEMDR_CASn O6 SDRAM CAS MEMDR_CKE O6 SDRAM Clock Enable MEMDR_CLK IOD6 (’OZD6’) SDRAM Clock (pad used as output only) MEM_DQM0 O6 Memory Data Qualifier Mask D0-7 MEM_DQM1 O6 Memory Data Qualifier Mask D8-15 MEM_DQM2 O6 Memory Data Qualifier Mask D16-23 MEM_DQM3 O6 Memory Data Qualifier Mask D24-31 MEM_D0 - 31 IOD6 Memory Data 0-31 MEM_A0 - 23 O6 Memory Address 0-23 PIOs shared with Dual-Port Memory shared with Extension Bus. PIOs PIO32 - 85 IOU9 Programmable IOs 32 - 85 Dual-Port Memory DPM_D0 -15 IOU9 Dual port memory Data 0 -15 DPM_D16 - 31 IOU9 Dual port memory Data 16 - 32, shared with other DPM signals DPM_A0 -15 IOU9 (’IU’) Dual port memory Address 0 -15

DPM_A16 -19 IOU9 (’IU’) Dual port memory Address 16 -19 (optional, used for address comparator only)

DPM_SELA12 -19 IOU9 (’IU’) Inputs for internal address comparator (-> DPM_A12 - 19) DPM_ALE IOU9 (’IU’) Dual port memory Adress Latch Enable DPM_CSn IOU9 (’IU’) Dual port memory Chip Select DPM_BE0 - 3 IOU9 (’IU’) Dual port memory Byte Enables 0 -3 (32 Bit mode only) DPM_BHEn IOU9 (’IU’) Dual port memory Byte High Enable DPM_RDn IOU9 (’IU’) Dual port memory Read DPM_WRLn IOU9 (’IU’) Dual port memory Write Low DPM_WRHn IOU9 (’IU’) Dual port memory Write High DPM_RDY IOU9 (’OZU9’) Dual port memory Ready DPM_INT IOU9 (’OZU9’) Dual port memory Interrupt Extension Bus EXT_D0 - 15 IOU9 Extension Bus Data 0 -15 EXT_A0 - 24 IOU9 (’OU9’) Extension Bus Address 0 - 24 EXT_CS0 - 3n IOU9 (’OU9’) Extension Bus Chip select 0 - 3 EXT_ALE IOU9 (’OU9’) Extension Bus Address Latch Enable EXT_BHEn IOU9 (’OU9’) Extension Bus High Enable EXT_RDn IOU9 (’OU9’) Extension Bus Read EXT_WRLn IOU9 (’OU9’) Extension Bus Write Low EXT_WRHn IOU9 (’OU9’) Extension Bus Write High EXT_RDY IOU9 (’IU’) Extension Bus Ready EXT_IRQ IOU9 (’IU’) Extension Bus Interrupt Request



Signal PAD Type Description

PHY 0 - PHY 1 PHY0_RXN PHY PHY 0 Receive Input negative PHY0_RXP PHY PHY 0 Receive Input positive PHY0_TXN PHY PHY 0 Transmit Output negative PHY0_TXP PHY PHY 0 Transmit Output positive PHY0_VSSAT1 AGND PHY 0 Analog Ground Supply PHY0_VSSAT2 AGND PHY 0 Analog Ground Supply PHY0_VSSAR AGND PHY 0 Analog Ground Supply PHY0_VDDCART APWR PHY 0 Analog TX/RX Power Supply 1.5 V PHY1_TXP PHY PHY 1 Receive Input negative PHY1_TXN PHY PHY 1 Receive Input positive PHY1_RXP PHY PHY 1 Transmit Output negative PHY1_RXN PHY PHY 1 Transmit Output positive PHY1_VSSAT1 AGND PHY 1 Analog Ground Supply PHY1_VSSAT2 AGND PHY 1 Analog Ground Supply PHY1_VSSAR AGND PHY 1 Analog Ground Supply PHY1_VDDCART APWR PHY 1 Analog TX/RX Power Supply 1.5 V PHY_EXTRES ANA Reference Resistor 12.4 k / 1% PHY_ATP ANA leave open! PHY_VSSACP AGND PHY Analog Central Ground Supply PHY_VDDCAP APWR PHY Analog Central Power Supply 1.5 V PHY_VDDIOAC APWR PHY Analog Central Power Supply 3.3 V PHY_VSSAT AGND PHY Analog Test Ground Supply PHY_VDDIOAT APWR PHY Analog Test Power Supply 3.3 V Power Supply VSS 46 x GND Ground Supply (except PHYs and OSC) VDDC 34 x PWR Power Supply, Core 1.5 V (except PHYs and OSC) VDDIO 24 x PWR Power Supply, IO Buffer 3.3 V (except PHYs and USB)

PAD Type Explanation: Symbol Description I Input O Output Z Output is tristateable or open drain S Input provides Schmitt trigger U Internal pull-up 50 k (I2C pins: pull-up 5k) D Internal pull-down 50 k 6 Output buffer can source / sink 6 mA 9 Output buffer can source / sink 9 mA XTAL Crystal input or output USB USB pad PHY PHY pad ANA Analog pin PWR 1.5 V (Core) or 3.3 V (I/O) GND Digital Ground (0 V) APWR Analog power (1.5V or 3.3V) AGND Analog ground (0 V) Notes:

1) PAD Types in brackets resemble the logical functionality of a buffer in a certain situation (when a pure input signal is assigned to an IO buffer, the buffer does of course not change in any way, however as its output driver is then automatically disabled, the buffer behaves like an input buffer)



4.4.1 Schematic View of netX Pad Types:

Notes:

1) The IO9, IOU6, IOD9, IOC9, O9, OZ9, I, and IU buffer types are not used in the netX50.

IO9

OUT

OE

IN

I/O

50k

IOU6,IOU9

VDDIO

50k

IN

50k

VDDIO

IN

IU

OUT

OE

IN

I/O

IOD6,IOD9

IN

ID

50k

IN

OUT

OE

IN 5k

IOZUS9

VDDIO

OUT

OE

IN

I/O

(TDBIAC33NN09) (TDBIAC33UN06,TDBIAC33UN09)

(TDBIAC33DN06,TDBIAC33DN09)

OUT OUT

O6,O9

OUT

OE

OUT

OZ6,OZ9(TDOPAC33NN06,TDOPAC33NN09)

(TDOTAC33NN06,TDOTAC33NN09)

(TDBIAC33WN09S)

(TDIPAC33U) (TDIPAC33D)

I/O

IN

50k

VDDIO

IN

IUS

IN

IDS

50k

IN

(TDIPAC33US) (TDIPAC33DS)

I(TDIPAC33N)

IN IN

OUT

OE

IN

IOC9

VDDH

(TDBIAPCUNLP36C)



4.5 Multiplex Matrix Signals

Signal Direction Description Power On

MMIO Mapping Hilscher Default MMIO Mapping

Multiplex Matrix signals (MMIO) CCD Interface CCD_ DATA0 - 7 I CCD Sensor data lines 0 - 7 - MMIO04 -11 CCD_PIXCLK I CCD Sensor pixel clock - MMIO12 CCD_LINE_VALID I CCD Sensor line valid signal - MMIO13 CCD_FRAME_VALID I CCD Sensor frame valid signal - MMIO14 GPIOs / IOLINK GPIO00 - GPIO31 IO General Purpose IOs or IOLINK signal blocks MMIO00 - 31 MMIO00 - 31 I2C I2C_SCL_MMIO IO I2C Interface clock signal - - I2C_SDA_MMIO IO I2C Interface data signal - - MII (Media Independent Interface (Ethernet)) MII_MDC O - - MII_MDIO IO - - MII0_COL I - - MII0_CRS I - - MII0_LED0 I - - MII0_LED1 I - - MII0_LED2 I - - MII0_LED3 I - - MII0_RXCLK I - - MII0_RXD0 I - - MII0_RXD1 I - - MII0_RXD2 I - - MII0_RXD3 I - - MII0_RXDV I - - MII0_RXER I - - - MII0_TXCLK I - - MII0_TXD0 OZ - - MII0_TXD1 OZ - - MII0_TXD2 OZ - - MII0_TXD3 OZ - - MII0_TXEN O - - MII0_TXER O - - MII1_COL I - - MII1_CRS I - - MII1_LED0 I - - MII1_LED1 I - - MII1_LED2 I - - MII1_LED3 I - - MII1_RXCLK I - - MII1_RXD0 I - -





MII1_RXD1 I - - MII1_RXD2 I - - MII1_RXD3 I - - MII1_RXDV I - - MII1_RXER I - - MII1_TXCLK I - - MII1_TXD0 OZ - - MII1_TXD1 OZ - - MII1_TXD2 OZ - - MII1_TXD3 OZ - - MII1_TXEN O - - MII1_TXER O - - PIOs PIO0 - 3 IO Programmable IOs 0 -3 - MMIO28 - 31 PIO4 - 7 IO Programmable IOs 4 -7 - - PHY LEDs PHY0_LED0 - 1 O Status LEDs 0 - 1 of internal PHY0 - MMIO12 - 13 PHY0_LED2 - 3 O Status LEDs 2 - 3 of internal PHY0 - - PHY1_LED0 - 1 O Status LEDs 0 - 1 of internal PHY1 - MMIO14 - 15 PHY1_LED2 - 3 O Status LEDs 2 - 3 of internal PHY1 - - SPI SPI0_CS2n IO Chip Select 2 signal of SPI0 interface - - SPI1_CLK IO Clock signal of SPI1 interface - - SPI1_CS0n IO Chip Select 0 signal of SPI1 interface - - SPI1_CS1n IO Chip Select 1 signal of SPI1 interface - - SPI1_CS2n IO Chip Select 2 signal of SPI1 interface - - SPI1_MISO IO Master In / Slave Out signal of SPI1 interface - - SPI1_MOSI IO Master Out / Slave In signal of SPI1 interface - - UARTs UART0_CTS I UART0 Clear To Send MMIO32 MMIO32 UART0_RTS OZ UART0 Request To Send MMIO33 MMIO33 UART0_RXD I UART0 Receive Data MMIO34 MMIO34 UART0_TXD OZ UART0 Transmit Data MMIO35 MMIO35 UART1_CTS I UART1 Clear To Send - MMIO18 UART1_RTS OZ UART1 Request To Send - MMIO19 UART1_RXD I UART1 Receive Data - MMIO16 UART1_TXD OZ UART1 Transmit Data - MMIO17 UART2_CTS I UART2 Clear To Send - MMIO22 UART2_RTS OZ UART2 Request To Send - MMIO23 UART2_RXD I UART2 Receive Data - MMIO20 UART2_TXD OZ UART2 Transmit Data - MMIO21 USB USB_ID I MMIO36 MMIO36 USB_ID_PU O - MMIO37 USB_RPDEN O - MMIO38 USB_RPUEN O - MMIO39





XMAC0 (Fieldbus 0) XM0_IO0 IO XMAC0 Programmable IO 0 - MMIO03 XM0_IO1 IO XMAC0 Programmable IO 1 - MMIO02 XM0_IO2 - 5 IO XMAC0 Programmable IO2 - 5 - tbd XM0_RX I XMAC0 Receive Data - MMIO00 XM0_TX_OE O XMAC0 Transmit Enable - - XM0_TX_OUT OZ XMAC0 Transmit Data - MMIO01 XMAC1 (Fieldbus 1) XM1_IO0 IO XMAC1 Programmable IO 0 - MMIO07 XM1_IO1 IO XMAC1 Programmable IO 1 - MMIO05 XM1_IO2 - 5 IO XMAC1 Programmable IO2 - 5 - tbd XM1_RX I XMAC1 Receive Data - MMIO06 XM1_TX_OE O XMAC1 Transmit Enable - - XM1_TX_OUT OZ XMAC1 Transmit Data - MMIO04 RTE Sync Signals XC_SAMPLE0 I - MMIO08 XC_SAMPLE1 I - MMIO09 XC_TRIGGER0 OZ - MMIO10 XC_TRIGGER1 OZ - MMIO11



4.6 Pin Table Sorted By Pin Numbers Pin Signal Pin Signal Pin Signal Pin Signal

DPM_D00 B11 TCLK D8 MEM_D28 H5 TMC2 EXT_D00 DPM_A09 D9 MEM_D24 H6 TMC1 A1 PIO83 EXT_A09 D10 MEM_D20 H7 VDDC DPM_SEL_A18

B12 PIO56 DPM_A07 H8 VSS

DPM_D30 DPM_A16 EXT_A07 H9 VSS EXT_CS3n DPM_D20

D11 PIO60 H10 VSS A2

PIO84 EXT_A16 D12 MEM_A15 H11 VSS DPM_D05

B13

PIO58 D13 MEM_A16 H12 VSS EXT_D05 DPM_A14 D14 VSS H13 VSS A3 PIO76 EXT_A14 D15 VSS H14 MEMSR_CS0n

A4 VDDIO B14

PIO54 D16 VSS DPM_D09 A5 VSS DPM_A12 D17 VSS EXT_D09

DPM_D04 EXT_A12 DPM_D14 H15

PIO34 EXT_D04

B15 PIO49 EXT_D14 DPM_D10 A6

PIO77 DPM_CSn D18

PIO42 EXT_D10 DPM_SEL_A17 EXT_CS0n E1 RDY

H16 PIO33

DPM_D29 B16

PIO51 E2 RUN DPM_ALE EXT_CS1n DPM_RDn E3 MEM_DQM3 DPM_D17 A7

PIO80 EXT_RDn E4 MEM_D16 EXT_ALE DPM_D06

B17 PIO52 E5 VSS

H17

PIO35 EXT_D06 DPM_RDY E6 VDDC DPM_SEL_A19 A8 PIO75 EXT_RDY E7 VSS DPM_D18 DPM_SEL_A14

B18 PIO46 E8 MEM_D26 EXT_A24

DPM_D26 C1 RSTOUTn E9 MEM_D25

H18

PIO40 EXT_A22 DPM_D02 E10 MEM_D21 MMIO01 (GPIO01) A9

PIO71 EXT_D02 E11 MEM_D18 XM0_TX DPM_A04

C2 PIO81 E12 MEM_A14

J1 XM0_TX_ECLK

EXT_A04 C3 MEM_D17 E13 MEM_A17 MMIO02 (GPIO02) A10 PIO65 C4 VDDIO E14 VDDC XM0_ECLK DPM_SEL_A13 C5 VSS E15 VDDIO

J2 FB0_CLK

DPM_D25 DPM_D03 E16 VDDIO J3 MEM_A08 EXT_A21 EXT_D03 E17 VDDIO J4 MEM_A11 A11

PIO68 C6

PIO78 E18 VDDIO J5 JT_TRSTn A12 MEM_IF_OM DPM_A00 F1 MEM_A02 J6 TACT_TRST

DPM_A18 DPM_BE0n F2 MEM_A04 J7 VDDC DPM_D22 EXT_A00 F3 MEM_DQM2 J8 VSS EXT_A18

C7

PIO73 F4 MEM_A03 J9 VSS A13

PIO62 DPM_A02 F5 VSS J10 VSS DPM_A17 EXT_A02 F6 VDDC J11 VSS DPM_D21

C8 PIO69 F7 VSS J12 MEMSR_CS2n

EXT_A17 DPM_SEL_A15 F8 MEM_D29 J13 MEMSR_OEn A14

PIO59 DPM_D27 F9 MEM_D23 J14 MEM_A22 DPM_A15 EXT_A23 F10 MEM_D22 J15 MEM_A23 EXT_A15

C9

PIO72 F11 MEM_D19 DPM_D08 A15 PIO55 DPM_A03 F12 VDDIO EXT_D08 DPM_A13 EXT_A03 F13 VDDIO

J16 PIO32

EXT_A13 C10

PIO66 F14 VDDC DPM_D31 A16 PIO48 DPM_A06 F15 VDDC J17 PIO85 DPM_A11 EXT_A06 F16 VDDC DPM_D16 EXT_A11

C11 PIO61 F17 VDDC EN_IN A17

PIO50 DPM_A19 F18 VDDC J18

PIO36 DPM_BHEn DPM_D23 G1 MEM_A05 MMIO05 (GPIO05) DPM_BE1n EXT_A19 G2 MEM_A00 XM1_ECLK EXT_BHEn

C12

PIO63 G3 MEM_A07 K1

FB1_CLK A18

PIO43 DPM_A08 G4 MEM_A01 MMIO04 (GPIO04) B1 PORn EXT_A08 G5 TEST XM1_TX

DPM_D01 C13

PIO57 G6 VDDIO K2

XM1_TX_ECLK EXT_D01 DPM_A10 G7 VDDC K3 MEM_A09 B2 PIO82 EXT_A10 G8 VDDC K4 MEM_A13

B3 MEM_D30 C14

PIO53 G9 VDDIO K5 JT_TCLK B4 VDDIO DPM_WRHn G10 VDDC K6 JT_TMS B5 VSS DPM_BE3n G11 VDDC K7 VDDC

DPM_SEL_A16 EXT_WRHn G12 VDDC K8 VSS DPM_D28

C15

PIO44 G13 VDDC K9 VSS EXT_CS2n DPM_WRLn G14 MEMSR_CS1n K10 VSS B6

PIO79 EXT_WRLn DPM_D13 K11 VSS DPM_D07

C16 PIO45 EXT_D13 K12 MEMSR_WEn

EXT_D07 DPM_INT G15

PIO37 K13 MEM_A21 B7 PIO74 EXT_IRQ DPM_D11 K14 MEM_A20 DPM_A01

C17 PIO47 EXT_D11 K15 PHY1_VSSAT1

DPM_BE2n DPM_D15 G16

PIO39 K16 PHY1_VSSAT2 EXT_A01 EXT_D15 DPM_D19 K17 PHY1_VSSAR B8

PIO70 C18

PIO41 G17 WDGACT K18 PHY_EXTRES DPM_A05 D1 CLKOUT DPM_D12 MMIO06 (GPIO06) EXT_A05 D2 RSTINn EXT_D12

L1 FB0_CLK B9

PIO64 D3 MEM_D31 G18

PIO38 L2 MMIO03 (GPIO03) DPM_SEL_A12 D4 VSS H1 MMIO00 (GPIO00) L3 MEMDR_CKE DPM_D24 D5 VDDIO H2 MEM_A10 L4 MEMDR_CSn EXT_A20 D6 VSS H3 MEM_A12 L5 JT_TDO B10

PIO67 D7 MEM_D27 H4 MEM_A06 L6 JT_TDI



Pin Signal Pin Signal Pin Signal L7 VDDIO R13 MEM_A19 MMIO36 L8 VSS R14 VDDIO ETM_TPKT12 L9 VSS R15 VSS

V13 FO1_EN

L10 VSS R16 VDDC MMIO39 L11 VSS R17 PHY_VSSAT ETM_TPKT15 L12 VDDIO R18 PHY_VDDIOAT

V14 FO01_TD

L13 I2C_SDA T1 MMIO14 (GPIO14) V15 SPI0_CLK L14 I2C_SCL T2 MEM_D09 V16 SPI0_MOSI L15 PHY_ATP T3 VSS V17 VSS L16 PHY1_VDDCART T4 VDDIO V18 VSS L17 PHY1_RXP T5 VSS L18 PHY1_RXN MMIO19 (GPIO19) M1 MMIO08 (GPIO08) T6 ETM_DREQ

MMIO07 (GPIO07) MMIO22 (GPIO22) M2 FB1_CLK

T7 ETM_PSTAT1

M3 MEMDR_RASn T8 USB_VDDIO M4 MEMDR_CLK MMIO28 (GPIO28) M5 MEMDR_CASn

T9 ETM_TPKT04

M6 VDDC MMIO30 (GPIO30) M7 VDDIO T10 ETM_TPKT06

Note: Because of shared signals some Pins ap-pear up to four times in the Pin Table

M8 VDDC MMIO33 (UART0_RTS) M9 VDDIO ETM_TPKT09 M10 VDDC

T11 FO0_RD

M11 VDDC MMIO35 (UART0_TXD) M12 VDDC ETM_TPKT11 M13 VDDC

T12 FO0_TD

M14 PHY_VSSCAP MMIO38 M15 PHY_VDDCAP ETM_TPKT14 M16 PHY_VDDIOAC

T13 FO1_SD

M17 PHY1_TXP T14 SPI0_CS1n M18 PHY1_TXN T15 VDDIO N1 MMIO09 (GPIO09) T16 VSS N2 MMIO10 (GPIO10) T17 VDDC N3 MEMDR_WEn T18 PHY0_VDDCART N4 MEM_DQM1 U1 MMIO13 (GPIO13) N5 VDDC U2 MMIO16 (GPIO16) N6 VDDC U3 VSS N7 VDDC U4 VDDIO N8 MEM_D14 U5 VSS N9 MEM_D00 MMIO21 (GPIO21) N10 MEM_D01 U6 ETM_PSTAT0 N11 MEM_D04 MMIO24 (GPIO24) N12 VDDIO

U7 ETM_TPKT00

N13 VSS U8 USB_DPOS N14 VDDC MMIO27 (GPIO27) N15 PHY0_VSSAT2

U9 ETM_TPKT03

N16 PHY0_VSSAT1 MMIO29 (GPIO29) N17 PHY0_TXP U10 ETM_TPKT05 N18 PHY0_TXN MMIO31 (GPIO31) P1 MMIO11 (GPIO11) U11 ETM_TPKT07 P2 MEM_DQM0 MMIO34 (UART0_RXD) P3 MEM_D07 ETM_TPKT10 P4 VSS

U12 FO0_SD

P5 VDDC MMIO37 P6 VDDC ETM_TPKT13 P7 MEM_D12

U13 FO1_RD

P8 MEM_D15 U14 SPI0_CS0n P9 OSC_VSS U15 SPI0_MISO P10 VSS U16 VDDIO P11 MEM_D03 U17 VSS P12 MEM_A18 U18 VDDC P13 VSS V1 MMIO15 (GPIO15) P14 VSS MMIO17 (GPIO17) P15 VDDC

V2 ETM_TCLK

P16 PHY0_VSSAR MMIO18 (GPIO18) P17 PHY0_RXP V3 ETM_TSYNC P18 PHY0_RXN V4 VDDIO R1 MMIO12 (GPIO12) V5 VSS R2 MEM_D08 MMIO20 (GPIO20) R3 MEM_D06

V6 ETM_DACK

R4 VDDIO MMIO23 (GPIO23) R5 MEM_D10 V7 ETM_PSTAT2 R6 MEM_D11 V8 USB_DNEG R7 MEM_D13 MMIO26 (GPIO26)

MMIO25 (GPIO25) V9 ETM_TPKT02 R8 ETM_TPKT01 V10 OSC_XTI

R9 VDDC V11 OSC_XTO R10 OSC_VDDC MMIO32 (UART0_CTS) R11 MEM_D02 ETM_TPKT08 R12 MEM_D05

V12 FO0_EN



4.7 Pin Table Sorted By Signals

Signal Shared with Signal Shared with Pin Signal Shared with Pin CLKOUT D1 ETM_PSTAT1 MMIO22 T7 FO0_SD ETM_TPKT10 MMIO34 (U0_RXD) U12 ETM_PSTAT2 MMIO23 V7 FO0_TD ETM_TPKT11 MMIO35 (U0_TXD) T12 DPM_A00 DPM_BE0n PIO73 EXT_A00 C7 ETM_TCLK MMIO17 V2 FO1_TD ETM_TPKT15 MMIO39 V14 DPM_A01 DPM_BE2n PIO70 EXT_A01 B8 ETM_TPKT00 MMIO24 U7 FO1_EN ETM_TPKT12 MMIO36 V13 DPM_A02 PIO69 EXT_A02 C8 ETM_TPKT01 MMIO25 R8 FO1_RD ETM_TPKT13 MMIO37 U13 DPM_A03 PIO66 EXT_A03 C10 ETM_TPKT02 MMIO26 V9 FO1_SD ETM_TPKT14 MMIO38 T13 DPM_A04 PIO65 EXT_A04 A10 ETM_TPKT03 MMIO27 U9 DPM_A05 PIO64 EXT_A05 B9 ETM_TPKT04 MMIO28 T9 I2C_SCL L14 DPM_A06 PIO61 EXT_A06 C11 ETM_TPKT05 MMIO29 U10 I2C_SDA L13 DPM_A07 PIO60 EXT_A07 D11 ETM_TPKT06 MMIO30 T10 DPM_A08 PIO57 EXT_A08 C13 ETM_TPKT07 MMIO31 U11 JT_TCLK K5 DPM_A09 PIO56 EXT_A09 B12 ETM_TPKT08 MMIO32 V12 JT_TDI L6 DPM_A10 PIO53 EXT_A10 C14 ETM_TPKT09 FO0_RD MMIO33 (U0_RTS) T11 JT_TDO L5 DPM_A11 PIO50 EXT_A11 A17 ETM_TPKT10 MMIO34 U12 JT_TMS K6 DPM_A12 PIO49 EXT_A12 B15 ETM_TPKT11 FO0_TD MMIO35 (U0_RTS) T12 JT_TRSTn J5 DPM_A13 PIO48 EXT_A13 A16 ETM_TPKT12 MMIO36 V13 DPM_A14 PIO54 EXT_A14 B14 ETM_TPKT13 MMIO37 U13 MEM_A00 G2 DPM_A15 PIO55 EXT_A15 A15 ETM_TPKT14 MMIO38 T13 MEM_A01 G4 DPM_A16 DPM_D20 PIO58 EXT_A16 B13 ETM_TPKT15 MMIO39 V14 MEM_A02 F1 DPM_A17 DPM_D21 PIO59 EXT_A17 A14 ETM_TSYNC MMIO18 V3 MEM_A03 F4 DPM_A18 DPM_D22 PIO62 EXT_A18 A13 EXT_A00 PIO73 DPM_A00 C7 MEM_A04 F2 DPM_A19 DPM_D23 PIO63 EXT_A19 C12 EXT_A01 PIO70 DPM_A01 B8 MEM_A05 G1 DPM_ALE DPM_D17 PIO35 EXT_ALE H17 EXT_A02 PIO69 DPM_A02 C8 MEM_A06 H4 DPM_BE0n DPM_A00 PIO73 EXT_A00 C7 EXT_A03 PIO66 DPM_A03 C10 MEM_A07 G3 DPM_BE1n DPM_BHEn PIO43 EXT_BHEn A18 EXT_A04 PIO65 DPM_A04 A10 MEM_A08 J3 DPM_BE2n DPM_A01 PIO70 EXT_A01 B8 EXT_A05 PIO64 DPM_A05 B9 MEM_A09 K3 DPM_BE3n DPM_WRHn PIO44 EXT_WRHn C15 EXT_A06 PIO61 DPM_A06 C11 MEM_A10 H2 DPM_BHEn DPM_BHE1n PIO43 EXT_BHEn A18 EXT_A07 PIO60 DPM_A07 D11 MEM_A11 J4 DPM_CSn PIO51 EXT_CS0n B16 EXT_A08 PIO57 DPM_A08 C13 MEM_A12 H3 DPM_D00 PIO83 EXT_D00 A1 EXT_A09 PIO56 DPM_A09 B12 MEM_A13 K4 DPM_D01 PIO82 EXT_D01 B2 EXT_A10 PIO53 DPM_A10 C14 MEM_A14 E12 DPM_D02 PIO81 EXT_D02 C2 EXT_A11 PIO50 DPM_A11 A17 MEM_A15 D12 DPM_D03 PIO78 EXT_D03 C6 EXT_A12 PIO49 DPM_A12 B15 MEM_A16 D13 DPM_D04 PIO77 EXT_D04 A6 EXT_A13 PIO48 DPM_A13 A16 MEM_A17 E13 DPM_D05 PIO76 EXT_D05 A3 EXT_A14 PIO54 DPM_A14 B14 MEM_A18 P12 DPM_D06 PIO75 EXT_D06 A8 EXT_A15 PIO55 DPM_A15 A15 MEM_A19 R13 DPM_D07 PIO74 EXT_D07 B7 EXT_A16 PIO58 DPM_A16 B13 MEM_A20 K14 DPM_D08 PIO32 EXT_D08 J16 EXT_A17 PIO59 DPM_A17 A14 MEM_A21 K13 DPM_D09 PIO34 EXT_D09 H15 EXT_A18 PIO62 DPM_A18 A13 MEM_A22 J14 DPM_D10 PIO33 EXT_D10 H16 EXT_A19 PIO63 DPM_A19 C12 MEM_A23 J15 DPM_D11 PIO39 EXT_D11 G16 EXT_A20 DPM_D24 PIO67 DPM_SELA12 B10 MEM_D00 N9 DPM_D12 PIO38 EXT_D12 G18 EXT_A21 DPM_D25 PIO68 DPM_SELA13 A11 MEM_D01 N10 DPM_D13 PIO37 EXT_D13 G15 EXT_A22 DPM_D26 PIO71 DPM_SELA14 A9 MEM_D02 R11 DPM_D14 PIO42 EXT_D14 D18 EXT_A23 DPM_D27 PIO72 DPM_SELA15 C9 MEM_D03 P11 DPM_D15 PIO41 EXT_D15 C18 EXT_A24 DPM_D18 PIO40 DPM_SELA19 H18 MEM_D04 N11 DPM_D16 EN_IN PIO36 EN_IN J18 EXT_ALE DPM_D17 PIO35 DPM_ALE H17 MEM_D05 R12 DPM_D17 DPM_ALE PIO35 EXT_ALE H17 EXT_BHEn DPM_BE1n PIO43 DPM_BHEn A18 MEM_D06 R3 DPM_D18 DPM_SELA19 PIO40 EXT_A24 H18 EXT_CS0n PIO51 DPM_CSn B16 MEM_D07 P3 DPM_D19 WDGACT G17 EXT_CS1n DPM_D29 PIO80 DPM_SELA17 A7 MEM_D08 R2 DPM_D20 DPM_A16 PIO58 EXT_A16 B13 EXT_CS2n DPM_D28 PIO79 DPM_SELA16 B6 MEM_D09 T2 DPM_D21 DPM_A17 PIO59 EXT_A17 A14 EXT_CS3n DPM_D30 PIO84 DPM_SELA18 A2 MEM_D10 R5 DPM_D22 DPM_A18 PIO62 EXT_A18 A13 EXT_D00 PIO83 DPM_D00 A1 MEM_D11 R6 DPM_D23 DPM_A19 PIO63 EXT_A19 C12 EXT_D01 PIO82 DPM_D01 B2 MEM_D12 P7 DPM_D24 DPM_SELA12 PIO67 EXT_A20 B10 EXT_D02 PIO81 DPM_D02 C2 MEM_D13 R7 DPM_D25 DPM_SELA13 PIO68 EXT_A21 A11 EXT_D03 PIO78 DPM_D03 C6 MEM_D14 N8 DPM_D26 DPM_SELA14 PIO71 EXT_A22 A9 EXT_D04 PIO77 DPM_D04 A6 MEM_D15 P8 DPM_D27 DPM_SELA15 PIO72 EXT_A23 C9 EXT_D05 PIO76 DPM_D05 A3 MEM_D16 E4 DPM_D28 DPM_SELA16 PIO79 EXT_CS2n B6 EXT_D06 PIO75 DPM_D06 A8 MEM_D17 C3 DPM_D29 DPM_SELA17 PIO80 EXT_CS1n A7 EXT_D07 PIO74 DPM_D07 B7 MEM_D18 E11 DPM_D30 DPM_SELA18 PIO84 EXT_CS3n A2 EXT_D08 PIO32 DPM_D08 J16 MEM_D19 F11 DPM_D31 PIO85 J17 EXT_D09 PIO34 DPM_D09 H15 MEM_D20 D10 DPM_INT PIO47 EXT_IRQ C17 EXT_D10 PIO33 DPM_D10 H16 MEM_D21 E10 DPM_RDn PIO52 EXT_RDn B17 EXT_D11 PIO39 DPM_D11 G16 MEM_D22 F10 DPM_RDY PIO46 EXT_RDY B18 EXT_D12 PIO38 DPM_D12 G18 MEM_D23 F9 DPM_SELA12 DPM_D24 PIO67 EXT_A20 B10 EXT_D13 PIO37 DPM_D13 G15 MEM_D24 D9 DPM_SELA13 DPM_D25 PIO68 EXT_A21 A11 EXT_D14 PIO42 DPM_D14 D18 MEM_D25 E9 DPM_SELA14 DPM_D26 PIO71 EXT_A22 A9 EXT_D15 PIO41 DPM_D15 C18 MEM_D26 E8 DPM_SELA15 DPM_D27 PIO72 EXT_A23 C9 EXT_IRQ PIO47 DPM_INT C17 MEM_D27 D7 DPM_SELA16 DPM_D28 PIO79 EXT_CS2n B6 EXT_RDn PIO52 DPM_RDn B17 MEM_D28 D8 DPM_SELA17 DPM_D29 PIO80 EXT_CS1n A7 EXT_RDY PIO46 DPM_RDY B18 MEM_D29 F8 DPM_SELA18 DPM_D30 PIO84 EXT_CS3n A2 EXT_WRHn PIO44 DPM_WRHn C15 MEM_D30 B3 DPM_SELA19 DPM_D18 PIO40 EXT_A24 H18 EXT_WRLn PIO45 DPM_WRLn C16 MEM_D31 D3 DPM_WRHn DPM_BE3n PIO44 EXT_WRHn C15 MEM_DQM0 P2 DPM_WRLn PIO45 EXT_WRLn C16 MMIO06 L1 MEM_DQM1 N4 FB0_CLK

XM0_ECLK MMIO02 J2 MEM_DQM2 F3 EN_IN DPM_D16 PIO36 J18 MMIO07 M2 MEM_DQM3 E3 ETM_DACK MMIO20 V6

FB1_CLK XM1_ECLK MMIO05 K1 MEMDR_CASn M5

ETM_DREQ MMIO19 T6 FO0_EN ETM_TPKT08 MMIO32 (U0_CTS) V12 MEMDR_CKE L3 ETM_PSTAT0 MMIO21 U6 FO0_RD ETM_TPKT09 MMIO33 (U0_RTS) T11 MEMDR_CLK M4



Signal Shared with Pin Signal Shared with Pin Signal Shared with Pin MEMDR_CSn L4 PIO32 DPM_D08 EXT_D08 J16 XM0_ECLK FB0_CLK MMIO02 J2 MEMDR_RASn M3 PIO33 DPM_D10 EXT_D10 H16 XM0_TX XM0_TX_ECLK MMIO01 J1 MEMDR_WEn N3 PIO34 DPM_D09 EXT_D09 H15 XM0_TX_ECLK XM0_TX MMIO01 J1 MEMSR_CS0n H14 PIO35 DPM_D17 DPM_ALE EXT_ALE H17 XM1_ECLK FB1_CLK MMIO05 K1 MEMSR_CS1n G14 PIO36 DPM_D16 EN_IN EN_IN J18 XM1_TX XM1_TX_ECLK MMIO04 K2 MEMSR_CS2n J12 PIO37 DPM_D13 EXT_D13 G15 XM1_TX_ECLK XM1_TX MMIO04 K2 MEMSR_OEn J13 PIO38 DPM_D12 EXT_D12 G18 MEMSR_WEn K12 PIO39 DPM_D11 EXT_D11 G16 MEM_IF_OM A12 PIO40 DPM_D18 DPM_SELA19 EXT_A24 H18

PIO41 DPM_D15 EXT_D15 C18 All signals in brackets indicate

Power Up functions of MMIO pins.

MMIO00 (GPIO00) H1 PIO42 DPM_D14 EXT_D14 D18 MMIO01 XM0_TX XM0_TX_ECLK (GPIO01) J1 PIO43 DPM_BE1n DPM_BHEn EXT_BHEn A18 MMIO02 XM0_ECLK FB0_CLK (GPIO02) J2 PIO44 DPM_BE3n DPM_WRHn EXT_WRHn C15 MMIO03 (GPIO03) L2 PIO45 DPM_WRLn EXT_WRLn C16 MMIO04 XM1_TX XM1_TX_ECLK (GPIO04) K2 PIO46 DPM_RDY EXT_RDY B18 MMIO05 XM1_ECLK FB1_CLK (GPIO05) K1 PIO47 DPM_INT EXT_IRQ C17 MMIO06 FB0_CLK (GPIO06) L1 PIO48 DPM_A13 EXT_A13 A16 MMIO07 FB1_CLK (GPIO07) M2 PIO49 DPM_A12 EXT_A12 B15 MMIO08 (GPIO08) M1 PIO50 DPM_A11 EXT_A11 A17 MMIO09 (GPIO09) N1 PIO51 DPM_CSn EXT_CS0n B16 MMIO10 (GPIO10) N2 PIO52 DPM_RDn EXT_RDn B17 MMIO11 (GPIO11) P1 PIO53 DPM_A10 EXT_A10 C14 MMIO12 (GPIO12) R1 PIO54 DPM_A14 EXT_A14 B14 MMIO13 (GPIO13) U1 PIO55 DPM_A15 EXT_A15 A15 MMIO14 (GPIO14) T1 PIO56 DPM_A09 EXT_A09 B12 MMIO15 (GPIO15) V1 PIO57 DPM_A08 EXT_A08 C13 MMIO16 (GPIO16) U2 PIO58 DPM_D20 DPM_A16 EXT_A16 B13 MMIO17 ETM_TCLK (GPIO17) V2 PIO59 DPM_D21 DPM_A17 EXT_A17 A14 MMIO18 ETM_TSYNC (GPIO18) V3 PIO60 EXT_A07 DPM_A07 D11 MMIO19 ETM_DREQ (GPIO19) T6 PIO61 EXT_A06 DPM_A06 C11 MMIO20 ETM_DACK (GPIO20) V6 PIO62 DPM_D22 EXT_A18 DPM_A18 A13 MMIO21 ETM_PSTAT0 (GPIO21) U6 PIO63 DPM_D23 EXT_A19 DPM_A19 C12 MMIO22 ETM_PSTAT1 (GPIO22) T7 PIO64 EXT_A05 DPM_A05 B9 MMIO23 ETM_PSTAT2 (GPIO23) V7 PIO65 EXT_A04 DPM_A04 A10 MMIO24 ETM_TPKT00 (GPIO24) U7 PIO66 EXT_A03 DPM_A03 C10 MMIO25 ETM_TPKT01 (GPIO25) R8 PIO67 DPM_D24 EXT_A20 DPM_SELA12 B10 MMIO26 ETM_TPKT02 (GPIO26) V9 PIO68 DPM_D25 EXT_A21 DPM_SELA13 A11 MMIO27 ETM_TPKT03 (GPIO27) U9 PIO69 EXT_A02 DPM_A02 C8 MMIO28 ETM_TPKT04 (GPIO28) T9 PIO70 DPM_BE2n EXT_A01 DPM_A01 B8 MMIO29 ETM_TPKT05 (GPIO29) U10 PIO71 DPM_D26 EXT_A22 DPM_SELA14 A9 MMIO30 ETM_TPKT06 (GPIO30) T10 PIO72 DPM_D27 DPM_SELA15 EXT_A23 C9 MMIO31 ETM_TPKT07 (GPIO31) U11 PIO73 DPM_BE0n DPM_A00 EXT_A00 C7 MMIO32 ETM_TPKT08 FO0_EN (U0_CTS) V12 PIO74 DPM_D07 EXT_D07 B7 MMIO33 ETM_TPKT09 FO0_RD (U0_RTS) T11 PIO75 DPM_D06 EXT_D06 A8 MMIO34 ETM_TPKT10 FO0_SD (U0_RXD) U12 PIO76 DPM_D05 EXT_D05 A3 MMIO35 ETM_TPKT11 FO0_TD (U0_TXD) T12 PIO77 DPM_D04 EXT_D04 A6 MMIO36 ETM_TPKT12 FO1_EN USB_ID V13 PIO78 DPM_D03 EXT_D03 C6 MMIO37 ETM_TPKT13 FO1_RD U13 PIO79 DPM_D28 DPM_SELA16 EXT_CS2n B6 MMIO38 ETM_TPKT14 FO1_SD T13 PIO80 DPM_D29 DPM_SELA17 EXT_CS1n A7 MMIO39 ETM_TPKT15 FO1_TD V14 PIO81 DPM_D02 EXT_D02 C2 PIO82 DPM_D01 EXT_D01 B2 OSC_VDDC R10 PIO83 DPM_D00 EXT_D00 A1 OSC_VSS P9 PIO84 DPM_D30 DPM_SELA18 EXT_CS3n A2 OSC_XTI V10 PIO85 DPM_D31 J17 OSC_XTO V11 PORn B1 PHY_ATP L15 PHY_EXTRES K18 RDY E1 PHY_VDDCAP M15 RSTINn D2 PHY_VDDIOAC

M16 RSTOUTn

C1

PHY_VDDIOAT R18 RUN E2 PHY_VSSCAP M14 Signal Pins PHY_VSSAT R17 SPI0_CLK V15 PHY0_RXN P18 SPI0_CS0n U14 PHY0_RXP P17 SPI0_CS1n T14 PHY0_TXN N18 SPI0_MISO U15 PHY0_TXP N17 SPI0_MOSI V16

VDDIO

A4, B4, C4, D5, E15, E16, E17, E18, F12, F13, G6, G9, L7, L12, M7, M9, N12, R4, R14, T4, T15, U4, U16, V4

PHY0_VDDCART

T18

PHY0_VSSAR P16 TACT_TRST J6

PHY0_VSSAT1 N16 TCLK B11 PHY0_VSSAT2 N15 TEST G5 PHY1_RXN L18 TMC1 H6 PHY1_RXP L17 TMC2 H5

VDDC

E6, E14, F6, F14, F15, F16, F17, F18, G7, G8, G10, G11, G12, G13, H7, J7, K7, M6, M8, M10, M11, M12, M13, N5, N6, N7, N14, P5, P6, P15, R9, R16, T17, U18

PHY1_TXN M18

PHY1_TXP M17 USB_DNEG V8 PHY1_VDDCART

L16 USB_DPOS

U8

PHY1_VSSAR K17 USB_VDDIO T8 PHY1_VSSAT1 K15 PHY1_VSSAT2 K16 WDGACT DPM_D19 G17

VSS

A5, B5, C5, D4, D6, D14, D15, D16, D17, E5, E7, F5, F7, H8, H9, H10, H11, H12, H13, J8, J9, J10, J11, K8, K9, K10, K11, L8, L9, L10, L11, N13, P4, P10, P13, P14, R15, T3, T5, T16, U3, U5, U17, V5, V17, V18

Note: Because of shared signals some Pins appears up to three times at the Pin Table.



4.8 Pin overview

4.8.1 Overview 1 (unmarked)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

A DPM_D00 EXT_D00

PIO83

DPM_SELA18 DPM_D30 EXT_CS3n

PIO84

DPM_D05 EXT_D05

PIO76 VDDIO VSS

DPM_D04 EXT_D04

PIO77


PIO80

DPM_D06 EXT_D06

PIO75

DPM_SELA14 DPM_D26 EXT_A22

PIO71

DPM_A04 EXT_A04

PIO65


PIO68

MEM_IF_OM

DPM_A18 DPM_D22 EXT_A18

PIO62


PIO59

DPM_A15 EXT_A15

PIO55

DPM_A13 EXT_A13

PIO48

DPM_A11 EXT_A11

PIO50

DPM_BHEn DPM_BE1n EXT_BHEn

PIO43

B PORn DPM_D01 EXT_D01

PIO82 MEM_D30 VDDIO VSS


PIO79

DPM_D07 EXT_D07

PIO74

DPM_A01 DPM_BE2n EXT_A01

PIO70

DPM_A05 EXT_A05

PIO64


PIO67

TCLK DPM_A09 EXT_A09

PIO56


PIO58

DPM_A14 EXT_A14

PIO54

DPM_A12 EXT_A12

PIO49

DPM_CSn EXT_CS0n

PIO51

DPM_RDn EXT_RDn

PIO52

DPM_RDY EXT_RDY

PIO46

C RSTOUTn DPM_D02 EXT_D02


DPM_D03 EXT_D03

PIO78


PIO73

DPM_A02 EXT_A02

PIO69


PIO72

DPM_A03 EXT_A03

PIO66

DPM_A06 EXT_A06

PIO61


PIO63

DPM_A08 EXT_A08

PIO57

DPM_A10 EXT_A10

PIO53

DPM_WRHn DPM_BE3n EXT_WRHn

PIO44

DPM_WRLn EXT_WRLn

PIO45

DPM_INT EXT_IRQ

PIO47

DPM_D15 EXT_D15

PIO41

D CLKOUT RSTINn MEM_D31 VSS VDDIO VSS MEM_D27 MEM_D28 MEM_D24 MEM_D20 DPM_A07 EXT_A07

PIO60 MEM_A15 MEM_A16 VSS VSS VSS VSS

DPM_D14 EXT_D14

PIO42

E RDY RUN MEM_DQM3 MEM_D16 VSS VDDC VSS MEM_D26 MEM_D25 MEM_D21 MEM_D18 MEM_A14 MEM_A17 VDDC VDDIO VDDIO VDDIO VDDIO

F MEM_A02 MEM_A04 MEM_DQM2 MEM_A03 VSS VDDC VSS MEM_D29 MEM_D23 MEM_D22 MEM_D19 VDDIO VDDIO VDDC VDDC VDDC VDDC VDDC

G MEM_A05 MEM_A00 MEM_A07 MEM_A01 TEST VDDIO VDDC VDDC VDDIO VDDC VDDC VDDC VDDC MEMSR_CS1n DPM_D13 EXT_D13

PIO37

DPM_D11 EXT_D11

PIO39

DPM_D19 WDGACT

DPM_D12 EXT_D12

PIO38

H MMIO00 MEM_A10 MEM_A12 MEM_A06 TMC2 TMC1 VDDC VSS VSS VSS VSS VSS VSS MEMSR_CS0n DPM_D09 EXT_D09

PIO34

DPM_D10 EXT_D10

PIO33

DPM_ALE DPM_D17 EXT_ALE

PIO35

DPM_SELA19DPM_D18 EXT_A24

PIO40

J MMIO01 XM0_TX

XM0_TX_ECK

MMIO02 XM0_ECLK FB0_CLK

MEM_A08 MEM_A11 JT_TRSTn TACT_TRST VDDC VSS VSS VSS VSS MEMSR_CS2n MEMSR_OEn MEM_A22 MEM_A23 DPM_D08 EXT_D08

PIO32

DPM_D31 PIO85

DPM_D16 EN_IN PIO36

K MMIO05

XM1_ECLK FB1_CLK

MMIO04 XM1_TX

XM1_TX_ECK MEM_A09 MEM_A13 JT_TCLK JT_TMS VDDC VSS VSS VSS VSS MEMSR_WEn MEM_A21 MEM_A20 PHY1_VSSAT1 PHY1_VSSAT2 PHY1_VSSAR PHY_EXTRES

L MMIO06 FB0_CLK MMIO03 MEMDR_CKE MEMDR_CSn JT_TDO JT_TDI VDDIO VSS VSS VSS VSS VDDIO I2C_SDA 2C_SCL PHY_ATP PHY1_VDDCA

RT PHY1_RXP PHY1_RXN

M MMIO08 MMIO07 FB1_CLK MEMDR_RASn MEMDR_CLK MEMDR_CASn VDDC VDDIO VDDC VDDIO VDDC VDDC VDDC VDDC PHY_VSSCAP PHY_VDDCAP PHY_VDDIOAC PHY1_TXP PHY1_TXN

N MMIO09 MMIO10 MEMDR_WEn MEM_DQM1 VDDC VDDC VDDC MEM_D14 MEM_D00 MEM_D01 MEM_D04 VDDIO VSS VDDC PHY0_VSSAT2 PHY0_VSSAT1 PHY0_TXP PHY0_TXN

P MMIO11 MEM_DQM0 MEM_D07 VSS VDDC VDDC MEM_D12 MEM_D15 OSC_VSS VSS MEM_D03 MEM_A18 VSS VSS VDDC PHY0_VSSAR PHY0_RXP PHY0_RXN

R MMIO12 MEM_D08 MEM_D06 VDDIO MEM_D10 MEM_D11 MEM_D13 MMIO25 ETM_TPKT01 VDDC OSC_VDDC MEM_D02 MEM_D05 MEM_A19 VDDIO VSS VDDC PHY_VSSAT PHY_VDDIOAT

T MMIO14 MEM_D09 VSS VDDIO VSS MMIO19 ETM_DREQ

MMIO22 ETM_PSTAT1 USB_VDDIO MMIO28

ETM_TPKT04 MMIO30

ETM_TPKT06

MMIO33 ETM_TPKT09

FO0_RD

MMIO35 ETM_TPKT11

FO0_TD

MMIO38 ETM_TPKT14

FO1_SD SPI0_CS1n VDDIO VSS VDDC PHY0_VDDCA

RT

U MMIO13 MMIO16 VSS VDDIO VSS MMIO21 ETM_PSTAT0

MMIO24 ETM_TPKT00 USB_DPOS MMIO27

ETM_TPKT03 MMIO29

ETM_TPKT05 MMIO31

ETM_TPKT07

MMIO34 ETM_TPKT10

FO0_SD

MMIO37 ETM_TPKT13

FO1_RD SPI0_CS0n SPI0_MISO VDDIO VSS VDDC

V MMIO15 MMIO17 ETM_TCLK

MMIO18 ETM_TSYNC VDDIO VSS MMIO20

ETM_DACK MMIO23

ETM_PSTAT2 USB_DNEG MMIO26 ETM_TPKT02 OSC_XTI OSC_XTO

MMIO32 ETM_TPKT08

FO0_EN

MMIO36 ETM_TPKT12

FO1_EN

MMIO39 ETM_TPKT15

FO01_TD SPI0_CLK SPI0_MOSI VSS VSS

Pinning netX 50 Top view



4.8.2 Overview 2 (digital power pins marked)

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

A DPM_D00 EXT_D00

PIO83


PIO84

DPM_D05 EXT_D05

PIO76 VDDIO VSS

DPM_D04 EXT_D04

PIO77


PIO80

DPM_D06 EXT_D06

PIO75


PIO71

DPM_A04 EXT_A04

PIO65


PIO68

MEM_IF_OM


PIO62


PIO59

DPM_A15 EXT_A15

PIO55

DPM_A13 EXT_A13

PIO48

DPM_A11 EXT_A11

PIO50

DPM_BHEn DPM_BE1n EXT_BHEn

PIO43

B PORn DPM_D01 EXT_D01



PIO79

DPM_D07 EXT_D07

PIO74


PIO70

DPM_A05 EXT_A05

PIO64


PIO67

TCLK DPM_A09 EXT_A09

PIO56


PIO58

DPM_A14 EXT_A14

PIO54

DPM_A12 EXT_A12

PIO49

DPM_CSn EXT_CS0n

PIO51

DPM_RDn EXT_RDn

PIO52

DPM_RDY EXT_RDY

PIO46

C RSTOUTn DPM_D02 EXT_D02


DPM_D03 EXT_D03

PIO78


PIO73

DPM_A02 EXT_A02

PIO69


PIO72

DPM_A03 EXT_A03

PIO66

DPM_A06 EXT_A06

PIO61


PIO63

DPM_A08 EXT_A08

PIO57

DPM_A10 EXT_A10

PIO53

DPM_WRHn DPM_BE3n EXT_WRHn

PIO44

DPM_WRLn EXT_WRLn

PIO45

DPM_INT EXT_IRQ

PIO47

DPM_D15 EXT_D15

PIO41

D CLKOUT RSTINn MEM_D31 VSS VDDIO VSS MEM_D27 MEM_D28 MEM_D24 MEM_D20 DPM_A07 EXT_A07

PIO60 MEM_A15 MEM_A16 VSS VSS VSS VSS

DPM_D14 EXT_D14

PIO42

E RDY RUN MEM_DQM3 MEM_D16 VSS VDDC VSS MEM_D26 MEM_D25 MEM_D21 MEM_D18 MEM_A14 MEM_A17 VDDC VDDIO VDDIO VDDIO VDDIO

F MEM_A02 MEM_A04 MEM_DQM2 MEM_A03 VSS VDDC VSS MEM_D29 MEM_D23 MEM_D22 MEM_D19 VDDIO VDDIO VDDC VDDC VDDC VDDC VDDC

G MEM_A05 MEM_A00 MEM_A07 MEM_A01 TEST VDDIO VDDC VDDC VDDIO VDDC VDDC VDDC VDDC MEMSR_CS1n DPM_D13 EXT_D13

PIO37

DPM_D11 EXT_D11

PIO39

DPM_D19 WDGACT

DPM_D12 EXT_D12

PIO38

H MMIO00 MEM_A10 MEM_A12 MEM_A06 TMC2 TMC1 VDDC VSS VSS VSS VSS VSS VSS MEMSR_CS0n DPM_D09 EXT_D09

PIO34

DPM_D10 EXT_D10

PIO33

DPM_ALE DPM_D17 EXT_ALE

PIO35

DPM_SELA19DPM_D18 EXT_A24

PIO40

J MMIO01 XM0_TX

XM0_TX_ECK

MMIO02 XM0_ECLK FB0_CLK

MEM_A08 MEM_A11 JT_TRSTn TACT_TRST VDDC VSS VSS VSS VSS MEMSR_CS2n MEMSR_OEn MEM_A22 MEM_A23 DPM_D08 EXT_D08

PIO32

DPM_D31 PIO85

DPM_D16 EN_IN PIO36

K MMIO05

XM1_ECLK FB1_CLK

MMIO04 XM1_TX

XM1_TX_ECK MEM_A09 MEM_A13 JT_TCLK JT_TMS VDDC VSS VSS VSS VSS MEMSR_WEn MEM_A21 MEM_A20 PHY1_VSSAT1 PHY1_VSSAT2 PHY1_VSSAR PHY_EXTRES

L MMIO06 FB0_CLK MMIO03 MEMDR_CKE MEMDR_CSn JT_TDO JT_TDI VDDIO VSS VSS VSS VSS VDDIO I2C_SDA 2C_SCL PHY_ATP PHY1_VDDCA

RT PHY1_RXP PHY1_RXN

M MMIO08 MMIO07 FB1_CLK MEMDR_RASn MEMDR_CLK MEMDR_CASn VDDC VDDIO VDDC VDDIO VDDC VDDC VDDC VDDC PHY_VSSCAP PHY_VDDCAP PHY_VDDIOAC PHY1_TXP PHY1_TXN

N MMIO09 MMIO10 MEMDR_WEn MEM_DQM1 VDDC VDDC VDDC MEM_D14 MEM_D00 MEM_D01 MEM_D04 VDDIO VSS VDDC PHY0_VSSAT2 PHY0_VSSAT1 PHY0_TXP PHY0_TXN

P MMIO11 MEM_DQM0 MEM_D07 VSS VDDC VDDC MEM_D12 MEM_D15 OSC_VSS VSS MEM_D03 MEM_A18 VSS VSS VDDC PHY0_VSSAR PHY0_RXP PHY0_RXN

R MMIO12 MEM_D08 MEM_D06 VDDIO MEM_D10 MEM_D11 MEM_D13 MMIO25 ETM_TPKT01 VDDC OSC_VDDC MEM_D02 MEM_D05 MEM_A19 VDDIO VSS VDDC PHY_VSSAT PHY_VDDIOAT

T MMIO14 MEM_D09 VSS VDDIO VSS MMIO19 ETM_DREQ

MMIO22 ETM_PSTAT1 USB_VDDIO MMIO28

ETM_TPKT04 MMIO30

ETM_TPKT06

MMIO33 ETM_TPKT09

FO0_RD

MMIO35 ETM_TPKT11

FO0_TD

MMIO38 ETM_TPKT14

FO1_SD SPI0_CS1n VDDIO VSS VDDC PHY0_VDDCA

RT

U MMIO13 MMIO16 VSS VDDIO VSS MMIO21 ETM_PSTAT0

MMIO24 ETM_TPKT00 USB_DPOS MMIO27

ETM_TPKT03 MMIO29

ETM_TPKT05 MMIO31

ETM_TPKT07

MMIO34 ETM_TPKT10

FO0_SD

MMIO37 ETM_TPKT13

FO1_RD SPI0_CS0n SPI0_MISO VDDIO VSS VDDC

V MMIO15 MMIO17 ETM_TCLK

MMIO18 ETM_TSYNC VDDIO VSS MMIO20

ETM_DACK MMIO23

ETM_PSTAT2 USB_DNEG MMIO26 ETM_TPKT02 OSC_XTI OSC_XTO

MMIO32 ETM_TPKT08

FO0_EN

MMIO36 ETM_TPKT12

FO1_EN

MMIO39 ETM_TPKT15

FO01_TD SPI0_CLK SPI0_MOSI VSS VSS

Pinning netX 50 Top view



4.9 Mechanical Dimensions / Physical Dimensions

The netX 50 comes in a 324 pin PBGA package. Mechanical Dimensions of the netX 50

Symbol Min. Typ. Max. A1 0.40 mm 0.50 mm 0.60 mm A2 1.33 mm b 0.50 mm 0.60 mm 0.70 mm E 18.90 mm 19.00 mm 19.10 mm e 1.00 mm D 18.90 mm 19.00 mm 19.10 mm



4.10 Material composition

4.10.1 Solder balls

Solder ball weight: 307 mg Material CAS No. Amount per ball Concentration Copper 7440-50-8 1.54 mg ~ 0.5% Tin 7440-31-5 296.25 mg ~ 96.5 % Silver 7440-22-4 9.21 mg ~ 3 %

4.11 Ordering Information

Ordering Number: 2230.000 NETX 50 netX 50 Network Controller (single chip) 2230.100 NETX 50 (BOX) - / - 15 pcs. 2230.200 NETX 50 (TRAY) - / - 70 pcs. 2230.300 NETX 50 (PACKAGE) - / - 350 pcs.

netX50 Technical Data Reference Guide Printed Circuit Board Design • 166


5 Printed Circuit Board Design

Coming in a PBGA package, the netX requires the use of small traces and vias on the PCB. Designs using external memory (SDRAM or PFLASH) will require the use of 4 signal layers along with 6 mil standard technology to be able to fan out all signals. However, designs using internal RAM only, might be realized with two signal layers as the SDRAM signal balls reside on the inner ball rings of the pack-age. Standard “dog bone style” routing as shown below can be used to fan out the netX50 signals.

Dimension Description mm mil c Clearance 0,15 6 e Pitch 1,00 39.37 p Pad 0,45 18 t Trace Width 0.15 6 v Via Diameter 0,50 20 w Drill Hole 0,20 8 PCB max. width 2,00 79

Note: Vias within the chip footprint area should be exactly centered between the pins to avoid possible solder-ing problems during manufacturing!

netX50 Technical Data Reference Guide Reference PCB Layout Design • 167


5.1 Routing hints

When routing the netX traces keep in mind, that there are some critical signal pairs. Especially the Ethernet differential pairs must be routed close to each other and must be of equal length. Care must be taken when routing the SDRAM interface lines. The SDRAM clock line is a 100 MHz sig-nal line and all the SDRAM bus lines should have equal length and capacitive load. The use of 32 Bit SDRAMs instead of 16 Bit RAM pairs is mandatory due to the limited driving capability of the SDRAM interface pins. For some applications, serial impedance matching resistors for all SDRAM signals may be required to maintain signal quality. We strongly recommend the use of CAD systems, that support impedance controlled routing to detect and eliminate signal integrity problems in the first place. The main quartz oscillator must be placed close to the netX chip, allowing the signal lines to be directly connected to the netX by short traces. Generally, netX power connections must be as short as possible.

5.2 Vcc Pin Requirements / Decoupling Capacitors

Since only some of the power pins of the netX 50 are located on the outer ball ring, part of the power pins must be supplied by internal planes, which should be decoupled properly (on PCBs with double sided mounting, the decoupling capacitors for the inner pins should be placed on the bottom side, close to the pins). Recommended decoupling capacitor types are X7R ceramic type with 100 nF / 6.3 V, which are avail-able in 0603 package. Additionaly, X5R or X7R ceramic capacitors of 10 uF / 6.3 V can be used. They are available in 1206 or 0805 package.

6 Reference PCB Layout Design

An appropriate reference design has not yet been published. It will be downloadable from the Hilscher website (netX Downloads at www.hilscher.com ) as soon as available.


netX50 Technical Data Reference Guide Reference Schematics • 168


7 Reference Schematics

Appropriate reference schematics have not yet been published. They will be downloadable from the Hilscher website (netX Downloads at www.hilscher.com ) as soon as available. However, the schemat-ics for the NXHX50-RE (netX50 Evaluationboard) are available for download.


netX50 Technical Data Reference Guide Revision History • 169


8 Revision History

Rev. Date Changes Who 0.1 18-06-2007 created JL 0.9 11-11-2007 Preliminary Release HJH 1.0 17-12-2007 Revised and amended (all chapters) JL 29-05-2008 Chapter 2.10.11 corrected diagram (was the same as in 2.20.20) JL 29-05-2008 Chapter 1, corrected data TCM size to 8KB (previously stated as 4KB) JL 29-05-2008 Chapter 1, corrected Prod. Feature List (ARM 966 does not provide

Jazelle hardware feature) JL

30-05-2008 Chapter 3.2, amended description (no special order required) JL 30-05-2008 Chapter 2.9.1.3, added Note JL 03-06-2008 Chapter 2.11.4 removed part of description and example for DPM map-

ping (already exists in Program Reference Guide) JL

05-06-2008 Chapter 3.4.3, added parameter tRESi , added Note JL 19-06-2008 Chapter 3.4.7, replaced completely JL 20-06-2008 Chapter 3.4.2, added note JL 20-06-2008 Chapter 3.4.6, revised power and current specs JL 23-06-2008 Chapter 3.5, added JL 23-06-2008 Chapter 2.14.2, amended note JL 01-07-2008 Renumbered Chapter 4.2.3 to 4.3, revised storage conditions JL 02-07-2008 Chapter 3.3, revised completely JL 09-07-2008 Chapter 7, added note about NXHX50-RE schematics JL 1.1 10-07-2008 Released JL 10-07-2008 Rev. 1.2 started JL 14-07-2008 Chapter 4.2.1 parameter t2,t3, changed < to ≤ JL 14-07-2008 Chapter 4.4.1 added buffer type IOC9, changed assignment of

TDBIAPCUNLP36C from IO9 to IOC9 JL

15-07-2008 Chapter 4.4, revised signal definitions: MEMDR_CLK (was OD6, is now IOD6), MMIOs (were IOD6, are now IODS6). Corrected number of VDDC pins (was 35, is now 34) and VDDIO pins (was 23, is now 24)

JL

13-11-2008 Chapter 3.4.7, added param. Tcas. Chapter 3.3, revised parameter IDDC JL 14-11-2008 Chapter 2.26, added circuit for unused Ethernet interface JL 24-11-2008 Chapter 3.4.12, specified parameter tDVAL (was tbd) JL 25-11-2008 Chapter 3.3, revised power supply recommendation for core supply JL 1.2 25-11-2008 Released JL Note: The specified date of a change is for (internal) reference only. Date-based revision steps are generally not published, hence a published (released) revision always contains ALL changes applied after the date of the previous revision.

netX50 Technical Data Reference Guide Contacts • 170


9 Contacts

Headquarter Germany Hilscher Gesellschaft für Systemautomation mbH Rheinstrasse 15 65795 Hattersheim Phone: +49 (0) 6190 9907-0 Fax: +49 (0) 6190 9907-50 E-Mail: [email protected] Support Phone: +49 (0) 6190 9907-99 E-Mail: [email protected]

Subsidiaries

China Hilscher Ges.f.Systemaut. mbH Shanghai Representative Office 200010 Shanghai Phone: +86 (0) 21-6355-5161 E-Mail: [email protected] Support Phone: +86 (0) 21-6355-5161 E-Mail: [email protected] France Hilscher France S.a.r.l. 69500 Bron Phone: +33 (0) 4 72 37 98 40 E-Mail: [email protected] Support Phone: +33 (0) 4 72 37 98 40 E-Mail: [email protected] Italy Hilscher Italia srl 20090 Vimodrone (MI) Phone: +39 02 25007068 E-Mail: [email protected] Support Phone: +39 / 02 25007068 E-Mail: [email protected]

Japan Hilscher Japan KK Tokyo, 160-0022 Phone: +81 (0) 3-5362-0521 E-Mail: [email protected] Support Phone: +81 (0) 3-5362-0521 E-Mail: [email protected] Switzerland Hilscher Swiss GmbH 4500 Solothurn Phone: +41 (0) 32 623 6633 E-Mail: [email protected] Support Phone: +49 (0) 6190 9907-99 E-Mail: [email protected] USA Hilscher North America, Inc. Lisle, IL 60532 Phone: +1 630-505-5301 E-Mail: [email protected] Support Phone: +1 630-505-5301 E-Mail: [email protected]

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