White Paper
looptelecom.com 1 December 16, 2008
Network Element Synchronization
By Dr. John W. Pan
Introduction In a nationwide synchronous telecommunications
network, the system clock within each element is synchronized to a
national master element, shown as M below. A discussion of network
synchronization is available in another white paper from Loop
Telecom named Transport Synchronization in SDH.
In this paper, synchronization issues are discussed related to a
single network element, typically at network edge, as A to G above.
All Loop products adhere to these principles.
Basic Synchronization Scheme For every network element designed
by Loop Telecom, such as the Loop-AM3440, capabilities are
available for this element to synchronize with the network clock.
Two connections, one for the primary source and another for the
secondary source, are provided as reference to duplicated internal
oscillators. With dual clock feeds, connection to the network clock
is assured under single fault conditions. Even when both
connections to the network clock fail, the network element can
still operate with its internal oscillators in holdover mode,
meaning the internal oscillators will continue to operate at the
last adjusted rate.
NetworkElement
SystemClock
InternalOscillator
PrimaryClock Source
SecondaryClock Source
SystemClock
InternalOscillator
Secondary
Primary
Because an internal oscillator can operate without reference on
occasion, they must meet American National Standards Institute
standard entitled Synchronization Interface Standards for Digital
Networks (ANSI/T1.101-1987). Network elements such as the Loop
AM3440 are considered stratum 4 elements. To provide redundancy,
the internal oscillator and system clock are duplicated in separate
controller cards.
Network Element Synchronization
White Paper
looptelecom.com 2 December 16, 2008
Internal Clock Characteristics To meet stratum 4 requirements,
for all Loop products including the AM3440, the specification for
the internal oscillator is an accuracy of 32 ppm over an operating
temperature range of 0 to 50C. Within this temperature range, the
temperature coefficient is under 2 ppm per degree Celsius. In
actual tests of Loop products, the average measured frequency for
internal oscillators is within 5 ppm at 20C, with a standard
deviation of 7 ppm. The maximum temperature coefficient measured
has an average of +0.5 ppm per degree Celsius over the 0 to 50C
range with a standard deviation of 0.2 ppm/C. Beyond the rated
temperature, Loop products including the Loop AM3440, has been
tested from -10 to 60 C and still found to operate within frequency
specs. Note that under normal sync conditions, the internal
oscillators will run at the network clock rate of stratum 1
accuracy.
Evaluation of the Quality of Clock Sources Another important
issue is the evaluation of the clock sources to ensure their
quality. Two parameters are of interest. First is signal strength
clearly if the clock source signal is weak or missing, that source
will be considered unreliable or failed. Second is accuracy.
Without a local reference more accurate than the incoming clocks,
evaluation of the incoming clock accuracy is not possible. Thus the
logic to select which clock source to use under fault conditions is
based on most likely scenario. That is: if the incoming signal
strength meets spec, its accuracy is assumed unless contradicted by
other results. The rated accuracy of the primary and secondary
clock sources is the stratum 1 spec of 0.00001 ppm. Even if an
intermediate stratum 3 relay node lost its connection to the
master, and reverted to its internal clock, the incoming accuracy
would still be within 1 ppm, far better than the stratum 4 accuracy
of 32 ppm.
Clock Selection Logic For reliability the controller card, which
includes the internal oscillator, is duplicated. The logic for
clock source selection and internal oscillator selection is as
follows. Note that, after any given failure, the failed condition
could recover. The system will then revert to as normal operation
as possible.
1. If the primary controller card is operating, and internal
oscillator of primary controller is phase
locked to the primary reference clock, then the primary clock
source will be used by the internal oscillator.
2. If the primary controller card fails, the secondary
controller card takes over operation. 3. If the primary clock
source signal becomes weak or missing, the secondary clock source
will be
used by the internal oscillators. 4. If the internal oscillator
fails to sync with the primary clock source, the secondary clock
source will
be used. 5. If the secondary clock source signal also becomes
weak or missing, both internal oscillators will be
allowed to run in the hold mode.
Conclusion With poorer tolerance of internal oscillators
compared to incoming reference clocks, determination of frequency
accuracy is not possible. The protection logic assumes if the
signal is present, it must be accurate. The clock switching logic
is based only on this best case scenario.
References John Pan "Synchronization and Multiplexing in a
Digital Communications Network" Proceedings of the IEEE, Vol 60,
May 1972
