Net-Ordering for Optimal Circuit Timing in Nanometer Interconnect Design M. Sc. work by Moiseev Konstantin Supervisors: Dr. Shmuel Wimer, Dr. Avinoam Kolodny

Net-Ordering for Net-Ordering for Optimal Circuit Timing Optimal Circuit Timing

in Nanometer in Nanometer Interconnect DesignInterconnect Design

M. Sc. work by Moiseev KonstantinM. Sc. work by Moiseev Konstantin

Supervisors: Dr. Shmuel Wimer, Dr. Avinoam Supervisors: Dr. Shmuel Wimer, Dr. Avinoam KolodnyKolodny

Problem formulationProblem formulation Minimize bus timing by ordering of wires and Minimize bus timing by ordering of wires and

allocation of wire widths and inter-wire spacesallocation of wire widths and inter-wire spaces Total width of interconnect structure is given Total width of interconnect structure is given

constant Aconstant A All wires have equal length LAll wires have equal length L

A

L

Wi-1 Wi Wi+1

Si Si+1

Ri-1 Ri Ri+1

Ci-1 Ci Ci+1

Vc

c

Vc

c

MotivationMotivation

Cross-capacitances between wires in Cross-capacitances between wires in interconnect structures have a major interconnect structures have a major effect on circuit timingeffect on circuit timing

Wires 10 years ago – area capacitance was dominant

Wires today – cross capacitance is dominant

MotivationMotivation Relative order of wire drivers in a bus influences circuit timingRelative order of wire drivers in a bus influences circuit timing

Case A Case B

Weak driver

Strong driver

Capacitive load

Circuit timing is better in case B !

Delay modelDelay model Elmore approximation for delay together with Elmore approximation for delay together with

- model equivalent circuit for wire - model equivalent circuit for wire

1 1

i i ii i i i i i

i i i i i i i i

eC hR hRb d da kRW gR RC

W W S W S W S S

QQ: Is Elmore delay model good enough for state-of-the-art technology?: Is Elmore delay model good enough for state-of-the-art technology?

AA: : Fitted Elmore DelayFitted Elmore Delay model gives up to 2% error in delay estimation model gives up to 2% error in delay estimation

Miller factor Miller factor assumed 1 for all assumed 1 for all wireswires

More general case More general case will be discussed will be discussed laterlater

Objective functionsObjective functions

Total sum of delays:Total sum of delays:

1

10 1 1

ni i i

i i i i ii i i i i i i i i

eC hR hRb d df a kRW gR RC

W W S W S W S S

Worst wire delay:Worst wire delay:

20 1 1 1max i i i

i i i i ii n i i i i i i i i

eC hR hRb d df a kRW gR RC

W W S W S W S S

Worst wire slack:Worst wire slack:

30 1 1 1max i i i

i i i i i ii n i i i i i i i i

eC hR hRb d df a kRW gR RC T

W W S W S W S S

AgendaAgenda

Solution for total sum of delays Solution for total sum of delays objective functionobjective function

Solution for worst delay objective Solution for worst delay objective functionfunction

Optimization of total sum of delays Optimization of total sum of delays with cross talkwith cross talk

Delay uncertainty issueDelay uncertainty issue

Solution for total sum of Solution for total sum of delays casedelays case

constant wire width constant wire width Differentiating function with respect to Differentiating function with respect to

and area constraint and equating derivatives to and area constraint and equating derivatives to zero, obtain:zero, obtain:

Now assume all wires have predefined constant Now assume all wires have predefined constant width and get:width and get:

W

1f iS

1

0 0

1

1 2, 0 1

1,

1

i i i

n n

dS hR hR i n

W

dS hR

W

dS hR

W

2 2 2 2 2 2 2 2

0 2 4 1 1 3 5n nS S S S S S S S

This property is preserved in all kinds of optimizations discussed

Solution for total sum of Solution for total sum of delays casedelays case

constant wire width constant wire width Substitute obtained relations for spaces to Substitute obtained relations for spaces to

objective function, simplify and obtain:objective function, simplify and obtain:

1 1 1

10 0 0

22

1 0 10

1 2

n n n

i i i ii i i

n

i i ni

b ef n a kW g R C C R

W W

d d dhR hR hR hR

A nW W W W

Order-independent part

Order-dependent part

Order of wires is influenced by values of driver resistances only ! Order of wires is influenced by values of driver resistances only ! Question: Does optimal order exist ???Question: Does optimal order exist ???

BMI orderBMI order Take wires sorted in descending order of Take wires sorted in descending order of

drivers and put alternately to the left and drivers and put alternately to the left and right sides of the bus channelright sides of the bus channel

Obtained permutation of wires called Obtained permutation of wires called Balanced Monotonic InterleavedBalanced Monotonic Interleaved (BMI)(BMI) orderorder

7 6 5 4 3 2 1

BMI order

BMI order provides best sharing of inter-wire spaces

Optimal order theoremOptimal order theorem

Define , Define , where - non-decreasing monotonic function where - non-decreasing monotonic function and - some permutation of -valuesand - some permutation of -values

Theorem (optimal order):Theorem (optimal order): given a bus whose given a bus whose wires are of uniform width , the BMI wires are of uniform width , the BMI order of signals in the bus yields minimum order of signals in the bus yields minimum total sum of delays.total sum of delays. Proof : Proof :

Order-dependent part of is special case of -Order-dependent part of is special case of -sumsum

Prove by induction that -sums are minimized by Prove by induction that -sums are minimized by BMI permutationBMI permutation

2

1 0 10

( , ) ( ) ( ) ( ) ( )n

n n i i ni

f f R f R f R f R

f

nR

W

1f

Impedance matchingImpedance matching

Balance the resistance of the driver Balance the resistance of the driver and resistance of the driven lineand resistance of the driven line

Mathematically: Mathematically:

BMI still holdsBMI still holds Simple but practical case:Simple but practical case:

Rdriver

Rwire=L

W

Cwire= LW1

( )ii

WR

( )i ii

aW R

b cR

Solution for general caseSolution for general case In general case, wire widths are optimization variablesIn general case, wire widths are optimization variables Derivatives with respect to :Derivatives with respect to :

Theorem (existence): Theorem (existence): For given set of wires For given set of wires , if for each pair of wires and with , if for each pair of wires and with drivers and loads and drivers and loads and respectively holds and , then respectively holds and , then optimal order of this set of wires is BMI, under optimal order of this set of wires is BMI, under total sum of wire delays objective function.total sum of wire delays objective function.

One special case: if all load capacitances are equal, One special case: if all load capacitances are equal, then optimal order is always BMI then optimal order is always BMI

iW

1i

i ii

i

d db eC

S SW

kR

n 0 1 1, , , n

i j ( , )i iR C

( , )j jR C i jR R i jC C

Minimizing total sum of Minimizing total sum of delays - summarydelays - summary

1.1. Generate all Generate all permutations of wirespermutations of wires

2.2. For each permutation For each permutation solve sizing problemsolve sizing problem

3.3. Find permutation Find permutation giving minimum delaygiving minimum delay

Complexity: Complexity: exponentialexponential

Number of Number of optimization variables: optimization variables:

1.1. Generate all Generate all permutations of wirespermutations of wires

2.2. For each permutation For each permutation solve sizing problemsolve sizing problem

3.3. Find permutation Find permutation giving minimum delaygiving minimum delay

Complexity: Complexity: exponentialexponential

Number of Number of optimization variables: optimization variables:

1.1. Perform impedance Perform impedance matching by function matching by function with parameters (if with parameters (if needed)needed)

2.2. Arrange wires in BMI Arrange wires in BMI orderorder

3.3. Solve sizing problem Solve sizing problem Complexity: linearComplexity: linear Number of optimization Number of optimization

variables: orvariables: or

1.1. Perform impedance Perform impedance matching by function matching by function with parameters (if with parameters (if needed)needed)

2.2. Arrange wires in BMI Arrange wires in BMI orderorder

3.3. Solve sizing problem Solve sizing problem Complexity: linearComplexity: linear Number of optimization Number of optimization

variables: orvariables: or2 1n

p

1n p

Our heuristicOur heuristic::Straight forward Straight forward solutionsolution: :

2 1n

Results: total sum Results: total sum minimizationminimization

problem demonstration on problem demonstration on random problem instancesrandom problem instances

20 sets of 5 wires20 sets of 5 wires RRdrdr: [0.1 : [0.1 ÷ ÷ 2] K2] KΩΩ

(random)(random) CCll: [10 : [10 ÷ ÷ 200] fF200] fF

(random)(random) Bus length: 600 Bus length: 600

μμmm Bus width: 12 Bus width: 12 μμmm Technology: 90 Technology: 90

nmnm


bus width influence bus width influence Set of 6 wiresSet of 6 wires RRdrdr: [0.1 ÷ 2] : [0.1 ÷ 2]

KKΩΩ

(random)(random) CCll: 10 fF: 10 fF Bus length: Bus length:

600 600 μμmm Technology: Technology:

90 nm90 nm

Bus width, [μm]

Best delay obtained

Worst delay obtained

Diff ,.%

14233.0539251.97827.51

16222.0889237.98696.68

18213.6536227.75536.19

20206.9164219.61765.78

25194.9293205.0774.95

30187.0116195.46014.32


interleaved businterleaved busNo. of weak

drivers

Best delay obtained,

[ps]

Worst delay

obtained, [ps]

Diff ,.%

1169.0378169.70110.39

2204.7659214.61854.81

3245.1067265.00638.12

4289.3409321.700711.19

5337.3242362.70437.52

6391.6022405.49363.55

Set of 7 wiresSet of 7 wires RRdrdr: 0.1K: 0.1KΩΩ and and

1.9 K1.9 KΩΩ CCll: 50 fF and 5 fF: 50 fF and 5 fF Bus length: 600 Bus length: 600


nmnm


comparison of heuristics on comparison of heuristics on random problem instancesrandom problem instancesExhaustive

search best delay

Exhaustive search worst delay

0.63%

0.76%

0.63%

0.07%

0.21%

0.20%

16.54%

12.60%

16.39%

11.28%

14.10%

9.60%

Average: 0.42% 14.10%iW const

ii

aW

b cR

1st heuristic

2nd heuristic

100%

AgendaAgenda





Solution for minmax caseSolution for minmax case

The goal: minimizing maximum wire delay (or The goal: minimizing maximum wire delay (or slack)slack)

Function is not differentiableFunction is not differentiable All wires have the same delay (S. Michaely et All wires have the same delay (S. Michaely et

al.)al.)

Assumptions:Assumptions: wire width is convex monotonic decreasing wire width is convex monotonic decreasing

in driver resistance (impedance matching)in driver resistance (impedance matching) Drivers and loads satisfy existence theoremDrivers and loads satisfy existence theorem

1 1

i i ii i i i i i

i i i i i i i i

eC hR hRb d da kRW gR RC const

W W S W S W S S

Solution for minmax caseSolution for minmax case

SuppositionSupposition: : In minimization of In minimization of maximum wire delay, optimal order maximum wire delay, optimal order of wires is BMIof wires is BMI Under assumptions of previous slide Under assumptions of previous slide

delay expression can be written as:delay expression can be written as:

Edge effects Edge effects (S. Michaely et. al)(S. Michaely et. al) can break can break down optimality of BMIdown optimality of BMI

1

1 1( ) ( )i i

i i

R R constS S

Results: minmax Results: minmax optimizationoptimization

bus width influencebus width influence 20 sets of 5 wires20 sets of 5 wires RRdrdr: [0.1 ÷ 2] K: [0.1 ÷ 2] KΩΩ



μμmm Technology: 90 nmTechnology: 90 nm

Bus width, umObtained

optimization impact, percent

215.94

513.92

109.12

156.49

205.11


bus length influence bus length influence 20 sets of 5 wires20 sets of 5 wires RRdrdr: [0.1 ÷ 2] K: [0.1 ÷ 2] KΩΩ

(random)(random) CCll: [10 ÷ 200] fF: [10 ÷ 200] fF

(random)(random) Bus width: 12 Bus width: 12 μμmm Technology: 90 nmTechnology: 90 nm

Bus length, μmObtained

optimization impact, percent

3003003.383.38

5005006.56.5

1000100010.5810.58

5000500011.3911.39

100001000010.9610.96


interleaved businterleaved busNo. of weak

drivers

Best delay obtained,

[ps]

Worst delay

obtained, [ps]

Diff ,.%

143.861243.861243.937443.93740.17

247.974852.68618.94

352.704861.151213.81

456.681569.270518.17

561.003169.315311.99

665.099869.36926.16

Set of 7 wiresSet of 7 wires RRdrdr: 0.1K: 0.1KΩΩ and and

1.9 K1.9 KΩΩ CCll: 50 fF and 5 fF: 50 fF and 5 fF Bus length: 600 Bus length: 600


nmnm

AgendaAgenda





Crosstalk issueCrosstalk issue

So far: we assumed Miller factor 1So far: we assumed Miller factor 1 In practice: can be 0, 1 or 2In practice: can be 0, 1 or 2 Introducing Miller factor changes wire delay Introducing Miller factor changes wire delay

equation:equation:

The solution will be different according to The solution will be different according to three cases:three cases: Miller factor is equal for all pairs of wiresMiller factor is equal for all pairs of wires Miller factor different only near wallsMiller factor different only near walls Each pair of wires has its own different Miller factorEach pair of wires has its own different Miller factor

1, , 1 1, , 1

1 1

i i i i i i i i i iii i i i i i

i i i i i i i i

d MCF d MCF h MCF R h MCF ReCba kRW gR RC

W W S W S W S S

11stst case: uniform Miller case: uniform Miller factorfactor

The order-dependent part of objective function is The order-dependent part of objective function is given as:given as:

When all Miller coefficients are equal, above When all Miller coefficients are equal, above expression changes to:expression changes to:

Conclusion:Conclusion: Uniform Miller factor doesn’t affect functional form Uniform Miller factor doesn’t affect functional form

of delay function and therefore optimal order will of delay function and therefore optimal order will be BMIbe BMI

Impact of wire ordering emphasized even moreImpact of wire ordering emphasized even more

*

22

1, 1 0 1,0* 10 ,00

1 2n

i i i i n ni

d d dMCF hR hR MCF hR MCF hR

A nW W W W

22

1 0 10

1 2n

i i ni

d d dMCF hR hR hR hR

A nW W W W

22ndnd case: almost uniform case: almost uniform Miller factorMiller factor

All Miller coefficients in internal inter-wire spaces are equal toAll Miller coefficients in internal inter-wire spaces are equal to Miller coefficients near the walls areMiller coefficients near the walls are Order-dependent part of objective function can be written as:Order-dependent part of objective function can be written as:

sMCF

intMCF

22

int1 0 1

0 int int

2ns s

i i ni

MCF MCF MCFd d dhR hR hR hR

A nW W MCF W MCF W

BMI order remains optimal ifBMI order remains optimal if

In other cases order is In other cases order is monotonic but not always monotonic but not always BMIBMI

Minmax optimization gives Minmax optimization gives the same resultsthe same results

int

1sMCF

MCF

33rdrd case: non-uniform Miller case: non-uniform Miller factorfactor

Miller coefficients can be presented by the matrixMiller coefficients can be presented by the matrix

Minimization problem then is equivalent to :Minimization problem then is equivalent to :

Where Where and and

Proved to be NP-complete (A. Vittal et al.)Proved to be NP-complete (A. Vittal et al.)

*

*

* * * *

0,0 0, 1 0,0

1, 11,0 1,0

0 ,0 0 , 1 0 ,0

n

n nn n

n

MCF MCF MCF

MCFMCF MCFMCF

MCF MCF MCF

,min sqr sqrall

permutations

D R MCF

0 1 1

2, , , ,sqr i i n

d d dR hR hR hR hR

W W W

* 1, 1,0*0 ,0, , , ,sqr i i nMCF MCF MCF MCF

AgendaAgenda





Delay uncertainty issueDelay uncertainty issue Due to difference in arrival Due to difference in arrival

times of signals transmitted times of signals transmitted by neighbor wires, crosstalk by neighbor wires, crosstalk noise is creatednoise is created

Crosstalk noise is Crosstalk noise is characterized by two main characterized by two main parameters: parameters: peak noise peak noise andand delay uncertaintydelay uncertainty

Peak noise

Delay uncertainty

Maximum delay uncertainty for a signal in a bus Maximum delay uncertainty for a signal in a bus can be expressed as follows:can be expressed as follows:

1max,

1 1

1 1

2log 1

ii i i

i idd i i i

dhR

W S St

V

(A. Vittal et al., T. Sato et al.)

Minimization of delay Minimization of delay uncertaintyuncertainty

Define new objective functions:Define new objective functions: Total sum of delay uncertainties:Total sum of delay uncertainties:

Worst delay uncertaintyWorst delay uncertainty::

Experiments show that BMI order Experiments show that BMI order leads to minimizing both and leads to minimizing both and

4 max,ii

f t

5 max,max ii

f t

4f 5f

Results: minimization of Results: minimization of delay uncertaintydelay uncertainty

20 sets of 5 wires20 sets of 5 wires RRdrdr: [0.1 : [0.1 ÷ ÷ 2] K2] KΩΩ



μμmm Bus width: 15 Bus width: 15 μμmm Technology: 90 nmTechnology: 90 nm

Total sum

Minmax

Average improvement:Average improvement: Total sum of delay Total sum of delay

uncertainties: about uncertainties: about 27 %27 % Worst delay uncertainty: Worst delay uncertainty:

about about 43%43%

Monotony in ordering Monotony in ordering optimizationsoptimizations

Monotony is most important property of Monotony is most important property of solutions of ordering optimization problemssolutions of ordering optimization problems Total sum of delays: optimal order is monotonic, BMITotal sum of delays: optimal order is monotonic, BMI Maximum delay: optimal order is monotonic, BMIMaximum delay: optimal order is monotonic, BMI Optimization with crosstalk: optimal order is Optimization with crosstalk: optimal order is

monotonicmonotonic Delay uncertainty optimization: optimal order is Delay uncertainty optimization: optimal order is

monotonic, BMImonotonic, BMI Generally, all above problems can be solved on Generally, all above problems can be solved on

cyclic bus and obtained optimal order will be cyclic bus and obtained optimal order will be monotonicmonotonic

BMI and other monotonic orders are special BMI and other monotonic orders are special cases and defined by edge conditions onlycases and defined by edge conditions only

ConclusionsConclusions

Problem of optimal simultaneous wire Problem of optimal simultaneous wire sizing and ordering was presented and sizing and ordering was presented and solvedsolved

Effects of crosstalk on nominal delays Effects of crosstalk on nominal delays and delay uncertainty are examinedand delay uncertainty are examined

Monotonic ordering according to driver Monotonic ordering according to driver strength is shown to be advantageous strength is shown to be advantageous for the various objective functions for the various objective functions

Examples for 90-nanometer technology Examples for 90-nanometer technology are analyzed and discussed are analyzed and discussed

Documents

Net-Ordering for Optimal Circuit Timing in Nanometer Interconnect Design M. Sc. work by Moiseev Konstantin Supervisors: Dr. Shmuel Wimer, Dr. Avinoam Kolodny