© Semiconductor Components Industries, LLC, 2017

November, 2018 − Rev. 151 Publication Order Number:

NCV898031/D

NCV898031

2 MHz Non-SynchronousSEPIC/Boost Controller

The NCV898031 is an adjustable output non−synchronous 2 MHzSEPIC/boost controller which drives an external N−channelMOSFET. The device uses peak current mode control with internalslope compensation. The IC incorporates an internal regulator thatsupplies charge to the gate driver.

Protection features include internally−set soft−start, undervoltagelockout, cycle−by−cycle current limiting and thermal shutdown.

Additional features include low quiescent current sleep mode andmicroprocessor compatible enable pin.

Features• Peak Current Mode Control with Internal Slope Compensation

• 1.2 V �2% Reference Voltage

• 2 MHz Fixed Frequency Operation

• Wide Input Voltage Range of 3.2 V to 40 V, 45 V Load Dump

• Input Undervoltage Lockout (UVLO)

• Internal Soft−Start

• Low Quiescent Current in Sleep Mode (< 10 �A Typical)

• Cycle−by−Cycle Current Limit Protection

• Hiccup−Mode Overcurrent Protection (OCP)

• Hiccup−Mode Short−Circuit Protection (SCP)

• Thermal Shutdown (TSD)

• NCV Prefix for Automotive and Other Applications RequiringUnique Site and Control Change Requirements; AEC−Q100Qualified and PPAP Capable

• This is a Pb−Free Device

Typical Applications• Small Form Factor Point−of−Load Power Regulation

• Headlamps

• Backlighting

MARKINGDIAGRAM

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SOIC−8D SUFFIXCASE 7511

8

PIN CONNECTIONS

1 8

2

3

4

7

6

5

(Top View)

EN

ISNS

GND

GDRV

VFB

VC

VIN

VDRV

898031 = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package

898031ALYW

�

1

8

Device Package Shipping†

ORDERING INFORMATION

NCV898031D1R2G SOIC−8(Pb−Free)

2500 / Tape &Reel

†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationBrochure, BRD8011/D.

NCV898031

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Gm

CSA

L1

SC

CLK

ENABLE

EN

VC

PW

N

RC

CC

RSNS

RF1

Vref

CDRV

Vg

Vo

Cg

Co

Figure 1. Simplified Block Diagram and Application Schematic

8

3

2

4

6

GND

ISNS

GDRV

VIN

VFB

5VDRV

OSC

QD

TEMPVDRV

DRIVELOGIC

CL

SCP

SS

FAULTLOGIC1

7+

●

L2

●

CCPL

RF2

PACKAGE PIN DESCRIPTIONS

Pin No.Pin

Symbol Function

1 EN Enable input. The part is disabled into sleep mode when this pin is brought low for longer than the enabletime−out period.

2 ISNS Current sense input. Connect this pin to the source of the external N−MOSFET, through a current−senseresistor to ground to sense the switching current for regulation and current limiting.

3 GND Ground reference.

4 GDRV Gate driver output. Connect to gate of the external N−MOSFET. A series resistance can be added fromGDRV to the gate to tailor EMC performance. An RGND = 15 k� (typical) GDRV−GND resistor is stronglyrecommended.

5 VDRV Driving voltage. Internally−regulated supply for driving the external N−MOSFET, sourced from VIN. Bypasswith a 1.0 �F ceramic capacitor to ground.

6 VIN Input voltage. If bootstrapping operation is desired, connect a diode from the input supply to VIN, in addi-tion to a diode from the output voltage to VDRV and/or VIN.

7 VC Output of the voltage error amplifier. An external compensator network from VC to GND is used to stabilizethe converter.

8 VFB Output voltage feedback. A resistor from the output voltage to VFB with another resistor from VFB to GNDcreates a voltage divider for regulation and programming of the output voltage.

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ABSOLUTE MAXIMUM RATINGS (Voltages are with respect to GND, unless otherwise indicated)

Rating Value Unit

Dc Supply Voltage (VIN) −0.3 to 40 V

Peak Transient Voltage (Load Dump on VIN) 45 V

Dc Supply Voltage (VDRV, GDRV) 12 V

Peak Transient Voltage (VFB) −0.3 to 6 V

Dc Voltage (VC, VFB, ISNS) −0.3 to 3.6 V

Dc Voltage (EN) −0.3 to 6 V

Dc Voltage Stress (VIN − VDRV)* −0.7 to 40 V

Operating Junction Temperature −40 to 150 °C

Storage Temperature Range −65 to 150 °C

Peak Reflow Soldering Temperature: Pb−Free, 60 to 150 seconds at 217°C 265 peak °C

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.*An external diode from the input to the VIN pin is required if bootstrapping VDRV and VIN off of the output voltage.

PACKAGE CAPABILITIES

Characteristic Value Unit

ESD Capability (All Pins) Human Body ModelMachine Model

�2.0�200

KVV

Moisture Sensitivity Level 1

Package Thermal Resistance Junction−to−Ambient, R�JA (Note 1) 100 °C/W

1. Value based on copper are of 650 mm2 (or 1 in2) of 1 oz copper thickness and FR4 PCB substrate.

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ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values areguaranteed by test, design or statistical correlation.

Characteristic Symbol Conditions Min Typ Max Unit

GENERAL

Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, TJ = 25°C − 2.0 − �A

Quiescent Current, Sleep Mode Iq,sleep VIN = 13.2 V, EN = 0, −40°C < TJ < 125°C − 2.0 6.0 �A

Quiescent Current, No switching Iq,off Into VIN pin, EN = 1, No switching − 1.5 2.5 mA

Quiescent Current, Switching,normal operation

Iq,on Into VIN pin, EN = 1, Switching − 7.5 10 mA

OSCILLATOR

Minimum pulse width ton,min 30 65 90 ns

Maximum duty cycle Dmax 85 88 90 %

Switching frequency fs 1.8 2.0 2.2 MHz

Soft−start time tss From start of switching with VFB = 0 untilreference voltage = VREF

520 650 780 �s

Soft−start delay tss,dly From EN → 1 until start of switching withVFB = 0 with VC pin compensation networkdisconnected

80 100 280 �s

Slope compensating ramp Sa 52 68 80 mV/�s

ENABLE

EN pull−down current IEN VEN = 5 V − 5.0 10 �A

EN input high voltage Vs,ih VIN > VUVLO 2.0 − 5.0 V

EN input low voltage Vs,il 0 − 800 mV

EN time−out ratio %ten From EN falling edge, to oscillator control(EN high) or shutdown (EN low), Percent oftypical switching frequency

− 250 350 %

CURRENT SENSE AMPLIFIER

Low−frequency gain Acsa Input−to−output gain at dc, ISNS � 1 V 0.9 1.0 1.1 V/V

Bandwidth BWcsa Gain of Acsa − 3 dB 2.5 − − MHz

ISNS input bias current Isns,bias Out of ISNS pin − 30 50 �A

Current limit threshold voltage Vcl Voltage on ISNS pin 360 400 440 mV

Current limit,Response time

tcl CL tripped until GDRV falling edge,VISNS = Vcl(typ) + 60 mV

− 80 125 ns

Overcurrent protection,Threshold voltage

%Vocp Percent of Vcl 125 150 175 %

Overcurrent protection,Response Time

tocp From overcurrent event, Until switchingstops, VISNS = VOCP + 40 mV

− 80 125 ns

VOLTAGE ERROR OPERATIONAL TRANSCONDUCTANCE AMPLIFIER

Transconductance gm,vea VFB – Vref = ± 20 mV 0.8 1.2 1.63 mS

VEA output resistance Ro,vea 2.0 − − M�

VFB input bias current Ivfb,bias Current out of VFB pin − 0.5 2.0 �A

Reference voltage Vref 1.176 1.200 1.224 V

VEA maximum output voltage Vc,max 2.5 − − V

VEA minimum output voltage Vc,min − − 0.3 V

VEA sourcing current Isrc,vea VEA output current, Vc = 2.0 V 80 100 − �A

VEA sinking current Isnk,vea VEA output current, Vc = 0.7 V 80 100 − �A

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ELECTRICAL CHARACTERISTICS (−40°C < TJ < 150°C, 3.2 V < VIN < 40 V, unless otherwise specified) Min/Max values areguaranteed by test, design or statistical correlation.

Characteristic UnitMaxTypMinConditionsSymbol

GATE DRIVER

Sourcing current Isrc VDRV ≥ 6 V, VDRV − VGDRV = 2 V 600 800 − mA

Sinking current Isink VGDRV ≥ 2 V 500 600 − mA

Driving voltage dropout Vdrv,do VIN − VDRV, IvDRV = 25 mA − 0.3 0.6 V

Driving voltage source current Idrv VIN − VDRV = 1 V 35 45 − mA

Backdrive diode voltage drop Vd,bd VDRV − VIN, Id,bd = 5 mA − − 0.7 V

Driving voltage VDRV IVDRV = 0.1 − 25 mA 6.0 6.3 6.6 V

UVLO

Undervoltage lock−out,Threshold voltage

Vuvlo VIN falling 2.95 3.05 3.15 V

Undervoltage lock−out,Hysteresis

Vuvlo,hys VIN rising 50 150 250 mV

SHORT CIRCUIT PROTECTION

Startup blanking period %tscp,dly From start of soft−start, Percent of tss 100 120 150 %

Hiccup−mode period %thcp,dly From shutdown to start of soft−start, Percent of tss

70 85 100 %

Short circuit threshold voltage %Vscp VFB as percent of Vref 60 67 75 %

Short circuit delay tscp From VFB < Vscp to stop switching − 35 100 ns

THERMAL SHUTDOWN

Thermal shutdown threshold Tsd TJ rising 160 170 180 °C

Thermal shutdown hysteresis Tsd,hys TJ falling 10 15 20 °C

Thermal shutdown delay tsd,dly From TJ > Tsd to stop switching − − 100 ns

Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different conditions.

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TYPICAL PERFORMANCE CHARACTERISTICS

0 10 20 30 40

VIN, INPUT VOLTAGE (V)

Figure 2. Sleep Current vs. Input Voltage

I q,s

leep

, SLE

EP

CU

RR

EN

T (�A

)

TJ = 25°C

Figure 3. Sleep Current vs. Temperature

−50 50 100 150 200TJ, JUNCTION TEMPERATURE (°C)

Figure 4. Quiescent Current vs. Temperature

t on,

min

MIN

IMU

M O

N T

IME

(ns

)

TJ, JUNCTION TEMPERATURE (°C)

Figure 5. Minimum On Time vs. Temperature

−50 0 50 100 200

TJ, JUNCTION TEMPERATURE (°C)

Figure 6. Normalized Current Limit vs.Temperature

−40 10 60 110 160

NO

RM

ALI

ZE

D C

UR

RE

NT

LIM

IT (

25°C

)I q

,on,

QU

IES

CE

NT

CU

RR

EN

T (

mA

)

Figure 7. Reference Voltage vs. Temperature

−50 0 50 100 200

I q,s

leep

, SLE

EP

CU

RR

EN

T (�A

) VIN = 13.2 V

0

1

2

3

4

5

6

150TJ, JUNCTION TEMPERATURE (°C)

0

1

2

3

4

5

7

6

7.1

7.2

7.4

7.5

7.6

7.7

0.990

0.995

1.000

1.005

1.010

61.5

62.0

62.5

63.0

64.5

64.0

0

1.195

1.197

1.199

1.201

1.203

1.205

TJ, JUNCTION TEMPERATURE (°C)

Vre

f, R

EF

ER

EN

CE

VO

LTA

GE

(V

)

−40 10 60 110 160

VIN = 13.2 V

7.3

7.8

150

63.5

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TYPICAL PERFORMANCE CHARACTERISTICS

Figure 8. Enable Pulldown Current vs. VoltageTJ, JUNCTION TEMPERATURE (°C)

Figure 9. Enable Pulldown Current vs.Temperature

I ena

ble,

PU

LLD

OW

N C

UR

RE

NT

(�A

)

0 1 2 3 4

Venable, VOLTAGE (V)

I ena

ble,

PU

LLD

OW

N C

UR

RE

NT

(�A

) TJ = 25°C

5 6 −40 10 60 110 1600

1

2

3

4

5

7

6

5.0

5.5

6.0

6.5

7.0

7.5

8.0

NCV898031

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APPLICATION INFORMATION

Current Mode ControlThe NCV898031 incorporates a current mode control

scheme, in which the PWM ramp signal is derived from thepower switch current. This ramp signal is compared to theoutput of the error amplifier to control the on−time of thepower switch. The oscillator is used as a fixed−frequencyclock to ensure a constant operational frequency. Theresulting control scheme features several advantages overconventional voltage mode control. First, derived directlyfrom the inductor, the ramp signal responds immediately toline voltage changes. This eliminates the delay caused by theoutput filter and the error amplifier, which is commonlyfound in voltage mode controllers. The second benefitcomes from inherent pulse−by−pulse current limiting bymerely clamping the peak switching current. Finally, sincecurrent mode commands an output current rather thanvoltage, the filter offers only a single pole to the feedbackloop. This allows for a simpler compensation.

The NCV898031 also includes a slope compensationscheme in which a fixed ramp generated by the oscillator isadded to the current ramp. A proper slope rate is provided toimprove circuit stability without sacrificing the advantagesof current mode control.

Current LimitThe NCV898031 features two current limit protections,

peak current mode and over current latch off. When thecurrent sense amplifier detects a voltage above the peakcurrent limit between ISNS and GND after the current limitleading edge blanking time, the peak current limit causes thepower switch to turn off for the remainder of the cycle. Setthe current limit with a resistor from ISNS to GND, with R =

VCL / Ilimit.If the voltage across the current sense resistor exceeds the

over current threshold voltage, the device enters overcurrent hiccup mode. The device will remain off for thehiccup time and then go through the soft−start procedure.

Short Circuit ProtectionIf the short circuit enable bit is set (SCE = Y), the device

will attempt to protect the power MOSFET from damage.When the output voltage falls below the short circuit tripvoltage, after the initial short circuit blanking time, the

device enters short circuit latch−off. The device will remainoff for the hiccup time and then go through the soft−start.

EnableThe Enable pin has two modes. When a DC logic high

(CMOS/TTL compatible) voltage is applied to this pin, theNCV898031 operates at the programmed frequency. Whena DC logic low voltage is applied, the NCV898031 enters alow quiescent current sleep mode. The NCV898031requires 2 clock cycles after the falling edge of the Enablesignal to stop switching.

If the VIN pin voltage falls below VUVLO when EN pin isat logic−high, the IC may not power up when VIN returnsback above the UVLO. To resume a normal operating state,the EN pin must be cycled with a single logic−low tologic−high transition.

UVLOInput Undervoltage Lockout (UVLO) is provided to

ensure that unexpected behavior does not occur when VINis too low to support the internal rails and power thecontroller. The IC will start up when enabled and VINsurpasses the UVLO threshold plus the UVLO hysteresisand will shut down when VIN drops below the UVLOthreshold or the part is disabled.

To avoid any lock state under UVLO conditions, the ENpin should be in logic−low state. For further details, pleaserefer to Enable paragraph.

Internal Soft-StartTo insure moderate inrush current and reduce output

overshoot, the NCV898031 features a soft start whichcharges a capacitor with a fixed current to ramp up thereference voltage.

VDRVAn internal regulator provides the drive voltage for the

gate driver. Bypass with a ceramic capacitor to ground toensure fast turn on times. The capacitor should be between0.1 �F and 1 �F, depending on switching speed and chargerequirements of the external MOSFET.

GDRVAn RGND = 15 k� (typical) GDRV−GND resistor is

strongly recommended.

NCV898031

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SEPIC TOPOLOGY APPLICATION INFORMATION

Oscillator

+

QS

R

NCV898031

Voltage Error

VEA

CSA

PWM Comparator GateDrive

Compensation

GDRV

L2

L1

Figure 10. SEPIC Current Mode Schematic

VFB

ISNS

VIN

RLCo

CCPL

SEPIC Design MethodologyThis section details an overview of the component

selection process for the NCV898031 in continuousconduction mode SEPIC. It is intended to assist with thedesign process but does not remove all engineering designwork. Many of the equations make heavy use of the smallripple approximation. This process entails the followingsteps:

1. Define Operational Parameters2. Select Current Sense Resistor3. Select SEPIC Inductors4. Select Coupling Capacitor5. Select Output Capacitors6. Select Input Capacitors7. Select Feedback Resistors8. Select Compensator Components9. Select MOSFET(s)

10. Select Diode

1. Define Operational ParametersBefore beginning the design, define the operating

parameters of the application. These include:VIN(min): minimum input voltage [V]VIN(max): maximum input voltage [V]VOUT: output voltage [V]IOUT(max): maximum output current [A]ICL: desired typical cycle−by−cycle current limit [A]

From this the ideal minimum and maximum duty cyclescan be calculated as follows:

Dmin �VOUT

VIN(max) � VOUT

Dmax �VOUT

VIN(min) � VOUT

Both duty cycles will actually be higher due to power lossin the conversion. The exact duty cycles will depend onconduction and switching losses.

If the calculated DWC (worst case) is higher than the Dmaxlimit of the NCV898031, the conversion will not bepossible. It is important for a SEPIC converter to have arestricted Dmax, because while the ideal conversion ratio ofa SEPIC converter goes up to infinity as D approaches 1, areal converter’s conversion ratio starts to decrease as lossesovertake the increased power transfer. If the converter is inthis range it will not be able to regulate properly.

If the following equation is not satisfied, the device willskip pulses at high VIN:

Dminfs

� ton(min)

Where: fs: switching frequency [Hz]ton(min): minimum on time [s]

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2. Select Current Sense ResistorCurrent sensing for peak current mode control and current

limit relies on the MOSFET current signal, which ismeasured with a ground referenced amplifier. Note that theICL equals the sum of the currents from both inductors. Theeasiest method of generating this signal is to use a currentsense resistor from the source of the MOSFET to deviceground. The sense resistor should be selected as follows:

RS �VCLICL

Where: RS: sense resistor [�]VCL: current limit threshold voltage [V]ICL: desire current limit [A]

3. Select SEPIC InductorsThe output inductor controls the current ripple that occurs

over a switching period. A high current ripple will result inexcessive power loss and ripple current requirements. A lowcurrent ripple will result in a poor control signal and a slowcurrent slew rate in case of load steps. A good starting pointfor peak to peak ripple is around 20−40% of the inductorcurrent at the maximum load at the worst case VIN, butoperation should be verified empirically. The worst case VINis the minimum input voltage. After choosing a peak currentripple value, calculate the inductor value as follows:

L �VIN(WC) DWC

�IL,max fs

Where: VIN(WC): VIN value as close as possible to half ofVOUT [V]

DWC: duty cycle at VIN(WC)�IL,max: maximum peak to peak ripple [A]

The maximum average inductor current can be calculated asfollows:

IL,AVG �VOUT IOUT(max)

VIN(min)�

The Peak Inductor current can be calculated as follows:

IL1,peak � IL1,avg ��IL1

2

IL2,peak � IOUT(max) ��IL2

2

Where (if L1 = L2): �IL1 = �IL2

4. Select Coupling CapacitorCoupling capacitor RMS current is significant. A low

ESR ceramic capacitor is required as a coupling capacitor.Selecting a capacitor value too low will result in highcapacitor ripple voltage which will distort ripple current anddiminish input line regulation capability. Budgeting 2−5%coupling capacitor ripple voltage is a reasonable guideline.

�Vcoupling �Iout DWC

Ccoupling fs

Current mode control helps resolve some of the resonantfrequencies that create issues in voltage mode SEPICconverter designs, but some resonance issues may occur. Aresonant frequency exists at

fresonance � 12� (L1 � L2)Ccoupling�

It may become necessary to place an RC damping networkin parallel with the coupling capacitor if the resonance iswithin ~1 decade of the closed−loop crossover frequency.The capacitance of the damping capacitor should be ~5times that of the coupling capacitor. The optimal dampingresistance (including the ESR of the damping capacitor) iscalculated as

Rdamping � L1 � L2Ccoupling

�5. Select Output Capacitors

The output capacitors smooth the output voltage andreduce the overshoot and undershoot associated with linetransients. The steady state output ripple associated with theoutput capacitors can be calculated as follows:

VOUT(ripple) �

IOUT(max)DWC

COUT fs��IOUT(max)

1 DWC�

DWCVIN(min)

2 fsL2Resr

The capacitors need to survive an RMS ripple current asfollows:

ICout(RMS) � IOUT(max)2 DWC ��I2

a �I2r3 IaIrD�WC�

whereIa � IL1_peak � IL2_peak Iout

Ir � �IL1 � �IL2

The use of parallel ceramic bypass capacitors is stronglyencouraged to help with the transient response.

6. Select Input CapacitorsThe input capacitor reduces voltage ripple on the input to

the module associated with the ac component of the inputcurrent.

ICin(RMS) ��IL1

12�

7. Select Feedback ResistorsThe feedback resistors form a resistor divider from the

output of the converter to ground, with a tap to the feedbackpin. During regulation, the divided voltage will equal Vref.The lower feedback resistor can be chosen, and the upperfeedback resistor value is calculated as follows:

Rupper � Rlower

�Vout Vref

Vref

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The total feedback resistance (Rupper + Rlower) should bein the range of 1 k� – 100 k�.

8. Select Compensator ComponentsCurrent Mode control method employed by the

NCV898031 allows the use of a simple, Type IIcompensation to optimize the dynamic response accordingto system requirements.

9. Select MOSFET(s)In order to ensure the gate drive voltage does not drop out

the MOSFET(s) chosen must not violate the followinginequality:

Qg(total) �Idrvfs

Where: Qg(total): Total Gate Charge of MOSFET(s) [C]Idrv: Drive voltage current [A]fs: Switching Frequency [Hz]

The maximum RMS Current can be calculated as follows:

ID(max) � DWC�IQ(peak)2 �

��IL1 � �IL22

3 IQ(peak)

��IL1 � �IL2�

where

IQ(peak) � IL1_peak � IL2_peak

The maximum voltage across the MOSFET will be themaximum output voltage, which is the higher of themaximum input voltage and the regulated output voltaged:

VQ(max) � VOUT(max) � VIN(max)

10. Select DiodeThe output diode rectifies the output current. The average

current through diode will be equal to the output current:

ID(avg) � IOUT(max)

Additionally, the diode must block voltage equal to thehigher of the output voltage and the maximum input voltage:

VD(max) � VOUT(max) � VIN(max)

The maximum power dissipation in the diode can becalculated as follows:

PD � Vf (max) IOUT(max)

Where: Pd: Power dissipation in the diode [W]Vf(max): Maximum forward voltage of the diode [V]

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BOOST TOPOLOGY APPLICATION INFORMATION

Oscillator

SlopeCompensation

+

NCV898031

Voltage Error

VEA

CSA

PWM Comparator GateDrive

Compensation

LGDRV

Figure 11. Boost Current Mode Schematic

S

R

Q

CO RL

VOUT

VFB

ISNS

VIN

Boost Converter Design MethodologyThis section details an overview of the component

selection process for the NCV898031 in continuousconduction mode boost. It is intended to assist with thedesign process but does not remove all engineering designwork. Many of the equations make heavy use of the smallripple approximation. This process entails the followingsteps:

1. Define Operational Parameters2. Select Current Sense Resistor3. Select Output Inductor4. Select Output Capacitors5. Select Input Capacitors6. Select Feedback Resistors7. Select Compensator Components8. Select MOSFET(s)9. Select Diode

10. Determine Feedback Loop Compensation Network

1. Define Operational ParametersBefore beginning the design, define the operating

parameters of the application. These include:VIN(min): minimum input voltage [V]VIN(max): maximum input voltage [V]VOUT: output voltage [V]IOUT(max): maximum output current [A]ICL: desired typical cycle−by−cycle current limit [A]

From this the ideal minimum and maximum duty cycles canbe calculated as follows:

Dmin � 1 VIN(max)

VOUT

DWC � 1 VIN(WC)

VOUT

Both duty cycles will actually be higher due to power lossin the conversion. The exact duty cycles will depend onconduction and switching losses. If the maximum inputvoltage is higher than the output voltage, the minimum dutycycle will be negative. This is because a boost convertercannot have an output lower than the input. In situationswhere the input is higher than the output, the output willfollow the input, minus the diode drop of the output diodeand the converter will not attempt to switch.

If the calculated DWC is higher than the Dmax limit of theNCV898031, the conversion will not be possible. It isimportant for a boost converter to have a restricted Dmax,because while the ideal conversion ratio of a boost convertergoes up to infinity as D approaches 1, a real converter’sconversion ratio starts to decrease as losses overtake theincreased power transfer. If the converter is in this range itwill not be able to regulate properly.

If the following equation is not satisfied, the device willskip pulses at high VIN:

Dminfs

� ton(min)

Where: fs: switching frequency [Hz]ton(min): minimum on time [s]

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2. Select Current Sense ResistorCurrent sensing for peak current mode control and current

limit relies on the MOSFET current signal, which ismeasured with a ground referenced amplifier. The easiestmethod of generating this signal is to use a current senseresistor from the source of the MOSFET to device ground.The sense resistor should be selected as follows:

RS �VCLICL

Where: RS: sense resistor [�]VCL: current limit threshold voltage [V]ICL: desire current limit [A]

3. Select Output InductorThe output inductor controls the current ripple that occurs

over a switching period. A high current ripple will result inexcessive power loss and ripple current requirements. A lowcurrent ripple will result in a poor control signal and a slowcurrent slew rate in case of load steps. A good starting pointfor peak to peak ripple is around 20−40% of the inductorcurrent at the maximum load at the worst case VIN, butoperation should be verified empirically. The worst case VINis half of VOUT, or whatever VIN is closest to half of VIN.After choosing a peak current ripple value, calculate theinductor value as follows:

L �VIN(WC)

2 DWC

�IL,max fsVOUT

Where: VIN(WC): VIN value as close as possible to half ofVOUT [V]

DWC: duty cycle at VIN(WC)�IL,max: maximum peak to peak ripple [A]

The maximum average inductor current can be calculated asfollows:

IL,avg �VOUTIOUT(max)

VIN(min)

The Peak Inductor current can be calculated as follows:

IL,peak � IL,avg �VIN(min)

2 DWC

LfsVOUT

Where: IL,peak: Peak inductor current value [A]

4. Select Output CapacitorsThe output capacitors smooth the output voltage and

reduce the overshoot and undershoot associated with linetransients. The steady state output ripple associated with theoutput capacitors can be calculated as follows:

VOUT(ripple) �

DIOUT(max)

fCOUT��IOUT(max)

1 D�

VIN(min)D

2fLRESR

The capacitors need to survive an RMS ripple current asfollows:

ICout(RMS) � IOUTDWC

D�WC�

DWC

12 � D�WCL

ROUT�TSW

2�The use of parallel ceramic bypass capacitors is strongly

encouraged to help with the transient response.

5. Select Input CapacitorsThe input capacitor reduces voltage ripple on the input to

the module associated with the ac component of the inputcurrent.

ICin(RMS) �VIN(WC)

2 DWC

LfsVOUT2 3�

6. Select Feedback ResistorsThe feedback resistors form a resistor divider from the

output of the converter to ground, with a tap to the feedbackpin. During regulation, the divided voltage will equal Vref.The lower feedback resistor can be chosen, and the upperfeedback resistor value is calculated as follows:

Rupper � Rlower

�Vout Vref

Vref

The total feedback resistance (Rupper + Rlower) should bein the range of 1 k� – 100 k�.

7. Select Compensator ComponentsCurrent Mode control method employed by the

NCV898031 allows the use of a simple, Type IIcompensation to optimize the dynamic response accordingto system requirements.

8. Select MOSFET(s)In order to ensure the gate drive voltage does not drop out

the MOSFET(s) chosen must not violate the followinginequality:

Qg(total) �Idrvfs

Where: Qg(total): Total Gate Charge of MOSFET(s) [C]Idrv: Drive voltage current [A]fs: Switching Frequency [Hz]

The maximum RMS Current can be calculated as follows:

IQ(max) � Iout

DWC�D�WC

The maximum voltage across the MOSFET will be themaximum output voltage, which is the higher of themaximum input voltage and the regulated output voltaged:

VQ(max) � VOUT(WC)

9. Select DiodeThe output diode rectifies the output current. The average

current through diode will be equal to the output current:

ID(avg) � IOUT(max)

NCV898031

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Additionally, the diode must block voltage equal to thehigher of the output voltage and the maximum input voltage:

VD(max) � VOUT(max)

The maximum power dissipation in the diode can becalculated as follows:

PD � Vf (max) IOUT(max)

Where: Pd: Power dissipation in the diode [W]Vf(max): Maximum forward voltage of the diode [V]

10. Determine Feedback Loop Compensation NetworkThe purpose of a compensation network is to stabilize the

dynamic response of the converter. By optimizing thecompensation network, stable regulation response isachieved for input line and load transients.

Compensator design involves the placement of poles andzeros in the closed loop transfer function. Losses from theboost inductor, MOSFET, current sensing and boost diodelosses also influence the gain and compensationexpressions. The OTA has an ESD protection structure(RESD ≈ 502 �, data not provided in the datasheet) locatedon the die between the OTA output and the IC package

compensation pin (VC). The information from the OTAPWM feedback control signal (VCTRL) may differ from theIC-VC signal if R2 is of similar order of magnitude as RESD.The compensation and gain expressions which follow takeinfluence from the OTA output impedance elements intoaccount.

Type-I compensation is not possible due to the presenceof RESD. The Figures 12 and 13 compensation networkscorrespond to a Type-II network in series with RESD.The resulting control-output transfer function is an accuratemathematical model of the IC in a boost converter topology.The model does have limitations and a more accurate SPICEmodel should be considered for a more detailed analysis:• The attenuating effect of large value ceramic capacitors

in parallel with output electrolytic capacitor ESR is notconsidered in the equations.

• The CCM Boost control-output transfer functionincludes operating efficiency as a correction factor toimprove modeling accuracy under low input voltageand high output current operating conditions whereoperating losses becomes significant.

Rds(on)

VdL

GND

ISNS

VFB

GDRVVC

Ri

COUT

VOUT

C1

R2

VCTRL

OTA

VINrL

rCf

C2

ROUT

RESD

R0

R1

Rlow

Figure 12. NCV898031 Boost Converter OTA and Compensation

NCV898031

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Rds(on)

Vd

GND

ISNS

VFB

GDRV

VC

Ri

COUT

VOUT

C1

R2

VCTRL

OTA

VIN

rCf

C2

ROUT

RESD

R0

R1

Rlow

Lp

1:N

VREF

Figure 13. NCV898031 Flyback Converter OTA and Compensation

The following equations may be used to select compensationcomponents R2, C1, C2 for Figures 12 & 13 power supply.Required input design parameters for analysis are:

Vd = Output diode Vf (V)

VIN = Power supply input voltage (V)

N = Ns/Np (Flyback transformer turns ratio)

Ri = Current sense resistor (�)

RDS(on) = MOSFET RDS(on) (�)(Rsw_eq = RDS(on) + Ri for the boost continuous conductionmode (CCM) expressions)

COUT = Bulk output capacitor value (F)

rCF = Bulk output capacitor ESR (�)

ROUT = Equivalent resistance of output load (�)

Pout = Output Power (W)

L = Boost inductor value or flyback transformer primaryside inductance (H)

rL = Boost inductor ESR (�)

Ts = 1/fs, where fs = 2 MHz clock frequency

R1 and Rlow = Feedback resistor divider values used to set theoutput voltage (�)

VOUT = Device specific output voltage (defined by R1 andRlow values) (V)

R0 = OTA output resistance = 3 M�

Sa = IC slope compensation (e.g. 68 mV/�s for NCV898031)

gm = OTA transconductance = 1.2 mS

D = Controller duty ratio

D’ = 1 − D

Necessary equations for describing the modulator gain(Vctrl-to-Vout gain) Hctrl_output(f) are described next. Boostcontinuous conduction mode (CCM) and discontinuousconduction mode (DCM) transfer function expressions aresummarized in Table 1. Flyback CCM and DCM transferfunction expressions are summarized in Table 2.

NCV898031

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Table 1. BOOST CCM AND DCM TRANSFER FUNCTION EXPRESSIONS

CCM DCM

Duty Ratio (D)

�

�

2ROUTVdVIN�Rsw_eq�ROUT� VIN

VOUT2�VOUT�

2

-VOUT ROUT�ROUTVIN�2�2Rsw_eqVINVOUT4VdRsw_eqVIN

-4Rsw_eqVOUT�24rLVdVIN4rLVOUT�

2 �Rsw_eq�2VOUT�2�

�

�2ROUT

�VOUT�2 � VdVIN

Where:

2�LM(M 1)�

�L �L

ROUTTs

VOUT/VIN DCConversion Ratio(M)

1

1 D�1

(1D)Vd

VOUT

�

�

�

1

1 � 1

(1D)2�rL�DRsw_eq

ROUT

�

�

1

2�1 � 1�

2D2

�L�

Inductor On-slope(Sn), V/s

VIN ILave�rL � Rsw_eq

LRi

Where average inductor current: ILave �Pout

VIN�

VIN

LRi

CompensationRamp (mc) 1 �

Sa

Sn1 �

Sa

Sn

Cout ESR Zero(�z1)

1

rCF�COUT

1

rCF�COUT

Right-Half-PlaneZero (�z2)

(1D)2

L�ROUT

rCF�ROUT

rCF � ROUT

rL

L

ROUT

M2L

Low FrequencyModulator Pole(�p1)

2ROUT

�Ts

LM3mc

COUT

1

RCF�COUT

�2M 1

M 1

High FrequencyModulator Pole(�p2)

− 2FSW�1 1M

D2

Sampling DoublePole (�n)

�

Ts−

Sampling QualityCoefficient (Qp)

1

�(mc(1 D) 0.5)−

Fm 1

2M �ROUTTs

LM2�12�

SaSn

1

Sn�mc�Ts

Hd ��ROUT

Ri

2VOUT

D�

M 1

2M 1

Control-OutputTransfer Function(Hctrl_output(f)) Fm�Hd

�1 � j2�fz1

�1 j2�fz2

�1 � j2�fp1�1 � j

2�fnQp

� �j 2�fn2

Fm�Hd

�1 � j2�fz1

�1 j2�fz2

�1 � j2�fp1�1 � j

2�fp2

NCV898031

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Table 2. FLYBACK CCM AND DCM TRANSFER FUNCTION EXPRESSIONS

CCM DCM

Duty ratio (D)

VOUT

VOUT � NVINWhere:

VOUT

NVIN

2�L�

�L �N2�Lp

Ts�ROUT

VOUT/VIN DC ConversionRatio (M)

N � D

1 D

N � D

2 � �L�

Inductor On-slope (Sn), V/s VIN

Lp

Ri

VIN

Lp

Ri

Compensation Ramp (mc)1 �

Sa

Sn1 �

Sa

Sn

Cout ESR Zero (�z1) 1

rCF�COUT

1

rCF�COUT

Right-Half-Plane Zero (�z2) (1D)2�ROUT

D�Lp�N2

ROUT

N2�Lp

�1

M�(M � 1)

Modulator Pole (�p1) D�3�L

� �1 � 2�SaSn � 1 � D

ROUT�COUT

2

ROUT�COUT

�p2

− 2FSW�� 1D

1� 1M

2

Fm 1

D�2�L

� �1 � 2�SaSn � 2M � 1

1

Sn�mc�Ts

Hd ROUT

Ri�NVIN�

1

2�L�

Control-output TransferFunction (Hctrl_output(f))

Fm�Hd

�1 � j2�fz1

�1 j2�fz2

�1 � j2�fp1

Fm�Hd

�1 � j2�fz1

�1 j2�fz2

�1 � j2�fp1�1 � j

2�fp2

Once the desired cross-over frequency (fc) gainadjustment and necessary phase boost are determined fromthe Hctrl_output(f) gain and phase plots, the Table 3 equationsmay be used. It should be noted that minor compensation

component value adjustments may become necessary whenR2 ≤ ~10·Resd as a result of approximations for determiningcomponents R2, C1, C2.

NCV898031

www.onsemi.com18

Table 3. OTA COMPENSATION TRANSFER FUNCTION AND COMPENSATION VALUES

Desired OTA Gain at Cross-over Frequency fc (G)

10

desired_Gfc_gain_db

20

Desired Phase Boost at Cross-over Frequency fc (boost) ��margin arg�Hctrl_output(fc) 180°

� 90° �

180°

Select OTA Compensation Zero to Coincide with Modulator Pole at fp1 (fz)

p1e

2�

Resulting OTA High Frequency Pole Placement (fp) fzfc � fc�2 tan(boost)

fc fz tan(boost)

Compensation Resistor R2

fpG

fp fz�VOUT

1.2�gm�

1��fcfp2�

1��fzfp�

Compensation Capacitor C1 1

2��fz�R2

Compensation Capacitor C2 1

2��fpG�

Rlow�gm

Rlow � R1

OTA DC Gain (G0_OTA) Rlow

Rlow � R1

� gm � R0

Low Frequency Zero (�z1e)

1

2�

�R2 � Resd

R2ResdC2 ��

1 1 4R2ResdC2

�R2�Resd2C1

� � ��

High Frequency Zero (�z2e)

1

2�

�R2 � Resd

R2ResdC2 ��

1 � 1 4R2ResdC2

�R2�Resd2C1

� � ��

Low Frequency Pole (�p1e)

1

2�

�R0 � R2 � Resd

R2�R0 � Resd

C2

��

1 1 4R2�R0�Resd

C2

�R0�R2�Resd2C1

� � ��

High Frequency Pole (�p2e)

1

2�

�R0 � R2 � Resd

R2�R0 � Resd

C2

��

1 � 1 4R2�R0�Resd

C2

�R0�R2�Resd2C1

� � ��

OTA Transfer Function (GOTA(f))

-G0_OTA

�1 � j2�fz1e

�1 � j2�fp1e�

�1 � j2�fz2e

�1 � j2�fp2e

The open-loop-response in closed-loop form to verify thegain/phase margins may be obtained from the followingexpression.

T(f) � GOTA(f) Hctrl_output(f)

Low Voltage OperationIf the input voltage drops below the UVLO or MOSFET

threshold voltage, another voltage may be used to power the

device. Simply connect the voltage you would like to boostto the inductor and connect the stable voltage to the VIN pinof the device. In boost configuration, the output of theconverter can be used to power the device. In some cases itmay be desirable to connect 2 sources to VIN pin, which canbe accomplished simply by connecting each of the sourcesthrough a diode to the VIN pin.

SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

SEATINGPLANE

14

58

N

J

X 45�

K

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

A

B S

DH

C

0.10 (0.004)

SCALE 1:1

STYLES ON PAGE 2

DIMA

MIN MAX MIN MAXINCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244

−X−

−Y−

G

MYM0.25 (0.010)

−Z−

YM0.25 (0.010) Z S X S

M� � � �

XXXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package

GENERICMARKING DIAGRAM*

1

8

XXXXXALYWX

1

8

IC Discrete

XXXXXXAYWW

�1

8

1.520.060

7.00.275

0.60.024

1.2700.050

4.00.155

� mminches

�SCALE 6:1

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

Discrete

XXXXXXAYWW

1

8

(Pb−Free)

XXXXXALYWX

�1

8

IC(Pb−Free)

XXXXXX = Specific Device CodeA = Assembly LocationY = YearWW = Work Week� = Pb−Free Package

*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

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SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

STYLE 4:PIN 1. ANODE

2. ANODE3. ANODE4. ANODE5. ANODE6. ANODE7. ANODE8. COMMON CATHODE

STYLE 1:PIN 1. EMITTER

2. COLLECTOR3. COLLECTOR4. EMITTER5. EMITTER6. BASE7. BASE8. EMITTER

STYLE 2:PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #13. COLLECTOR, #24. COLLECTOR, #25. BASE, #26. EMITTER, #27. BASE, #18. EMITTER, #1

STYLE 3:PIN 1. DRAIN, DIE #1

2. DRAIN, #13. DRAIN, #24. DRAIN, #25. GATE, #26. SOURCE, #27. GATE, #18. SOURCE, #1

STYLE 6:PIN 1. SOURCE

2. DRAIN3. DRAIN4. SOURCE5. SOURCE6. GATE7. GATE8. SOURCE

STYLE 5:PIN 1. DRAIN

2. DRAIN3. DRAIN4. DRAIN5. GATE6. GATE7. SOURCE8. SOURCE

STYLE 7:PIN 1. INPUT

2. EXTERNAL BYPASS3. THIRD STAGE SOURCE4. GROUND5. DRAIN6. GATE 37. SECOND STAGE Vd8. FIRST STAGE Vd

STYLE 8:PIN 1. COLLECTOR, DIE #1

2. BASE, #13. BASE, #24. COLLECTOR, #25. COLLECTOR, #26. EMITTER, #27. EMITTER, #18. COLLECTOR, #1

STYLE 9:PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #13. COLLECTOR, DIE #24. EMITTER, COMMON5. EMITTER, COMMON6. BASE, DIE #27. BASE, DIE #18. EMITTER, COMMON

STYLE 10:PIN 1. GROUND

2. BIAS 13. OUTPUT4. GROUND5. GROUND6. BIAS 27. INPUT8. GROUND

STYLE 11:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. DRAIN 27. DRAIN 18. DRAIN 1

STYLE 12:PIN 1. SOURCE

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 14:PIN 1. N−SOURCE

2. N−GATE3. P−SOURCE4. P−GATE5. P−DRAIN6. P−DRAIN7. N−DRAIN8. N−DRAIN

STYLE 13:PIN 1. N.C.

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 15:PIN 1. ANODE 1

2. ANODE 13. ANODE 14. ANODE 15. CATHODE, COMMON6. CATHODE, COMMON7. CATHODE, COMMON8. CATHODE, COMMON

STYLE 16:PIN 1. EMITTER, DIE #1

2. BASE, DIE #13. EMITTER, DIE #24. BASE, DIE #25. COLLECTOR, DIE #26. COLLECTOR, DIE #27. COLLECTOR, DIE #18. COLLECTOR, DIE #1

STYLE 17:PIN 1. VCC

2. V2OUT3. V1OUT4. TXE5. RXE6. VEE7. GND8. ACC

STYLE 18:PIN 1. ANODE

2. ANODE3. SOURCE4. GATE5. DRAIN6. DRAIN7. CATHODE8. CATHODE

STYLE 19:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. MIRROR 27. DRAIN 18. MIRROR 1

STYLE 20:PIN 1. SOURCE (N)

2. GATE (N)3. SOURCE (P)4. GATE (P)5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 21:PIN 1. CATHODE 1

2. CATHODE 23. CATHODE 34. CATHODE 45. CATHODE 56. COMMON ANODE7. COMMON ANODE8. CATHODE 6

STYLE 22:PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC3. COMMON CATHODE/VCC4. I/O LINE 35. COMMON ANODE/GND6. I/O LINE 47. I/O LINE 58. COMMON ANODE/GND

STYLE 23:PIN 1. LINE 1 IN

2. COMMON ANODE/GND3. COMMON ANODE/GND4. LINE 2 IN5. LINE 2 OUT6. COMMON ANODE/GND7. COMMON ANODE/GND8. LINE 1 OUT

STYLE 24:PIN 1. BASE

2. EMITTER3. COLLECTOR/ANODE4. COLLECTOR/ANODE5. CATHODE6. CATHODE7. COLLECTOR/ANODE8. COLLECTOR/ANODE

STYLE 25:PIN 1. VIN

2. N/C3. REXT4. GND5. IOUT6. IOUT7. IOUT8. IOUT

STYLE 26:PIN 1. GND

2. dv/dt3. ENABLE4. ILIMIT5. SOURCE6. SOURCE7. SOURCE8. VCC

STYLE 27:PIN 1. ILIMIT

2. OVLO3. UVLO4. INPUT+5. SOURCE6. SOURCE7. SOURCE8. DRAIN

STYLE 28:PIN 1. SW_TO_GND

2. DASIC_OFF3. DASIC_SW_DET4. GND5. V_MON6. VBULK7. VBULK8. VIN

STYLE 29:PIN 1. BASE, DIE #1

2. EMITTER, #13. BASE, #24. EMITTER, #25. COLLECTOR, #26. COLLECTOR, #27. COLLECTOR, #18. COLLECTOR, #1

STYLE 30:PIN 1. DRAIN 1

2. DRAIN 13. GATE 24. SOURCE 25. SOURCE 1/DRAIN 26. SOURCE 1/DRAIN 27. SOURCE 1/DRAIN 28. GATE 1

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