© Semiconductor Components Industries, LLC, 2016

March, 2016 − Rev. 41 Publication Order Number:

NCP1392/D

NCP1392B, NCP1392D

High-Voltage Half-BridgeDriver with InbuiltOscillator

The NCP1392B/D is a self−oscillating high voltage MOSFETdriver primarily tailored for the applications using half bridgetopology. Due to its proprietary high−voltage technology, the driveraccepts bulk voltages up to 600 V. Operating frequency of the drivercan be adjusted from 25 kHz to 480 kHz using a single resistor.Adjustable Brown−out protection assures correct bulk voltageoperating range. An internal 100 ms or 12.6 ms PFC delay timerguarantee that the main downstream converter will be turned on in thetime the bulk voltage is fully stabilized. The device provides fixeddead time which helps lowering the shoot−through current.

Features• Wide Operating Frequency Range − from 25 kHz to 480 kHz

• Minimum frequency adjust accuracy �3%

• Fixed Dead Time − 0.6 �s or 0.3 �s

• Adjustable Brown−out Protection for a Simple PFC Association

• 100 ms or 12.6 ms PFC Delay Timer

• Non−latched Enable Input

• Internal 16 V VCC Clamp

• Low Startup Current of 50 �A

• 1 A / 0.5 A Peak Current Sink / Source Drive Capability

• Operation up to 600 V Bulk Voltage

• Internal Temperature Shutdown

• SOIC−8 Package

• These are Pb−Free Devices

Typical Applications• Flat Panel Display Power Converters

• Low Cost Resonant SMPS

• High Power AC/DC Adapters for Notebooks

• Offline Battery Chargers

• Lamp Ballasts

Device Package Shipping†

ORDERING INFORMATION

NCP1392BDR2G SOIC−8(Pb−Free)

2500 /Tape & Reel

MARKINGDIAGRAMS

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1

8

SOIC−8CASE 751

1392xALYWW

�1

8

1392x = Specific Device Codex = B or D

A = Assembly LocationL = Wafer LotY = YearWW = Work Week� = Pb−Free Package

†For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationsBrochure, BRD8011/D.

PINOUT DIAGRAM

VCC

Rt

BO

GND

Vboot

Mupper

HB

Mlower

NCP1392DDR2G SOIC−8(Pb−Free)

2500 /Tape & Reel

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Figure 1. Typical Application Example

+

+

PFC FRONT STAGE

Rbo2

RfRfmax

Rfstart

Cbulk

Rbo1

Dboot

VCC

Rt

Bo

GND

Vboot

Mupper

HB

Mlower

Cboot

M2

NCP1392

DCOUTPUT

ACOUTPUT

CSS

M1

PIN FUNCTION DESCRIPTION

Pin # Pin Name Function Pin Description

1 VCC Supplies the Driver The driver accepts up to 16 V (given by internal zener clamp)

2 Rt Timing Resistor Connecting a resistor between this pin and GND, sets the operating frequency

3 BO Brown−Out/Enable Input Brown−Out function detects low input voltage conditions. Enable Input, whenbrought above Vref_EN, stops the driver. Operation is then restored (without anydelay) when BO pin voltage drops by EN_Hyste below Vref_EN.

4 GND IC Ground

5 Mlower Low−Side Driver Output Drives the lower side MOSFET

6 HB Half−Bridge Connection Connects to the half−bridge output

7 Mupper High−Side Driver Output Drives the higher side MOSFET

8 Vboot Bootstrap Pin The floating supply terminal for the upper stage

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−+

−+

−+

−+

20�sFilter

HIGH Level for 50ms After VCC On

VrefBO

−+ VrefEN

SW

I hys

ter

BO

VCC

Rt

VCCManagement

PONRESET

TSD

VCCClamp

VCCVDD

Vref

PFC Delay(100ms)

Vref

VDD

−+ Vref

IDT

Ct

S

D

R

CLK

Q

Q

PulseTrigger

LevelShifter

UVDetect

DELAY

S

R

Q

Q

Vboot

Mupper

Bridge

Mlower

GND

VCC

Figure 2. Internal Circuit Architecture (B Version)

0.5�sFilter

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−+

−+

−+

20�sFilter

HIGH Level for 6.3 ms After VCC On

VrefBO

SW

I hys

ter

BO

VCC

Rt

VCCManagement

PONRESET

TSD

VCCClamp

VCCVDD

Vref

PFC Delay(12.6 ms)

Vref

VDD

−+ Vref

IDT

Ct

S

D

R

CLK

Q

Q

PulseTrigger

LevelShifter

UVDetect

DELAY

S

R

Q

Q

Vboot

Mupper

Bridge

Mlower

GND

VCC

Figure 3. Internal Circuit Architecture (D Version)

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MAXIMUM RATINGS TABLE

Symbol Rating Value Unit

Vbridge High Voltage Bridge Pin − Pin 6 −1 to +600 V

Vboot −Vbridge

Floating Supply Voltage 0 to 20 V

VDRV_HI High−Side Output Voltage Vbridge − 0.3 toVboot + 0.3

V

VDRV_LO Low−Side Output Voltage −0.3 to VCC +0.3 V

dVbridge/dt Allowable Output Slew Rate �50 V/ns

ICC Maximum Current that Can Flow into VCC Pin (Pin 1), (Note 1) 20 mA

V_Rt Rt Pin Voltage −0.3 to 5 V

Maximum Voltage, All Pins (Except Pins 4 and 5) −0.3 to 10 V

R�JA Thermal Resistance Junction−to−Air, IC Soldered on 50 mm2 Cooper 35 �m 178 °C/W

R�JA Thermal Resistance Junction−to−Air, IC Soldered on 200 mm2 Cooper 35 �m 147 °C/W

Storage Temperature Range −60 to +150 °C

ESD Capability, Human Body Model (All Pins Except HV Pins 6, 7 and 8) 2.0 kV

ESD Capability, Human Body Model (HV Pins 6, 7 and 8) 1.5 kV

ESD Capability, Machine Model 200 V

Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionalityshould not be assumed, damage may occur and reliability may be affected.1. This device contains internal zener clamp connected between VCC and GND terminals. Current flowing into the VCC pin has to be limited

by an external resistor when device is supplied from supply which voltage is higher than VCCclamp (16 V typically). The ICC parameter isspecified for VBO = 0 V.

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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V, unless otherwise noted)

Characteristic Pin Symbol Min Typ Max Unit

SUPPLY SECTION

Turn−On Threshold Level, VCC Going Up 1 VCCON 10 11 12 V

Minimum Operating Voltage after Turn−On 1 VCCmin 8 9 10 V

Startup Voltage on the Floating Section 1 VbootON 7.8 8.8 9.8 V

Cutoff Voltage on the Floating Section, 1 Vbootmin 7 8 9 V

VCC Level at which the Internal Logic gets Reset 1 VCCreset − 6.5 − V

Startup Current, VCC < VCCON, 0°C � Tamb � +125°C 1 ICC − − 50 �A

Startup Current, VCC < VCCON, −40°C � Tamb < 0°C 1 ICC − − 65 �A

Internal IC Consumption, No Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz 1 ICC1 − 2.2 − mA

Internal IC Consumption, 1 nF Output Load on Pins 8/7 − 5/4, Fsw = 100 kHz 1 ICC2 − 3.4 − mA

Consumption in Fault Mode (Drivers Disabled, VCC > VCC(min), RT = 3.5 k�) 1 ICC3 − 2.56 − mA

Consumption During PFC Delay Period, 0°C � Tamb � +125°C ICC4 − − 400 �A

Consumption During PFC Delay Period, −40°C � Tamb < 0°C ICC4 − − 470 �A

Internal IC Consumption, No Output Load on Pin 8/7 FSW = 100 kHz 8 Iboot1 − 0.3 − mA

Internal IC Consumption, 1 nF Load on Pin 8/7 FSW = 100 kHz 8 Iboot2 − 1.44 − mA

Consumption in Fault Mode (Drivers Disabled, Vboot > Vbootmin) 8 Iboot3 − 0.1 − mA

VCC Zener Clamp Voltage @ 20 mA 1 VCCclamp 15.4 16 17.5 V

INTERNAL OSCILLATOR

Minimum Switching Frequency (Rt = 35 k� on Pin 2 for DT = 600 ns, Rt = 70 k� on Pin 2 for DT = 300 ns)

2 FSW min 24.25 25 25.75 kHz

Maximum Switching Frequency (B Version), Rt = 3.5 k� on Pin 2, DT = 600 ns 2 FSW maxB 208 245 282 kHz

Maximum Switching Frequency (D Version), Rt = 3.5 k� on Pin 2, DT = 300 ns 2 FSW maxD 408 480 552 kHz

Reference Voltage for all Current Generations 2 Vref RT 3.33 3.5 3.67 V

Internal Resistance Discharging Csoft−start 2 Rtdischarge − 500 − �

Operating Duty Cycle Symmetry 5, 7 DC 48 50 52 %

NOTE: Maximum capacitance directly connected to Pin 2 must be under 100 pF.

DRIVE OUTPUT

Output Voltage Rise Time @ CL = 1 nF, 10−90% of Output Signal 5, 7 Tr − 40 − ns

Output Voltage Fall Time @ CL = 1 nF, 10−90% of Output Signal 5, 7 Tf − 20 − ns

Source Resistance 5, 7 ROH − 12 − �

Sink Resistance 5, 7 ROL − 5 − �

Deadtime (B Version) 5,7 TdeadB 540 610 720 ns

Deadtime (D Version) 5,7 TdeadD 260 305 360 ns

Leakage Current on High Voltage Pins to GND (600 Vdc) 6,7,8 IHVLeak − − 5 �A

PROTECTION

Brown−Out Input Bias Current 3 IBObias − 0.01 − �A

Brown−Out Level 3 VBO 0.95 1 1.05 V

Hysteresis Current, Vpin3 < VBO 3 IBO 15.6 18.2 20.7 �A

Reference Voltage for EN Input (B Version) 3 Vref EN 1.9 2 2.1 V

EN Comparator (not available in D Version) − Vref EN_D − − − V

Enable Comparator Hysteresis 3 EN_Hyste − 100 − mV

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ELECTRICAL CHARACTERISTICS (For typical values TJ = 25°C, for min/max values TJ = −40°C to +125°C, Max TJ = 150°C, VCC = 12 V, unless otherwise noted)

Characteristic UnitMaxTypMinSymbolPin

PROTECTION

Propagation Delay Before Drivers are Stopped 3 EN_Delay − 0.5 − �s

Delay Before Any Driver Restart (B Version) − PFC Delay − 100 − ms

Delay Before Any Driver Restart (D Version) − PFC Delay − 12.6 − ms

Temperature Shutdown − TSD 140 − − °C

Hysteresis − TSDhyste − 30 − °C

Brown Out discharge time (B Version) (Note 2) − BOdisch − 50 − ms

Brown Out discharge time (D Version) (Note 2) − BOdisch − 6.3 − ms

2. Guaranteed by design.

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TYPICAL CHARACTERISTICS

11.01

11.00

10.99

10.98

10.97

10.96

10.95

10.94

10.93

10.92

10.91−40 −20 0 20 40 60 80 100 120

VO

LTA

GE

(V)

TEMPERATURE (°C)

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

VO

LTA

GE

(V)

8.98

8.97

8.96

8.95

8.94

8.93

8.92

8.91

8.90

Figure 4. VCCon Figure 5. VCCmin

VO

LTA

GE

(V)

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 6. VBOOTon

8.85

8.80

8.75

8.70

8.65

8.60

8.55

TEMPERATURE (°C)

Figure 7. VBOOTmin

−40 −20 0 20 40 60 80 100 120

VO

LTA

GE

(V)

8.10

8.05

8.00

7.95

7.90

7.85

7.80

7.75

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 8. ROH

20

18

16

14

12

10

8

6

4

2

0

TEMPERATURE (°C)

Figure 9. ROL

−40 −20 0 20 40 60 80 100 120

8

7

6

5

4

3

2

1

0

RE

SIS

TAN

CE

(�

)

RE

SIS

TAN

CE

(�

)

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TYPICAL CHARACTERISTICS

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 10. FSWmax (B Version)

FRE

QU

EN

CY

(kH

z)

243.4

TEMPERATURE (°C)

Figure 11. FSWmax (D Version)

−40 −20 0 20 40 60 80 100 120

FRE

QU

EN

CY

(kH

z)

25.05

25.00

24.95

24.90

24.85

24.80

24.75

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 12. FSWmin (B Version)

45.0

40.0

35.0

30.0

25.0

20.0

15.0

10.0

5.0

0.0

450

TEMPERATURE (°C)

Figure 13. FSWmin (D Version)

−40 −20 0 20 40 60 80 100 120

400

350

300

250

200

150

100

50

0

Figure 14. ICC_startup Figure 15. ICC4

CU

RR

EN

T (�A

)

CU

RR

EN

T (�A

)

243.2

243.0

242.8

242.6

242.4

242.2

242.0

241.8−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

FRE

QU

EN

CY

(kH

z)

490

485

480

475

470

465

460

455

450

TEMPERATURE (°C)

−40 −20 0 20 40 60 80 100 120

FRE

QU

EN

CY

(kH

z)

24.92

24.90

24.88

24.86

24.84

24.82

24.80

25.00

24.98

24.96

24.94

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TYPICAL CHARACTERISTICS

Figure 16. Tdead (B Version)

TEMPERATURE (°C)

Figure 17. Tdead (D Version)

−40 −20 0 20 40 60 80 100 120

2.008

VO

LTA

GE

(V)

2.006

2.004

2.002

2.000

1.998

1.996

1.994

1.992

1.990−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 18. PFCdelay (B Version)

VO

LTA

GE

(V)

1.015

1.014

1.013

1.012

1.011

1.010

1.009

1.008

1.007

Figure 19. PFCdelay (D Version)

Figure 20. Vref_EN Figure 21. VBO

TIM

E (n

s)

645

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

640

635

630

625

620

615

610−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

TIM

E (n

s)

330

325

320

315

310

305

300

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

TIM

E (m

s)14.0

13.5

13.0

12.5

12.0

11.5

11.0−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

109

TIM

E (m

s)

108

107

106

105

104

103

102

101

100

90

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TYPICAL CHARACTERISTICS

Irt (mA)

Figure 22. Rt_discharge

0.2

FRE

QU

EN

CY

(kH

z)

290

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

240

190

140

90

40

Figure 23. ENhyste

Figure 24. IBO Figure 25. VCC_clamp

Figure 26. Irt and Appropriate Frequency(B Version)

TEMPERATURE (°C)

−40 −20 0 20 40 60 80 100 120

VO

LTA

GE

(V)

17.0

16.8

16.6

16.4

16.2

16.0

15.8−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

19.4

19.2

19.0

18.8

18.6

18.4

18.2

18.0

17.8

17.6

17.4

CU

RR

EN

T (�A

)

VO

LTA

GE

(mV

)

110

108

106

104

102

100

98

96

94

92

90−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

Figure 27. Irt and Appropriate Frequency(D Version)

−40 −20 0 20 40 60 80 100 120

TEMPERATURE (°C)

580

560

540

520

500

480

460

440

420

400

RE

SIS

TAN

CE

(�

)

Irt (mA)

0.2

FRE

QU

EN

CY

(kH

z)

600

0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2

400

300

200

100

0

500

0.0 0.1

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APPLICATION INFORMATION

The NCP1392 is primarily intended to drive low cost halfbridge applications and especially resonant half bridgeapplications. The IC includes several features that help thedesigner to cope with resonant SPMS design. All featuresare described thereafter:• Wide Operating Frequency Range: The internal

current controlled oscillator is capable to operate overwide frequency range. Minimum frequency accuracy is�3%.

• Fixed Dead−Time: The internal dead−time helping tofight with cross conduction between the upper andlower power transistors. Three versions with differentdead time values are available to cover wide range ofapplications.

• PFC Timer: Fixed delay is placed to IC operationwhenever the driver restarts (VCCON or BO_OK detectevents). This delay assures that the bulk voltage will bestabilized in the time the driver provides pulses on theoutputs. Another benefit of this delay is that the softstart capacitor will be full discharged before any restart.

• Brown−Out Detection: The BO input monitors bulkvoltage level via resistor divider and thus assures thatthe application is working only for wanted bulk voltageband. The BO input sinks current of 18.2 �A until theVrefBO threshold is reached. Designer can thus adjustthe bulk voltage hysteresis according to the applicationneeds.

• Non−Latched Enable Input: The enable comparatorinput is connected in parallel to the BO terminal toallow the designer stop the output drivers when needed.There is no PFC delay when enable input is released soskip mode for resonant SMPS applications anddimming for light ballast applications are possible.

• Internal VCC Clamp: The internal zener clamp offersa way to prepare passive voltage regulator to maintainVCC voltage at 16 V in case the controller is suppliedfrom unregulated power supply or from bulk capacitor.

• Low Startup Current: This device features maximumstartup current of 50 �A which allows the designer touse high value startup resistor for applications whendriver is supplied from the auxiliary winding. Powerdissipation of startup resistor is thus significantlyreduced.

Current Controlled OscillatorThe current controlled oscillator features a high−speed

circuitry allowing operation from 50 kHz up to 960 kHz.However, as a division by two internally creates the two Qand Q outputs, the final effective signal on output Mlowerand Mupper switches in half frequency range. The VCO isconfigured in such a way that if the current that flows outfrom the Rt pin increases, the switching frequency also goesup. Figure 28 shows the architecture of this oscillator.

Figure 28. The Internal Current Controlled Oscillator Architecture

−+

−+

Delay

Vref Rt

From PFC Delay

Ct

Rt

Rt

Vref

S

D

CLK

R

IDT

Q

Q

From ENCmp.

PONReset

VDD

A

B

DeadTime

Csoft−start

+−

+−

Rsoft−start

The internal timing capacitor Ct is charged by currentwhich is proportional to the current flowing out from theRt pin. The discharging current IDT is applied when voltageon this capacitor reaches 2.5 V. The output drivers aredisabled during discharge period so the dead time length is

given by the discharge current sink capability. Dischargesink is disabled when voltage on the timing capacitorreaches zero and charging cycle starts again. The chargingcurrent and thus also whole oscillator is disabled during thePFC delay period to keep the IC consumption below 400 �A.

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This is valuable for applications that are supplied fromauxiliary winding and VCC capacitor is supposed to provideenergy during PFC delay period.

For the resonant applications and light ballast applicationsit is necessary to adjust minimum operating frequency with

high accuracy. The designer also needs to limit maximumoperating and startup frequency. All these parameters can beadjusted using few external components connected to the Rtpin as depicted in Figure 29.

Figure 29. Typical Rt Pin Connection

Rfmax

Rt

VCC

Rt

Rfstart Rbias

Rfmax−OCP

Rcomp Ccomp

CSS

D1

TLV431 (to primarycurrent sensor)

(to secondaryvoltage regulator)

NCP1392

Voltage Feedback Current Feedback

The minimum switching frequency is given by the Rtresistor value. This frequency is reached if there is nooptocoupler or current feedback action and soft start periodhas been already finished. The maximum switchingfrequency excursion is limited by the Rfmax selection. Notethat the Fmax value is influenced by the optocouplersaturation voltage value. Resistor Rfstart together withcapacitor CSS prepares the soft start period after PFC timerelapses. The Rt pin is grounded via an internal switch duringthe PFC delay period to assure that the soft start capacitorwill be fully discharged via Rfstart resistor.

There is a possibility to connect other control loops (likecurrent control loop) to the Rt pin. The only one limitationlies in the Rt pin reference voltage which is VrefRt = 3.5 V.Used regulator has to be capable to work with voltage lowerthan VrefRt.

The TLV431 shunt regulator is used in the example fromfigure 4 to prepare current feedback loop. Diode D1 is usedto enable regulator biasing via resistor Rbias. Totalsaturation voltage of this solution is 1.25 + 0.6 = 1.85 V forroom temperature. Shottky diode will further decreasesaturation voltage. Rfmax − OCP resistor value, limits themaximum frequency that can be pushed by this regulationloop. This parameter is not temperature stable because of theD1 temperature drift.

Brown−Out ProtectionThe Brown−Out circuitry (BO) offers a way to protect the

application from low DC input voltages. Below a givenlevel, the controller blocks the output pulses, above it, itauthorizes them. The internal circuitry, depicted byFigure 30, offers a way to observe the high−voltage (HV)rail.

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Figure 30. The internal Brown−Out Configuration with an Offset Current Sink

−+

Rupper

BO

Rlower

VrefBO

IBO

SW

20�sFilter

Vbulk

High Level for BOdisch time after VCC ON

BO_OK to and gates

To PFC Delay

+−

A resistive divider made of Rupper and Rlower, brings aportion of the HV rail on Pin 3. Below the turn−on level,the 18.2 �A current sink (IBO) is on. Therefore, the turn−onlevel is higher than the level given by the division ratiobrought by the resistive divider. To the contrary, when the

internal BO_OK signal is high (PFC timer runs or Mlowerand Mupper pulse), the IBO sink is deactivated. As a result,it becomes possible to select the turn−on and turn−off levelsvia a few lines of algebra:

IBO is on

VrefBO � Vbulk1 �Rlower

Rlower � Rupper� IBO � � Rlower � Rupper

Rlower � Rupper (eq. 1)

IBO is off

VrefBO � Vbulk2 �Rlower

Rlower � Rupper

(eq. 2)

We can extract Rlower from Equation 2 and plug it into Equation 1, then solve for Rupper:

Rlower � VrefBO �Vbulk1 � Vbulk2

IBO � �Vbulk2 � VrefBO

(eq. 3)

Rupper � Rlower �Vbulk2 � VrefBO

VrefBO

(eq. 4)

If we decide to turn−on our converter for Vbulk1 equals 350 V and turn it off for Vbulk2 equals 250 V, then for IBO = 18.2 �Aand VrefBO = 1.0 V we obtain:Rupper = 5.494 M�

Rlower = 22.066 k�The bridge power dissipation is 4002 / 5.517 M� = 29 mW when front−end PFC stage delivers 400 V. Figure 31 simulation

result confirms our calculations.

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Figure 31. Simulation Results for 350/250 ON/OFF Brown−Out Levels

The IBO current sink is turned ON for BOdisch time afterany controller restart to let the BO input voltage stabilize(there can be connected big capacitor to the BO input and theIBO is only 18.2 �A so it will take some time to discharge).Once the BOdisch time one shoot pulse ends the BO

comparator is supposed to either hold the IBO sink turnedON (if the bulk voltage level is not sufficient) or let it turnedOFF (if the bulk voltage is higher than Vbulk1).

See Figures 10 − 13 for better understanding on how theBO input works.

Figure 32. BO Input Functionality − Vbulk2 < Vbulk < Vbulk1

Vbulk

VBO

BO_OK

Vcc

DRV_EN

Vbulk_ON

Vbulk_OFF

1 V

IBO is turned ON after Vcc_ON by internal logic (for BOdisch time)

< BOdisch

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Figure 33. BO Input Functionality −Vbulk2 < Vbulk < Vbulk1, PFC Start Follows

Vbulk

VBO

BO_OK

Vcc

DRV_EN

Vbulk_ON

Vbulk_OFF

1 V

PFCdelay

Figure 34. BO Input Functionality − Vbulk > Vbulk1

Vbulk

VBO

BO_OK

Vcc

DRV_EN

Vbulk_ON

Vbulk_OFF

1 V

Checking VBO by activating IBO sink, released after BOdisch time

BOdisch

The drivers are activated with delay specify by PFCdelay after Vcc_ON, IBO sing has been turned OFF by BOdisch time after Vcc_ON, BO capacitor had enough time to charge

PFCdelay

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Figure 35. BO Input Functionality − Vbulk < Vbulk2, PFC Start Follows

Vbulk

VBO

BO_OK

Vcc

DRV_EN

Vbulk_ON

Vbulk_OFF

1 V

PFCdelay

Non−Latched Enable Input (B Version only)The non−latched input stops output drivers immediately

the BO terminal voltage grows above 2 V threshold. Theenable comparator features 100 mV hysteresis so the BOterminal has to go down below 1.9 V to recover IC operation.

This input offers other features to the NCP1392 likedimming function for lamp ballasts (Figure 36) or skipmode capability for resonant converters (Figures 37and 39).

Figure 36. Dimming Feature Implementation Using Nonlatched Input on BO Terminal

−+

−+

Q2

R2

R3 R4

R1

D1

Q1

GND

to AND gates

to AND gates

SW

VrefBO

VrefEN

Rupper

BO

Rlower

20�sFilter

Vbulk

Rt

Rfstart

CSS

Rt

VCC

DimmingInput

NCP1392

Ihyste

High Level for BOdisch time after VCC ON

To PFC Delay

0.5�sFilter

+−

+−

NCP1392B, NCP1392D

www.onsemi.com18

The dimming feature can be easily aid to the ballastapplication by adding two bipolar transistors (Figure 14).Transistor Q2 pullup BO input when dimming signal is high.

In the same time the Q1 discharges soft start capacitor viadiode D1. Ballast application is enabled (includingsoft−start phase) when dimming signal becomes low again.

Figure 37. Skip Mode Feature Implementation (Temperature Dependent, Cost Effective)

−+

−+

R1

Voltage

R2

GND

to AND gates

to AND gates

SW

VrefBO

VrefEN

Rupper

BO

Rlower

20�sFilter

Vbulk

RtRfstart

CSS

Rt

NCP1392Feedback

D1

Ihyste

High Level for BOdisch time after VCC ON

To PFC Delay

0.5�sFilter

+−

+−

Figure 38. Skip Mode with Transistor Feature Implementation (Temperature Dependent, Cost Effective)

−+

−+

R4

Voltage

R5

GND

to AND gates

to AND gates

SW

VrefBO

VrefENRupper

BO

Rlower

20�sFilter

Vbulk

RtRfstart

CSS

Rt

NCP1392Feedback

Ihyste

C1

R6

R3R2

R1

VCC

Q1

High Level for BOdisch time after VCC ON

To PFC Delay

Q2

Soft−Start After Skip (If Needed)

D1

+−−

+−

0.5�sFilter

NCP1392B, NCP1392D

www.onsemi.com19

Figure 39. Skip Mode Feature Implementation (Better Accuracy)

−+

−+

R4

Voltage

R5

GND

to AND gates

to AND gates

SW

VrefBO

VrefEN

Rupper

BO

Rlower

20�sFilter

Vbulk

RtRfstart

CSS

Rt

NCP1392Feedback

Ihyste

IC1TLV431

C1

R6

R3R2

R1

VCC

Q1

High Level for BOdisch time after VCC ON

To PFC Delay

0.5�sFilter

+−

+−

Figures 37 and 39 shows skip mode featureimplementation using NCP1392 driver. Voltage acrossresistor R1 (R4) increases when converter enters light loadconditions. The enable comparator is triggered whenvoltage across R1 is higher than Vref EN + Vf(D1) forconnection from Figure 37 (voltage across R4 is higher than1.24 V for connection from figure 16). IC then preventsoutputs from pulsing until BO terminal voltage decreasesbelow 1.92 V.

Note that enable comparator serves also as an automaticovervoltage protection. When bulk voltage is too high, theenable input is triggered via BO divider.

Following equations can be used for easy calculations ofdevices connected to Rt pin:

Minimum frequency:

Rt �3.5 � k

Frequency � q(eq. 5)

Maximum frequency where soft−start begins:

Rfstart �3.5 � k � Rt

Frequency � Rt � Rt � q � 3.5 � k(eq. 6)

The soft−start duration is set by Css capacitor:

CSS �SSduration

Rfstart � 5(eq. 7)

A resistor to set maximum frequency, if the optocoupler isfully conductive is calculated by the following equation:

R(R4�R5) � −�−3.5 � Vce_sat � k � Rt

Frequency � Rt − Rt � q − 3.5 � k � k � Vce_sat

(eq. 8)

The constants in the equations are as follows:Version B: k = 244.4�106, q = 0.555�103

Version D: k = 478.9�106, q = 1.053�103

NCP1392B, NCP1392D

www.onsemi.com20

The High−Voltage DriverFigure 40 shows the internal architecture of the

high−voltage section. The device incorporates an upperUVLO circuitry that makes sure enough Vgs is available for

the upper side MOSFET. The VCC for floating driver sectionis provided by Cboot capacitor that is refilled by externalbootstrap diode.

Figure 40. The Internal High−Voltage Section of the NCP1392

Hgd

Delay

UVDetect

HB

VCC

Lgd

GND

PulseTrigger

LevelShifter

from latchhigh if OK

from PFCDelay

Boot

S

R

Q

Q

Cboot

A

B

DEAD TIME

A

B+

Dboot

Vaux

Vbulk

The A and B outputs are delivered by the internal logic, asdepicted in block diagram. This logic is constructed in sucha way that the Mlower driver starts to pulse firs after anydriver restart. The bootstrap capacitor is thus charged duringfirst pulse. A delay is inserted in the lower rail to ensure good

matching between these propagating signals. As stated in themaximum rating section, the floating portion can go up to600 Vdc and makes the IC perfectly suitable for offlineapplications featuring a 400 V PFC front−end stage.

SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

SEATINGPLANE

14

58

N

J

X 45�

K

NOTES:1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.2. CONTROLLING DIMENSION: MILLIMETER.3. DIMENSION A AND B DO NOT INCLUDE

MOLD PROTRUSION.4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)

PER SIDE.5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBARPROTRUSION SHALL BE 0.127 (0.005) TOTALIN EXCESS OF THE D DIMENSION ATMAXIMUM MATERIAL CONDITION.

6. 751−01 THRU 751−06 ARE OBSOLETE. NEWSTANDARD IS 751−07.

A

B S

DH

C

0.10 (0.004)

SCALE 1:1

STYLES ON PAGE 2

DIMA

MIN MAX MIN MAXINCHES

4.80 5.00 0.189 0.197

MILLIMETERS

B 3.80 4.00 0.150 0.157C 1.35 1.75 0.053 0.069D 0.33 0.51 0.013 0.020G 1.27 BSC 0.050 BSCH 0.10 0.25 0.004 0.010J 0.19 0.25 0.007 0.010K 0.40 1.27 0.016 0.050M 0 8 0 8 N 0.25 0.50 0.010 0.020S 5.80 6.20 0.228 0.244

−X−

−Y−

G

MYM0.25 (0.010)

−Z−

YM0.25 (0.010) Z S X S

M� � � �

XXXXX = Specific Device CodeA = Assembly LocationL = Wafer LotY = YearW = Work Week� = Pb−Free Package

GENERICMARKING DIAGRAM*

1

8

XXXXXALYWX

1

8

IC Discrete

XXXXXXAYWW

�1

8

1.520.060

7.00.275

0.60.024

1.2700.050

4.00.155

� mminches

�SCALE 6:1

*For additional information on our Pb−Free strategy and solderingdetails, please download the ON Semiconductor Soldering andMounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

Discrete

XXXXXXAYWW

1

8

(Pb−Free)

XXXXXALYWX

�1

8

IC(Pb−Free)

XXXXXX = Specific Device CodeA = Assembly LocationY = YearWW = Work Week� = Pb−Free Package

*This information is generic. Please refer todevice data sheet for actual part marking.Pb−Free indicator, “G” or microdot “�”, mayor may not be present. Some products maynot follow the Generic Marking.

MECHANICAL CASE OUTLINE

PACKAGE DIMENSIONS

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98ASB42564BDOCUMENT NUMBER:

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PAGE 1 OF 2SOIC−8 NB

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

SOIC−8 NBCASE 751−07

ISSUE AKDATE 16 FEB 2011

STYLE 4:PIN 1. ANODE

2. ANODE3. ANODE4. ANODE5. ANODE6. ANODE7. ANODE8. COMMON CATHODE

STYLE 1:PIN 1. EMITTER

2. COLLECTOR3. COLLECTOR4. EMITTER5. EMITTER6. BASE7. BASE8. EMITTER

STYLE 2:PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #13. COLLECTOR, #24. COLLECTOR, #25. BASE, #26. EMITTER, #27. BASE, #18. EMITTER, #1

STYLE 3:PIN 1. DRAIN, DIE #1

2. DRAIN, #13. DRAIN, #24. DRAIN, #25. GATE, #26. SOURCE, #27. GATE, #18. SOURCE, #1

STYLE 6:PIN 1. SOURCE

2. DRAIN3. DRAIN4. SOURCE5. SOURCE6. GATE7. GATE8. SOURCE

STYLE 5:PIN 1. DRAIN

2. DRAIN3. DRAIN4. DRAIN5. GATE6. GATE7. SOURCE8. SOURCE

STYLE 7:PIN 1. INPUT

2. EXTERNAL BYPASS3. THIRD STAGE SOURCE4. GROUND5. DRAIN6. GATE 37. SECOND STAGE Vd8. FIRST STAGE Vd

STYLE 8:PIN 1. COLLECTOR, DIE #1

2. BASE, #13. BASE, #24. COLLECTOR, #25. COLLECTOR, #26. EMITTER, #27. EMITTER, #18. COLLECTOR, #1

STYLE 9:PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #13. COLLECTOR, DIE #24. EMITTER, COMMON5. EMITTER, COMMON6. BASE, DIE #27. BASE, DIE #18. EMITTER, COMMON

STYLE 10:PIN 1. GROUND

2. BIAS 13. OUTPUT4. GROUND5. GROUND6. BIAS 27. INPUT8. GROUND

STYLE 11:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. DRAIN 27. DRAIN 18. DRAIN 1

STYLE 12:PIN 1. SOURCE

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 14:PIN 1. N−SOURCE

2. N−GATE3. P−SOURCE4. P−GATE5. P−DRAIN6. P−DRAIN7. N−DRAIN8. N−DRAIN

STYLE 13:PIN 1. N.C.

2. SOURCE3. SOURCE4. GATE5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 15:PIN 1. ANODE 1

2. ANODE 13. ANODE 14. ANODE 15. CATHODE, COMMON6. CATHODE, COMMON7. CATHODE, COMMON8. CATHODE, COMMON

STYLE 16:PIN 1. EMITTER, DIE #1

2. BASE, DIE #13. EMITTER, DIE #24. BASE, DIE #25. COLLECTOR, DIE #26. COLLECTOR, DIE #27. COLLECTOR, DIE #18. COLLECTOR, DIE #1

STYLE 17:PIN 1. VCC

2. V2OUT3. V1OUT4. TXE5. RXE6. VEE7. GND8. ACC

STYLE 18:PIN 1. ANODE

2. ANODE3. SOURCE4. GATE5. DRAIN6. DRAIN7. CATHODE8. CATHODE

STYLE 19:PIN 1. SOURCE 1

2. GATE 13. SOURCE 24. GATE 25. DRAIN 26. MIRROR 27. DRAIN 18. MIRROR 1

STYLE 20:PIN 1. SOURCE (N)

2. GATE (N)3. SOURCE (P)4. GATE (P)5. DRAIN6. DRAIN7. DRAIN8. DRAIN

STYLE 21:PIN 1. CATHODE 1

2. CATHODE 23. CATHODE 34. CATHODE 45. CATHODE 56. COMMON ANODE7. COMMON ANODE8. CATHODE 6

STYLE 22:PIN 1. I/O LINE 1

2. COMMON CATHODE/VCC3. COMMON CATHODE/VCC4. I/O LINE 35. COMMON ANODE/GND6. I/O LINE 47. I/O LINE 58. COMMON ANODE/GND

STYLE 23:PIN 1. LINE 1 IN

2. COMMON ANODE/GND3. COMMON ANODE/GND4. LINE 2 IN5. LINE 2 OUT6. COMMON ANODE/GND7. COMMON ANODE/GND8. LINE 1 OUT

STYLE 24:PIN 1. BASE

2. EMITTER3. COLLECTOR/ANODE4. COLLECTOR/ANODE5. CATHODE6. CATHODE7. COLLECTOR/ANODE8. COLLECTOR/ANODE

STYLE 25:PIN 1. VIN

2. N/C3. REXT4. GND5. IOUT6. IOUT7. IOUT8. IOUT

STYLE 26:PIN 1. GND

2. dv/dt3. ENABLE4. ILIMIT5. SOURCE6. SOURCE7. SOURCE8. VCC

STYLE 27:PIN 1. ILIMIT

2. OVLO3. UVLO4. INPUT+5. SOURCE6. SOURCE7. SOURCE8. DRAIN

STYLE 28:PIN 1. SW_TO_GND

2. DASIC_OFF3. DASIC_SW_DET4. GND5. V_MON6. VBULK7. VBULK8. VIN

STYLE 29:PIN 1. BASE, DIE #1

2. EMITTER, #13. BASE, #24. EMITTER, #25. COLLECTOR, #26. COLLECTOR, #27. COLLECTOR, #18. COLLECTOR, #1

STYLE 30:PIN 1. DRAIN 1

2. DRAIN 13. GATE 24. SOURCE 25. SOURCE 1/DRAIN 26. SOURCE 1/DRAIN 27. SOURCE 1/DRAIN 28. GATE 1

ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.ON Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages. ON Semiconductor does not convey any license under its patent rights nor therights of others.

98ASB42564BDOCUMENT NUMBER:

DESCRIPTION:

Electronic versions are uncontrolled except when accessed directly from the Document Repository.Printed versions are uncontrolled except when stamped “CONTROLLED COPY” in red.

PAGE 2 OF 2SOIC−8 NB

© Semiconductor Components Industries, LLC, 2019 www.onsemi.com

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