NAR-2200 Manual v100 UTM1 Appliance

7/27/2019 NAR-2200 Manual v100 UTM1 Appliance

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NAR-2200 Series

Communications Appliance

Users Manual

Revision: 1.00

Portwell Inc.3F, No. 92, Sec. 1, Nei-Hu Rd., Taipei 114, Taiwan, R.O.C.Headquarter: +886-2-2799-2020 FAX: +886-2-2799-1010http://www.portwell.com.twE M A I L :I N F O @ M A I L . P O R T W E L L . C O M . T W


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NAR-2200 Users Manual 1

Table of ContentsChapter 1 Introduction ..................................................................................................2

1.1 About This Manual...................................................................................................2

1.2 Manual Organization................................................................................................2

1.3 Technical Support Information .................................................................................2

Chapter 2 Get Started....................................................................................................3

2.1 Included Hardware ..................................................................................................3

2.2 Before You Begin ....................................................................................................3

2.3 The Chassis ............................................................................................................4

2.4 Open the Chassis .................................................................... !

2.5 Install or Remove a SODIMM .................................................. !

2.6 Remove and Install Battery...................................................... !

2.7 Install Compact Flash .............................................................. !

2.8 Install 3.5 Hard disk................................................................ !

2.9 Product Specifications .............................................................................................8

2.10 Hardware Configuration Setting...............................................................................9

2.11 Use a Client Computer ..........................................................................................14

2.12 BIOS Setup Information......................................................................................... 15

Chapter 3 Operation Guide.........................................................................................22

3.1 Brief Guide of PPAP-2200 ..................................................................................... 22

3.2 System Architecture...............................................................................................22


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Chapter 1 Introduction

1.1 About This Manual

This manual describes all required information for setting up and using the NAR-2200 Allmentioned below applies to the whole system, unless specially stated.

NAR-2200 provides the essential components for delivering optimal performance andfunctionality in the value communications appliance market segment. This manual shouldfamiliarize you with NAR-2200 operations and functions. NAR-2200 family has one, Five or Sixon-board Ethernet ports to serve communication appliances, such as Firewall, which needsmore Ethernet ports to connect external network (internet), demilitarized zone and internalnetwork.

NAR-2200 features:

Versatile networking and I/O capabilities: 1, 5 or 6 Ethernet ports One COM ports

1.2 Manual Organization

The manual describes how to configure your NAR-2200 system to meet various operatingrequirements. It is divided into three chapters, with each chapter addressing a basic conceptand operation of this whole system.

Chapter 1: Introduction. This section briefly talks about how this document is organized. It includes

some guidelines for users who do not want to read through everything, but still helpsyou find what you need.

Chapter 2: Hardware Configuration Setting and Installation. This chapter shows how the hardwareis put together, including detailed information. It shows the definitions and locations ofJumpers and Connectors that you can easily configure your system. Descriptions onhow to properly mount the main memory are also included to help you get a safeinstallation. Reading this chapter will teach you how to set up NAR-2200.

Chapter 3: Operation Information. This section gives you illustrations and more information on thesystem architecture and how its performance can be maximized.

Any updates to this manual, technical clarification and answers to frequently asked questions wouldbe posted on the web site: http:// isc.portwell.com.tw

1.3 Technical Support Information

Users may find helpful tips or related information on Portwell's web site: http://www.portwell.com.tw.A direct contact to Portwell's technical person is also available. For further support, users mayalso contact Portwells headquarter in Taipei or your local distributors.

Taipei Off ic e Ph one Num ber: +886-2-27992020


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Chapter 2 Get Started

This section describes how the hardware installation and system settings should be done.

2.1 Included Hardware

The following hardware is included in your kit: PPAP-2200 Communication Appliance System Board. One null serial port cable.

2.2 Before You Begin

To prevent damage to any system board, it is important to handle it with care. The followingmeasures are generally sufficient to protect your equipment from static electricity discharge:

When handling the board, uses a grounded wrist strap designed for static discharge eliminationand touches a grounded metal object before removing the board from the antistatic bag. Handlethe board by its edges only; do not touch its components, peripheral chips, memory modules orgold contacts.

When handling memory modules, avoid touching their pins or golden edge fingers. Put the valuecommunications appliance system board and peripherals back into the antistatic bag when theyare not in use or not installed in the chassis.

Some circuitry on the system board can continue operating even though the power is switchedoff. Under no circumstances should the Lithium coin cell be used to power the real-time clock beallowed to be shorted. The coin cell can heat under these conditions and present a burn hazard.

WARNING!

1. "CAUTION: Danger of explosion if battery is incorrectly replaced. Replace only with the same orequivalent type recommended by the manufacturer. Discard used batteries according to themanufacturers instructions"

2. This guide is for technically qualified personnel who have experience installing and configuringsystem boards. Disconnect the system board power supply from its power source before youconnect/disconnect cables or install/remove any system board components. Failure to do this canresult in personnel injury or equipment damage.

3. Avoid short-circuiting the lithium battery; this can cause it to superheat and cause burns if touched.

4. Do not operate the processor without a thermal solution. Damage to the processor can occur inseconds.

5. Do not block air vents. Minimum 1/2-inch for clearance required.


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2.3 The Chassis

The system is integrated in a customized chassis (Fig. 2-1, Fig . 2-2). On the front panel you willfind the Power LED, Hard Disk LED and LAN LED. The back panel has Six LAN ports and a

COM port.

Fig. 2-1 Front view of the Chassis

Fig. 2-2 Back view of the Chassis

2.4 Open the Chassis

1. Take off the four screws (three at therear side and two at the right/left sideand remove the top lead (Fig. 2-3).

Fig. 2-3 Take off two screws

2. The top lead (Fig. 2-4) can be removed from the base stand (Fig. 2-5).

Fig. 2-4 The top lead Fig. 2-5 The base stand


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2.5 Install or Remove a SODIMM

Follow these steps to upgrade or remove RAM module:

3. Install the system memory by pulling the sockets arm and pressing it into the slot gently.(Fig. 2-6, 2-7)

Fig. 2-6 The memory slot Fig. 2-7 Install SODIMM

4. By pulling the arms, the SODIMM can eject itself (Fig. 2-8).

Fig. 2-8 Eject a SODIMM module


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2.6 Remove and Install Battery

5. Press the metal clip back to eject the button battery (Fig. 2-9).

6. Replace it with a new one by pressing the battery with fingertip to restore the battery(Fig. 2-10).

2.7 Install Compact Flash

The system has an internal drive bay for one Compact Flash card drive. If the CF is not pre-installed, you can install it by yourself. Follow the steps below to install the CF:

7. Fasten the five screws to lock bracket together (Fig. 2-11a, 2-11b).

Fig. 2-11a Remove L type base under buttoncase

Fig. 2-11b Pu sh CF into the bracket

8. Completion CF to the System Chassis (Fig. 2-12)

Fig. 2-12 complet ion CF in system Fix all screws back (Fig. 2-13).

Fig. 2-9 Eject the battery Fig. 2-10 Restor ethe battery


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2.8 Install 3.5Hard disk

The system has an internal drive bay for one 3.5" hard disk drive. If the HDD is not pre-installed,you can install by yourself. You need the parts from the accessory-bag as shown on Figure 2-14.

They are one HDD-bracket, several screws. (from left to right).

(Fig. 2-14)3.5 HDD kit (Fig. 2-15) Fix the hard disk drive on the HDDbracket with four screws. Plug the IDE cable intohard disk drive connector

(Fig. 2-16) Completion HDD with bracket andfixed screws.

(Fig. 2-17) Finished.

9. Connect Power Cable and IDE Cable before assemble hard disk. After assemble hard disk,put IDE Cable and Power cable into main board.


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2.9 Product Specifications

Model: NAR-2200

Main Processor: NAR-2200-601: Intel

R915GME platform w/ Celeron-M/Pentium-M socket

type CPU desktop platform.

NAR-2200-621: Intel 915GME platform w/ ULV Celeron-M BGA600MHz CPU desktop platform.

BIOS: Award system BIOS with 512KB flash ROM to support DMI, PnP, APMfunction

Main Memory: Two 200-pin SODIMM socket supports DDRII.

DDR2 400/533, up to 2GB.

Chipset:

North Bridge: Intel

R

915GME South Bridge: ICH6-M

SATA Interface 2 Serial ATA ports supported.

VGA One 2x5 Pin pin-header for internal VGA interface is required.

PCI IDE Interface: One 40 Pin for DMA/33/66/100 IDE Storage

Serial Ports: Support two high-speed 16550 compatible UARTs with 16-byte T/RFIFOs

USB Interface: Support two USB 2.0 ports for high speed I/O peripheral devices

Auxiliary I/O Interfaces: System reset switch, power okay LED, Ethernet activity LED, Ethernetspeed LED, general purpose LED, alert LED, Bypass LED and HDD LEDinterface

Power Input: Support one AC Adaptor with Adaptor input (power requirement: Input:100-240V, Output: 12V == 7A)

FSP084-1ADC11, FSP Power Supply (AC-DC) Adapter. Black.

On-board Ethernet: Maximal 6 Ethernet interfaces with RJ45 connector to be built onboard. Ethernet controller: The two PCI interfaces should be co-layout with

IntelR

82541PI (GbE) and IntelR

82551ER (FE). NAR-2200-601 is PGA with Four 82573L GbE ports (four ports from leftside) + Two 82551ER FE. NAR-2200-621 is BGA with Four 82573L GbE ports (four ports from leftside) + Two 82551ER FE.

Hardware Monitor: Support on-board hardware monitor for CPU fan, System fan ,System voltages

EnvironmentalRequirements:

Operating Temperature: 5C ~ 40C

Storage Temperature: 0C ~ 70C

Relative Humidity: 5% 95%, non-condensing

Dimension: 214mm(L) x 225mm (W) x 52mm (H)

Eth-0 Eth-1 Eth-2 Eth-3 Eth-4 Eth-5 ConsoleUSB

Bypass SegmentPXE port

Full configuration


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2.10 Hardware Configuration Setting

This section gives the definitions and shows the positions of jumpers, headers and connectors.All of the configuration jumpers on PPAP-2200 are in the proper position. The default settings

set by factory are marked with a star ( ).

J u m p e r s

In general, jumpers on PPAP-2200 system board are used to select options for certainfeatures. Some of the jumpers are configurable for system enhancement. The others arefor testing purpose only and should not be altered. To select any option, cover the jumpercap over (Short) or remove (NC) it from the jumper pins according to the followinginstructions. Here NC stands for Not Connected.

P

PAP-2200 Jum per Table


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PPAP-2200 ZR0 jumper setting: (default setting)

JP2: CMOS Clear

JP2 Function

1-2 Short Normal Operation 2-3 Short Clear CMOS Contents

JP4: FSB Frequency selection

JP4 Function

1-2 short CPU FSB frequency=400MHz

2-3 short CPU FSB frequency=533MHz

Note: The DDR2 frequency is followed the CPU FSB frequency. For example, the DDR2module populated is DDR2 533, the CPU must be 533MHz FSB. Please use same frequency ofmemory module and CPU.

Neither CPU/DDR=533/400 nor 400/533 are allowed. This is the limitation of 915GM chipset.

CPU VCCA voltage input (JP5B)

JP5B Function

2-4 short VCCA=1.8V (Banias)

4-6 short VCCA=1.5V ( Dothan)

Note: wrong voltage selection may damage the CPU. Please survey the CPUs type beforesetup this jumper setting.

PCI-E x16 graphic port enable/disable (JP5C)

JP5C Function

7-8 short Reserved

7-8 open PCI-E x16 graphic port enabled

DDR2 memory frequency selection (JP5D)

JP5D Function

9-10 open

11-12 open

reserved

9-10 open11-12 short

The memory module is DDR2 400

9-10 short11-12 open

The memory module is DDR2 533

9-10 short11-12 short

reserved

J15: Reset to default function

J15 Function

1-2 Short RESET TO DEFAULT

1-2 Open Normal mode


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Connector Setting

Connector Function Remark

J1~J6 LAN LED

J7 HDD LED +Power LED

J8 TV out connectorJ9 PS/2 Keyboard & Mouse Connector

J10 CPU FAN connector

J11 IDE connector

J12 J13 SATA connector

J14 +5V & +12V power connector(only output)

J15 RESET TO DEFAULT

J16 CPLD Programming connector

J17 8-bit GPO LED connectorJ18 External thermal sensor connector

J19 PCI ConnectorJ20 PCI-E Connector

J22 COM2 connector

J23 POWER S/W

J24~J29 RJ45 connector

J30 USB connector

J31 POWER JACK connector

J32 SYS FAN connector

J33 CF Connector

CN2 VGA connector

CN4 COM1 connector

JP3 By-pass LED

J9: PS/2 Keyboard & Mouse Connector

PIN No. Signal Description PIN No. Signal Description

1 Keyboard data 2 Mouse data

3 KB/MS ground 4 KB/MS VCC (+5V)

5 Keyboard clock 6 Mouse clock

7 NC (key) 8 NC (key)

J17: 8-bit GPIO connector define

Pin Signal Name Pin Signal Name

1 GPIO 2 GPIO

3 GPIO 4 GPIO

5 GPIO 6 GPIO

7 GPIO 8 GPIO

9 Ground 10 +5V


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J7: HDD LED +Power LED connector define

Pin Signal Name Pin Signal Name1 +5V 2 -HD

3 +5V 4 -PWR

CN2: VGA connector define

Pin Signal Name Pin Signal Name

1 RED 2 DDCCLK

3 GREEN 4 Ground

5 BLUE 6 DDCDATA

7 HSYNC 8 Ground

9 VSYNC 10 N/C


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2.11 Use a Client Computer

C o n n e c t i o n U s i n g H y p e r T e r m i n a l

If users use a headless NAR-2200, which has no mouse/keyboard and VGA outputconnected to it, the console may be used to communicate with NAR-2200.

To access NAR-2200 via the console, Hyper Terminal is one of the choices. Follow thesteps below for the setup:

1. Execute HyperTerminal under C:\Program Files\Accessories\HyperTerminal

2. Enter a name to create new dial

3. For the connection settings, make it Direct to COM1.

4. Please make the port settings to Baud rate 19200, Parity None, Data bits 8, Stop bits 1


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5. Turn on the power of NAR-2200, after following screen was shown

6. Users can then see the boot up information of NAR-2200

When message Hit if users want to run Setup appear during POST, afterturning on or rebooting the computer, press key im m e d ia t e ly to enter BIOSsetup program.

7. This is the end of this section. If the terminal did not port correctly, please check the previoussteps.

2.12 BIOS Setup Information

NAR-2200 is equipped with the Award BIOS within Flash ROM. The BIOS has a built-in setupprogram that allows users to modify the basic system configuration easily. This type ofinformation is stored in CMOS RAM so that it still retains during power-off periods. When system

is turned on, NAR-2200 communicates with peripheral devices and checks its hardwareresources against the configuration information stored in the CMOS memory. Whenever an erroris detected, or the CMOS parameters need to be initially defined, the diagnostic program willprompt the user to enter the Setup program. Some errors are significant enough to abort thestart-up.

E n te r in g S etu p

When users see the message Hit ifusers want to run Setup, after turning on orrebooting the computer, press key im m e d ia t e ly to enter BIOS setup program.

If users want to enter Setup but fail to respond before the message disappears, pleaserestart the system either by first turning it off and followed by turning it on (COLD START)or simply press the "RESET" button. WARM START (press , , and keys simultaneously) will do, too. Unless users press the keys at the right time, thesystem will not boot, an error message will display and users will be asked to do it again.

When no setting is stored in BIOS or the setting is missing, a message Press torun Setup will appear. Then press to run Setup or resume HIFLEX BIOS Setup.

users can use the keyboard to choose among options or modify the system parameters tomatch the options with your system. The table shown on next page will show all ofkeystroke functions in BIOS Setup.

K e y s t o n a v i g at e w i t h i n S e tu p m e n u


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Key Function

Up ( ) Move to the previous item

Down ( ) Move to the next item

Left ( ) Move to the item on the left (menu bar)

Right ( ) Move to the item on the right (menu bar)

Enter Enter the item you desiredPgUp Increase the numeric value or make changes

PgDn Decrease the numeric value or make changes

Increase the numeric value or make changes

Decrease the numeric value or make changes

Esc

Main Menu:Quit and not save changes into CMOS

Status Page Setup Menu and Option Page Setup Menu:Exit current page and return to Main Menu

F1General help on SETUP navigation keys

F5 Load previous values from CMOS

F6 Load the fail-safe defaults from BIOS default table

F7 Load the optimized defaults

F10 Save all the CMOS changes and exit

Main Menu

Once users enter NAR-2200 Award BIOS CMOS Setup utility, should start with the Main Menu.The Main Menu allows user to select from eleven setup functions and two exit choices. Usearrow keys to switch among items and press to accept or bring up the sub-menu.Ph o e n i x Awa rd BIOS CM OS Setu p Ut i l i ty

NOTE: It is strongly recommended to reload the optimized default setting if CMOS is lost or BIOS is updated.


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Standard CMOS Setup Menu

This setup page includes all the items within standard compatible BIOS. Use the arrowkeys to highlight the item and then use the / or / keys to select the

value or number in each item and press to certify it.

Follow command keys in CMOS Setup table to change Date, Time, Drive type and BootSector Virus Protection Status.

Sc re e n Sh o t: Ph o e n i x Aw a rd BIOS CM OS Setu p Ut i l i ty


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M e n u Se l e c t i o n s

Item Options Description

Date mm:dd:yySet the system date. Note that the 'Day'automatically changes when set the date

Time hh:mm:ss Set the system time

Video

EGA/VGA

CGA 40

CGA 80

MONO

Select the default video device

Base Memory N/ADisplay the amount of conventional memorydetected during boot up

Extended Memory N/ADisplay the amount of extended memorydetected during boot-up

Total Memory N/A Display the total memory available in the system

A d v a n c e B IOS F e atu r e s

This section allows user to configure system for basic operation. Users will be able toselect the systems default speed, boot-up sequence, keyboard operation, shadowing andsecurity.

Sc re e n Sh o t: Ph o e n i x Aw a rd BIOS CM OS Setu p Ut i l i ty

Internal Cache/Extern al Cache

These two categories speed up memory access. However, it depends on CPU/chipset


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design.

Enabled Enable cache

Disabled Disable cache

Q u i c k P o w e r O n S e l f T es t

This category speeds up Power On Self Test (POST) after power up the computer. If it isset to Enable, BIOS will shorten or skip some check items during POST.

Enabled Enable quick POST

Disabled Normal POST

B o o t U p N u m L o c k S t at u s

Select power on state for NumLock.

The choice: Enabled/Disabled.

Gate A20 Option

This entry allows user to select how the gate A20 is handled. The gate A20 is a deviceused to address memory over 1 Mbytes. Originally, the gate A20 was handled via a pin

on the keyboard. But now, though keyboards still provide this support, it is more common,and much faster, for the system chipset to provide support for gate A20.

Normal Keyboard

Fast Chipset

Typematic Rate Sett ing

Keystrokes repeat at a rate determined by the keyboard controller. When enabled, thetypematic rate and typematic delay can be selected.


Typem atic Rate (Chars/Sec)

Set the how many number of times a second to repeat a keystroke when a key is holdingdown.

The choice: 6, 8, 10, 12, 15, 20, 24 and 30.


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Typematic Delay (Msec)

Set the delay time after the key is held down before it begins to repeat the keystroke.

The choice: 250, 500, 750 and 1000.

S ec u r i ty O p t i o n

Select whether the password is required every time the system boots or only when entersetup.

SystemThe system will not boot and access to Setup will be denied if the correctpassword is not entered at the prompt.

SetupThe system will boot and access to Setup will be denied if the correct passwordis not entered at the prompt.

Note: To disable security, select PASSWORD SETTING at Main Menu and then user will be asked to enterpassword. Do not type anything and simply press , it will disable security. Once the security isdisabled, the system will boot up and user can enter Setup freely.

OS Select fo r DRA M > 64MB

Select the operating system that is running with more than 64MB of RAM on the system.

The choice: Non-OS2, OS2.

C o n s o l e R ed i r e c t i o n

Set the UNIX Console redirect to the terminal from COM1.


B a u d R a te

Set the RS-232 baud rate speed.

The choice: 9600, 19200, 38400, 57600 and 115200.

A d v a n c e d C h i p s e t F e atu r e s

This section allows user to configure system for AT clock, DRAM timings...


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Integrated Peripherals

O n b o a r d L A N B o o t R O M

User can press L for boot from LAN.


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Chapter 3 Operation Guide

3.1 Brief Guide of PPAP-2200

PPAP-2200 is a Communication Appliance computing board based on Intel 915GV chipsettechnology. PPAP-2200 has SIX on-board LAN ports to serve communication appliances, suchas Firewall, which needs SIX Ethernet ports to connect external network (internet), demilitarizedzone and internal network. Different I/O management policies can be applied respectively toindividual network to achieve the highest security level. The target market segment iscommunication appliance including Virtual Private Network, Load Balancing, Quality of Service,Intrusion Detection, Virus Detection, Firewall and Voice Over IP.

This PPAP-2200 system board is eligible with INTEL processor package (INTEL Celeron M) andtwo slot for DDR2RAM module. The enhanced on-board PCI IDE interface supports 1 drive upto PIO mode 4 timing and Ultra DMA/100 synchronous mode, SATA I feature. The on-board

super I/O chipset integrates two serial ports driven by two high performance 16550C-compatibleUARTs to provide 16-byte send/receive FIFOs. The two Universal Serial Bus ports provide high-speed data communication between peripherals and PC.

The on-board flash ROM is used to make the BIOS update easier. The high precision Real TimeClock/Calendar is built to support Y2K for accurate scheduling and storing configurationinformation. All of these features make PPAP-2200 excellent in stand-alone applications.

If any of these items is damaged or missing, please contact your vendor and save all packingmaterials for future replacement and maintenance.

F i g u r e 3 -1 P PA P -2 20 0 B o a r d

3.2 System Architecture

The following illustration of block diagram will show how PPAP-2200 gives a highly integratedsystem solution. The most up-to-date system architecture of PPAP-2200 includes two mainchips. It contains INTEL 915GM and ICH-6 M to support INTEL Celeron -M processor, DDR2SODIMM, USB 2.0 port, communication, Ultra DMA/100 IDE Master storage, SATA I storage.The on-board super ICH6-M supports two UARTs and hardware monitoring.

PPAP-2200 has built-in onboard INTEL celeron-M processor EBGA package 400MHz systembus for cost-effective and high performance application.

The INTEL 915GM provides a completely integrated solution for the system controller and datapath components in a INTEL mobile processor system.

The INTEL 82801DBM I/O Controller Hub mobile (ICH6-M) provides a highly integratedmultifunction for the best industry applications. It supports up to for Ultra ATA/33/66/100 IDEmaster interface, SATA I interface. Universal Serial Bus (USB2.0) controllers,


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All detailed operating relations are shown in Fig. 3-2(PPAP-2200 System Block Diagram).

Fig u re 3 -2 P P A P -2 20 0 B lo ck Diag ra m

Intel Celeron -M/

Pentium -M

Intel Celeron -M/

Pentium -M DDR2 400/533DDR2 400/533

82915GME

MCH

DMI (1GB/s) ineach direction

FSB: 400/533 MHz

PCI -E x4

golden finger

SATA-1

SATA-2

PCI Vertical slot

BIOS/Firmware

4 PCI-E x1

USB -pin

-------------

Dual USB

RJ45

System

Console

DDR2 400/533DDR2 400/533

PCI-

E x4

Add-

on Module in R/M

PCIAdd-

on Module

(Crypto card)

PCI-E

GbE -1(82573L)

PCI-E

GbE -0(82573L)

RJ45 RJ45 RJ45 RJ45

Bypass 0

PCI-E

GbE -3(82573L)

PCI -E

GbE -2(82573L)

PPAP-2200VL-4201 Block Diagram

PCI

GbE -0(82551ER

PCI

GbE -1(82551ER )

RJ45 RJ45

40-pin IDEconnector

IDE CF -Socke

2 PCI

82801FBM

ICH6-M


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Chapter 4 Programming guide

4.1 GPIO Sample Code

// Portwell Confidential !// Portwell Intellectual Property, All rights reserved.////////////////////////////////////////////////////////////////////////////////////// Program : 3727GPIO.CPP// Descript. : PPAP-3727 GPIO test program// Designer : Frank Hsu// Language : Borland C++ 5.02// O.S. : MS-DOS/Win98 only// Upddate : 11222006 Release////

////////////////////////////////////////////////////////////////////////////////////// GPIO on PPAP-3727// PPAP-3727 J30_Pin1=GPIO1:from SUPER I/O_GPIO17// J30_Pin2=GPIO2:from SUPER I/O_GPIO16// J30_Pin3=GPIO3:from SUPER I/O_GPIO15// J30_Pin4=GPIO4:from SUPER I/O_GPIO14// J30_Pin6=GPIO5:from SUPER I/O_GPIO10// J30_Pin7=GPIO6:from SUPER I/O_GPIO11// J30_Pin8=GPIO7:from SUPER I/O_GPIO12// J30_Pin9=GPIO8:from SUPER I/O_GPIO13// >

//// Programming Guide :// Step1 : CR29_Bit[7..6]P[0,1] to select GPIO10~17 pin// Step2 : LD7_CR07h_P[07h] : point to LD7// Step3 : LD7_CR30h_bit0_P1 : Enable LD7// Step4 : Start 4 test items ( t1 , t2, t3, t4 )// LD7_CRF0h definition : GPIO17 ~ 10 : 1 = input , 0 = output pin// LD7_CRF2h_P[00h] : Always let CRF1 ( GPIO data port ) non-invert.// LD7_CRF1h : GPIO17~10 data port ,// t1 : GPO17,16,15,14 output [1,1,1,1] to GPI10,11,12,13// t2 : GPO17,16,15,14 output [0,0,0,0] to GPI10,11,12,13// t3 : GPO10,11,12,13 output [1,1,1,1] to GPI17,16,15,14// t4 : GPO10,11,12,13 output [0,0,0,0] to GPI17,16,15,14

//

#include "stdlib.h"#include "conio.h"#include "stdio.h"#include "dos.h" // for delay(), and sleep()

// Global constant --------- Start --------------#define config_W83627 0x2E // Hardware strapping#define GPIO1_LDN 0x07 // W83627 GPIO1 LDN = 0x07 for GP10~17#define CR07 0x07#define CR29 0x29#define CR30 0x30

#define CRF0 0xF0#define CRF1 0xF1#define CRF2 0xF2#define portb 0x61#define refresh_status 0x10


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void fixdelay_15us (){

// delay 15 usunsigned char char_ah,char_al ;

char_ah = inportb ( portb ) & refresh_status ;fixdelay_loop :

char_al = inportb ( portb ) & refresh_status ;if(char_ah == char_al ) goto fixdelay_loop ;

} // end of fixdelay_15us

main(){

unsigned char al_char ;

printf("\n\n PORTWELL PPAP-3727 GPIO,3727GPIO.exe, V1.00 11-22-2006,All rights reserved.\n\n");

printf("\n PPAP-3727 J30_Pin1=GPIO1:from SuperIO_GPIO17 ");

printf("\n J30_Pin2=GPIO2:from SuperIO_GPIO16 ");printf("\n J30_Pin3=GPIO3:from SuperIO_GPIO15 ");printf("\n J30_Pin4=GPIO4:from SuperIO_GPIO14 ");printf("\n J30_Pin6=GPIO5:from SuperIO_GPIO10 ");printf("\n J30_Pin7=GPIO6:from SuperIO_GPIO11 ");printf("\n J30_Pin8=GPIO7:from SuperIO_GPIO12 ");printf("\n J30_Pin9=GPIO8:from SuperIO_GPIO13 ");printf("\n\n Put 4 jumper cap on J20 pin header pin1-6, 2-7, 3-8,4-9.\n");printf("\n\n Be careful !!! J30 pin5 (GND), and pin10 (Vcc) can not be shorted\n");

printf("\n\n Ready ? If yes , then Press any key to start test .......");getche() ;

// W83627THG Super IO GP10~13 , 23~26 are used for PPAP-3719 GPIO// GP10~13 located at LD7 , GP23~26 located at LD8

// ***** First : define the Multiplexed pins --- startoutportb ( config_W83627 , 0x87 ) ; // enter config modeoutportb ( config_W83627 , 0x87 ) ;fixdelay_15us();

// CR29Bit[7,6]_P[01] , Define the multiplexed pin,GPIO10~17outportb ( config_W83627 , CR29 ) ;al_char = ( inportb ( config_W83627 +1 ) & 0x7D ) | 0x40 ;outportb ( config_W83627 , CR29 ) ;outportb ( config_W83627+1 , al_char ) ;

// Enable GPIO1 and GPIO2 and Set Non-inverseoutportb ( config_W83627 , CR07 ) ;outportb ( config_W83627+1 , GPIO1_LDN ) ;

outportb ( config_W83627 , CR30 ) ;al_char = inportb ( config_W83627 +1 ) | 0x01 ;outportb ( config_W83627 , CR30 ) ;outportb ( config_W83627+1 , al_char ) ;

outportb ( config_W83627 , CRF2 ) ;outportb ( config_W83627+1 , 0x00 ) ;//LD8---------------------------------------------------

/*


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Testing way :Use PPAP-3719 GPIO ( 8 bi-direction pins from Super IO W83627THG )Initialization for W83627THG must be done first in Main().--- t1SGPO17 Write 0 to SGPI10 , SGPI10 = 0 ? ,if yes, pass ; if no, failedSGPO16 Write 0 to SGPI11 , SGPI11 = 0 ? ,if yes, pass ; if no, failedSGPO15 Write 0 to SGPI12 , SGPI12 = 0 ? ,if yes, pass ; if no, failedSGPO14 Write 0 to SGPI13 , SGPI13 = 0 ? ,if yes, pass ; if no, failed--- t2

SGPO17 Write 1 to SGPI10 , SGPI10 = 1 ? ,if yes, pass ; if no, failedSGPO16 Write 1 to SGPI11 , SGPI10 = 1 ? ,if yes, pass ; if no, failedSGPO15 Write 1 to SGPI12 , SGPI10 = 1 ? ,if yes, pass ; if no, failedSGPO14 Write 1 to SGPI13 , SGPI10 = 1 ? ,if yes, pass ; if no, failed--- t3SGPO10 Write 0 to SGPI17 , SGPI26 = 0 ? ,if yes, pass ; if no, failedSGPO11 Write 0 to SGPI16 , SGPI25 = 0 ? ,if yes, pass ; if no, failedSGPO12 Write 0 to SGPI15 , SGPI24 = 0 ? ,if yes, pass ; if no, failedSGPO13 Write 0 to SGPI14 , SGPI23 = 0 ? ,if yes, pass ; if no, failed--- t4SGPO10 Write 1 to SGPI17 , SGPI26 = 1 ? ,if yes, pass ; if no, failedSGPO11 Write 1 to SGPI16 , SGPI25 = 1 ? ,if yes, pass ; if no, failedSGPO12 Write 1 to SGPI15 , SGPI24 = 1 ? ,if yes, pass ; if no, failed

SGPO13 Write 1 to SGPI14 , SGPI23 = 1 ? ,if yes, pass ; if no, failed*/

// GPIO Direction setting for t1 and t2 test items ==============outportb ( config_W83627 , CR07 ) ;outportb ( config_W83627+1 , GPIO1_LDN ) ;

outportb ( config_W83627 , CRF0 ) ;outportb ( config_W83627+1 , 0x0F ) ; // Input direction ; SGPI10~13

// Output direction ; SGPO17~14

// t1 -----outportb ( config_W83627 , CR07 ) ;outportb ( config_W83627+1 , GPIO1_LDN ) ;

outportb ( config_W83627 , CRF1 ) ;outportb ( config_W83627+1 , 0x0F ) ; // Write 0 ,

outportb ( config_W83627 , CRF1 ) ;al_char = inportb ( config_W83627+1 ) & 0x0F ;

if( al_char == 0x00 ) goto next_t2 ;outportb ( config_W83627 , 0xaa ) ; // exit config modeprintf("\n\n Error#01 : PPAP-3727 GPIO test failed(GPO17->GPI10_w0x0). But=0x%X \n\n",al_char);

exit(1);

// t2 ------next_t2:outportb ( config_W83627 , CRF1 ) ;outportb ( config_W83627+1 , 0xFF ) ; // Write 1 ,

outportb ( config_W83627 , CRF1 ) ;al_char = inportb ( config_W83627+1 ) & 0x0F ;

if( al_char == 0x0F ) goto next_t3 ;outportb ( config_W83627 , 0xaa ) ; // exit config modeprintf("\n\n Error#02 : PPAP-3727 GPIO test failed(GPO17->GPI10_w0xF). But=0x%X \n\n",al_char);exit(1);

// GPIO Direction setting for t3 and t4 test items ==============


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next_t3:outportb ( config_W83627 , CRF0 ) ;outportb ( config_W83627+1 , 0xF0 ) ; // Output direction ; SGPO10~13

// Input direction , SGPI17~14// t3 -----------------outportb ( config_W83627 , CRF1 ) ;outportb ( config_W83627+1 , 0xF0 ) ; // Write 0 ,

outportb ( config_W83627 , CRF1 ) ;

al_char = inportb ( config_W83627+1 ) & 0xF0 ;

if( al_char == 0x00 ) goto next_t4 ;outportb ( config_W83627 , 0xaa ) ; // exit config modeprintf("\n\n Error#03 : PPAP-3727 GPIO test failed(GPO10->GPI17_w0x0). But=0x%X \n\n",al_char);exit(1);

// t4 ------------------next_t4:outportb ( config_W83627 , CRF1 ) ;outportb ( config_W83627+1 , 0xFF ) ; // Write 1 ,

outportb ( config_W83627 , CRF1 ) ;

al_char = inportb ( config_W83627+1 ) & 0xF0 ;

if( al_char == 0xF0 ) goto gpio_done ;

outportb ( config_W83627 , 0xaa ) ; // exit config modeprintf("\n\n Error#04 : PPAP-3727 GPIO test failed(GPO10->GPI17_w0xF). But=0x%X \n\n",al_char);exit(1) ; //

gpio_done :

outportb ( config_W83627 , 0xaa ) ; // exit config modeprintf("\n\n PPAP-3727 GPIO test okay. ^_^ \n\n");

exit(0);

} // end of main()


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4.2 WDT Sample Code

/include/gloab.h

unsigned int cnt=0;

/include/WDT.h

#include // Global constant --------- Start --------------#define LDN8 0x08 // WDT in LDN8#define CR07 0x07#define CR20 0x20#define CR2B 0x2B#define CR2D 0x2D#define CR30 0x30#define CRF5 0xF5#define CRF6 0xF6#define CRF7 0xF7#define portb 0x61

#define refresh_status 0x10#define Bit7_6_AND0 0x3F#define Bit4_AND0 0xEF#define Bit3_AND0 0xF7#define Bit2_AND0 0xFB#define Bit0_AND0 0xFE#define Bit4_OR1 0x10#define Bit3_OR1 0x08#define Bit2_OR1 0x04#define Bit0_OR1 0x01#define second_unit 0x69// Global constant --------- End --------------

// Global Variable ----- Start ---time_t t;struct tm *d;unsigned char W627_CONFIG = 0x2E , W627_DATA = 0x2F , W627_EDHG = 0x00 ;

// Global Variable ---- end -----


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/application/test_all/common.c

#include #include unsigned int cnt=0;unsigned char *status[5] = {"","Status=Ok","Status=Fail","Status=Testing"};/*------------------------------------------------------------------------*/

void showprocitem(int fn){

system("clear");printf("+--------------------------------------------------------------------+\n");printf("| Portwell watch dog timer test program version:1.00 |\n");printf("| Author:Jason Wu |\n");printf("+--------------------------------------------------------------------+\n");printf("| Product select |\n");printf("| [\x1b[%d;%dm1\x1b[m] NAR5510/NAR7090 [\x1b[%d;%dmESC\x1b[m] exit program

|\n",36,1,36,1);printf("| \x1b[%d;%dmSelect function\x1b[m:%-24c\x1b[%d;%dmstatus\x1b[m:\x1b[%d;%dm%-

20s\x1b[m|\n",33,1,fn,33,1,31,1,"");printf("+--------------------------------------------------------------------+\n\n");

}void showtitle_THG(unsigned int sts){

system("clear");printf("+----------------------------------------------------------------------------+\n");printf("| Portwell watch dog timer test program version:1.00 |\n");printf("| Author:Jason Wu |\n");printf("+----------------------------------------------------------------------------+\n");printf("| Product Type :NAR-5510/NAR-7090

\x1b[%d;%dm%15s\x1b[m|\n",33,1,status[sts]);printf("| Refresh SYS_WDT 1 times. < choice > Twd : Refresh interval |\n");printf("| PRESS Ctrl+C KEY TO STOP REFRESHING SYS_WDT & DISABLE SYS_WDT. |\n");printf("| < 1 >: 2 seconds : 0.385 second. < A >: 40 seconds : 34.011 second. |\n");

printf("| < 2 >: 3 seconds : 1.374 seconds. < B >: 48 seconds : 40.824 seconds. |\n");printf("| < 3 >: 4 seconds : 2.363 seconds. < C >: 60 seconds : 51.044 seconds. |\n");printf("| < 4 >: 8 seconds : 5.604 seconds. < D >: 120 seconds : 102.088 seconds. |\n");printf("| < 5 >: 10 seconds : 7.033 seconds. < E >: 4 minutes : 204.176 seconds. |\n");printf("| < 6 >: 16 seconds : 13.736 seconds. < F >: 8 minutes : 408.352 seconds. |\n");printf("| < 7 >: 20 seconds : 17.033 seconds. < G >: 10 minutes : 510.439 seconds. |\n");printf("| < 8 >: 24 seconds : 20.330 seconds. < H >: 30 minutes :1531.318 seconds. |\n");printf("| < 9 >: 32 seconds : 27.198 seconds. < I >: 60 minutes :3060.000 seconds. |\n");printf("| < 0 >: Enable WDT ( This will reset system within 1 second.) |\n");printf("| : return main window |\n");

printf("+----------------------------------------------------------------------------+\n");}void showtitle_EDHG(unsigned int sts)

{system("clear");printf("+----------------------------------------------------------------------------+\n");printf("| Portwell watch dog timer test program version:1.00 |\n");printf("| Author:Jason Wu |\n");printf("+----------------------------------------------------------------------------+\n");printf("| Product Type :NAR-5510/NAR-7090

\x1b[%d;%dm%15s\x1b[m|\n",33,1,status[sts]);printf("| Refresh SYS_WDT 1 times. < choice > Twd : Refresh interval |\n");printf("| PRESS Ctrl+C KEY TO STOP REFRESHING SYS_WDT & DISABLE SYS_WDT. |\n");printf("| < 1 >: 8 ms : 4.350 ms. < A >: 2 seconds : 0.385 second. |\n");printf("| < 2 >: 32 ms : 24.675 ms. < B >: 8 seconds : 5.604 seconds. |\n");printf("| < 3 >: 96 ms : 78.750 ms. < C >: 16 seconds : 13.736 seconds. |\n");printf("| < 4 >: 128 ms : 105.750 ms. < D >: 32 seconds : 27.198 seconds. |\n");printf("| < 5 >: 146 ms : 121.500 ms. < E >: 48 seconds : 40.824 seconds. |\n");printf("| < 6 >: 186 ms : 161.700 ms. < F >: 60 seconds : 51.044 seconds. |\n");printf("| < 7 >: 226 ms : 202.800 ms. < G >: 120 seconds : 102.088 seconds. |\n");printf("| < 8 >: 246 ms : 232.800 ms. < H >: 4 minutes : 204.176 seconds. |\n");


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printf("| < 9 >: 255 ms : 237.000 ms. < I >: 30 minutes :1531.318 seconds. |\n");printf("| < 0 >: Enable WDT ( This will reset system within 1 second.) |\n");printf("| : return main window |\n");

printf("+----------------------------------------------------------------------------+\n");}unsigned int WDT_test_T(void){

unsigned char rst=0x00;W627_Init();

showtitle_THG(0x00);do{

if(((rst>=0x30)&&(rst=0x41)&&(rst=0x61)&&(rst


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break ;case 0x49 : WDT_RFSHs_m(0x5a,60,3060.000) ;


break ;case 0x30 :

resetpc();break;

}

showtitle_THG(cnt);printf("\r\x1b[%d;%dH\x1b[%d;%dmplease select

key:\x1b[m",20,0,33,1);}else{

printf("\r\x1b[%d;%dH\x1b[%d;%dmplease select key:\x1b[m",20,0,33,1);}rst=getchar();

}while(rst != 0x1b);exit_W627();

return 0;}

unsigned int WDT_test_ED(void){

unsigned char rst=0x00;W627_Init();showtitle_THG(0x00);do{

if(((rst>=0x30)&&(rst=0x41)&&(rst=0x61)&&(rst


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break ;case 0x45 : WDT_RFSHs_m(0x69,48,40.824) ;




break ;

case 0x47 : WDT_RFSHs_m(0x69,120,102.088) ;break ;

case 0x67 : WDT_RFSHs_m(0x69,120,102.088) ;break ;

// H,I Minute unit -------------------------------case 0x48 : WDT_RFSHs_m(0x5a,4,204.176) ;




break ;

case 0x30 :resetpc();

break;}

showtitle_THG(cnt);printf("\r\x1b[%d;%dH\x1b[%d;%dmplease select

key:\x1b[m",20,0,33,1);}else{

printf("\r\x1b[%d;%dH\x1b[%d;%dmplease select key:\x1b[m",20,0,33,1);}rst=getchar();

}while(rst != 0x1b);exit_W627();

return 0;}


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/application/test_all/main.c

#include extern void showprocitem(int fn);extern unsigned int WDT_test_T(void);/*------------------------------------------------------------------------*/int main(void){

char rst=0x30;showprocitem(rst);do{

if(rst == 0x31){WDT_test_T();showprocitem(rst);

}printf("\r\x1b[%d;%dH\x1b[%d;%dmplease select key:\x1b[m",9,0,33,1);rst=getchar();

}while(rst != 0x1b);return 0;

}

Documents

NAR-2200 Manual v100 UTM1 Appliance