NAMC-SDR RF module 8 Antenna Radio Head for MicroTCA User … · 2018. 10. 12. · This chapter describes the functionalities of the module's interfaces, front panel LEDs and boot

FRAUNHOFER-INSTITUTE FOR TELECOMMUNICATIONS, HEINRICH HERTZ INSTITUTE, HHI

WIRELESS COMMUNICATION AND NETWORKS

NAMC-SDR RF module 8 Antenna Radio Head for

MicroTCA User Guide

FHGUG903

NAMC-SDR User Guide www.hhi.fraunhofer.de FHGUG903 2017-11-27 2

Table of Content Table of Content ............................................................................................................... 2

Notice of Disclaimer .......................................................................................................... 5

Revision History ................................................................................................................ 5

1 Overview ....................................................................................................................... 6

1.1 The NAMC-SDR module .................................................................................................... 6

1.1.1 Block Diagram ................................................................................................................ 7

1.2 Purpose of this guide ........................................................................................................ 7

2 Specification ......................................................................................................................... 8

3 Interfaces and Control LEDs .......................................................................................... 10

3.1 Interfaces ........................................................................................................................ 10

3.1.1 AMC Connector ........................................................................................................ 11

3.1.2 Programmable Logic JTAG Connector ..................................................................... 11

3.1.3 MicroSD Card Slot .................................................................................................... 11

3.1.4 Micro-USB-B Connector ........................................................................................... 11

3.1.5 Ethernet Connector ................................................................................................. 11

3.1.6 QSFP Module Connector .......................................................................................... 12

3.1.7 Reference Clock Output ........................................................................................... 12

3.1.8 Reference Clock Input ( base band PLL) ................................................................... 12

3.1.9 RF Transmitter Connectors ...................................................................................... 12

3.1.10 RF Receiver Connectors ......................................................................................... 13

3.1.11 External TX LO Connector ...................................................................................... 13

3.1.12 External RX LO Connector ...................................................................................... 13

3.1.13 Trigger Output Connector ...................................................................................... 13

3.1.14 Alternative reference clock Input (Transceivers) ................................................... 13

3.2 Front Panel LEDs ............................................................................................................. 14

3. 3 Boot mode Switches ...................................................................................................... 15

4 Clock Generation and Referencing ................................................................................ 16

5 Getting Started ............................................................................................................ 17

http://www.hhi.fraunhofer.de/


5.1 Power-on NAMC-SDR module ........................................................................................ 17

5.2 Setup a connection ......................................................................................................... 18

5.3 Login credentials ............................................................................................................. 18

5.4 Network interfaces configuration .................................................................................. 19

6 Radio frequency frontend ............................................................................................ 20

6.1 Overview ......................................................................................................................... 20

6.2 Block diagram ................................................................................................................. 21

6.3 Functional description .................................................................................................... 21

6.4 external LOs usage .......................................................................................................... 22

7 Firmware ..................................................................................................................... 23

7.1 Firmware description ...................................................................................................... 23

7.2 File system structure ...................................................................................................... 24

7.3 Linux Industrial I/O Subsystem ....................................................................................... 25

7.3.0 List of installed IIO Devices ...................................................................................... 25

7.3.1 Libiio ......................................................................................................................... 25

7.3.2 IIO DMA interface .................................................................................................... 26

7.3.3 IIO tools .................................................................................................................... 26

7.3.3.1 iiod ..................................................................................................................... 26

7.3.3.2 iio_info ............................................................................................................... 27

7.3.3.3 iio_tx_stream .................................................................................................... 27

7.3.3.4 iio_readdev ........................................................................................................ 27

7.3.3.5 iio_mcs .............................................................................................................. 27

7.3.3.6 iio_reg ................................................................................................................ 27

7.3.3.7 iio_webserver .................................................................................................... 28

7.4 Debug Filesystem ............................................................................................................ 28

7.5 CPRI interface (optional) ................................................................................................. 28

7.6 Maintenance tools .......................................................................................................... 29

7.6.1 si5324 ....................................................................................................................... 29

7.6.2 cdcm6208 ................................................................................................................. 30

7.6.3 cpri (optional) ........................................................................................................... 30



7.6.4 ad9361 ..................................................................................................................... 30

7.6.5 gpio ........................................................................................................................... 31

7.7 Default firmware settings ............................................................................................... 32

7.8 Enabling external LOs ..................................................................................................... 33

7.9 NTP (Network Time Protocol) Client .............................................................................. 33

7.10 Auto execute ................................................................................................................. 34

7.11 Self-provided user applications .................................................................................... 34

7.12 Matlab Interface ........................................................................................................... 34

8 Firmware Generation and/or Modification ................................................................... 35

8.1 Vivado Design Suite ........................................................................................................ 35

8.1.1 Getting started ......................................................................................................... 35

8.1.2 Modifying design ...................................................................................................... 35

8.1.3 Built bit stream and tcl script ................................................................................... 36

8.2 Petalinux ......................................................................................................................... 36

8.2.1 Getting started ......................................................................................................... 36

8.2.2 Built project .............................................................................................................. 37

8.2.3 Generate firmware ................................................................................................... 37

Appendix A: References .................................................................................................. 38

Appendix B: Fraunhofer Resources .................................................................................. 39

Appendix E: Regulatory and Compliance Information ...................................................... 40

Declaration of Conformity ............................................................................................. 40

Directives ....................................................................................................................... 40

Standards ....................................................................................................................... 40



Notice of Disclaimer

FRAUNHOFER HEINRICH HERTZ INSTITUTE IS DISCLOSING THIS DOCUMENTATION

TO YOU ONLY FOR PERSONAL USE. YOU MAY NOT REPRODUCE, DISTRIBUTE,

REPUBLISH, DOWNLOAD DISPLAY, POST, OR TRANSMIT THIS DOCUMENTATION IN

ANY FORM OR BY ANY MEANS INCLUDING, BUT NOT LIMITED TO, ELECTRONIC,

MECHANICAL, PHOTOCOPYING, RECORDING, OR OTHERWISE, WITHOUT THE PRIOR

WRITTEN CONSENT OF FRAUNHOFER HEINRICH HERTZ INSTITUTE. © Copyright 2018, Fraunhofer Heinrich Hertz Institute. © Zynq, and other designated brands included herein are trademarks of Xilinx. All other trademarks are the property of their respective owners.

_____________________________________________________________________________________________________

Revision History

The following table shows the revision history. Date Version Revision

Author

27/11/2017 V1.0 Initial Release

K.Krüger

15/12/2017 V1.1 external LO usage NTP Client Linux file system information

K.Krüger

18/01/2018 V1.2 Maintenance tools Auto execute functionality Matlab Interface

K.Krüger, A.Forck



1 Overview

1.1 The NAMC-SDR module The NAMC-SDR module is an eight antenna radio head that provides a flexible software defined radio (SDR) platform for prototyping 5G network base stations and other massive multiple input, multiple output (MIMO) base station transceiver (BTS) systems. Consisting of a stacked digital interface card and a radio frequency front-end, the NAMC-SDR supports different communication standards with variable signal bandwidths, carrier frequencies and transmit power.

Digital interface card

Xilinx Zynq XC7Z045-2FFG900C AP SoC, consisting of an integrated processing system (PS) and programmable logic on a single die

The Zynq AP SoC uses a multi-stage boot process that supports both a non-secure and a secure boot

1 Gbyte 32-bit wide DDR3 SDRAM (8X 256 MB x 4 SDRAMs)

64Mbyte Quad SPI-Flash (2X 256 Mbit) for non-volatile storage

Clock synthesizer, clock jitter attenuator and clock distribution network

The board provides access to 12 GTX transceivers:

Eight of the GTX transceivers are wired to the MicroTCA backplane

Four of the GTX transceivers are wired to the QSFP Module connector (QSFP1)

4 x 10 Gbps optical lanes for CPRI and 10 GbE to the front panel via QSFP

(Accepts QSFP or SFP modules)

Marvell Alaska PHY provides 10/100/1000 Mb/s Ethernet communications

Silicon Labs USB-to-UART bridge device allows connection to host computer through

USB connector

Programmable logic JTAG connector

1X micro SD card slot available, memory extension up to 64 Gbyte, bootable

Radio frequency front-end

Up to 4x AD9361 RF agile transceiver devices each supporting two antennas Each transceiver can be fully synchronized up to 4 GHz

Integrated ADCs/DACs

Tunable carrier frequency between 70 MHz and 6 GHz

Up to 56 MHz analog bandwidth

Noise figure < 2.5 dB

Each receive (RX) subsystem includes independent automatic gain control (AGC), dc offset correction, quadrature correction, and digital filtering, thereby eliminating the need for these functions in the digital baseband.



1.1.1 Block Diagram

Figure 1-1 NAMC-SDR block diagram

CAUTION! The module can be damaged by electrostatic discharge (ESD). Follow ESD prevention

measures when handling the module.

1.2 Purpose of this guide This manual guides through the first steps to bring up the NAMC-SDR Module. The Module

will be delivered in QSPI Boot mode by default. The firmware is stored in the Quad-SPI flash

memory. The provided firmware includes a linux operating system to run the AD9361 drivers

and IIO interface (Getting Started).



2 Specification 2x2, 4x4 or 8x8 MIMO duplex operation

Wide carrier frequency range from 70 MHz up to 6 GHz

Different clock reference sources

Receive and transmit local oscillators referenced on recovered optical interface clock or external clock reference

Full synchronized radio frequency and baseband oscillators

FDD and TDD operation

Variable band pass RF filter

Supporting CPRI 4.1, OBSAI, 10 GbE

Maximal output power (RMS, CW) of 0 dBm at 2.6 GHz

External power amplifiers depending on carrier frequency

External duplex components such as SAW filters, diplexers and/or TDD switches

Configurable via optical control and management (C&M) channel, USB or web interface

Embedded Linux operating system

Power Levels

Maximum TX Output Power (1 MHz tone into 50 Ω load)

8 dBm @800MHz

7.5dBm @2.4GHz

6.5dbm @5.5GHz

RF Inputs (Peak Power), Absolute Maximum rating: 2.5 dBm

Received Signal Strength (RSSI)

Range 100 dB

Accuracy ±2 dB

RX Gain

Minimum 0dB

Maximum

74.5 dB @ 800 MHz

73.0 dB @ 2.3GHz

65.5 dB @ 5.5GHz



Isolation

RX1 to RX2, RX3 to RX4, RX5 to RX6, RX7 to RX8Isolation

70dB @ 800MHz

65dB @ 2.4GHz

52db @ 5.5GHz

TX1 to TX2, TX3 to TX4, TX5 to TX6, TX7 to TX8 Isolation

50dB @ 800MHz

50dB @ 2.4GHz

50db @ 5.5GHz

Frequency Stability

TRx8Mod in standalone mode uses onboard reference oscillator (Connor Winfield T602- 30.72M, temperature compensated crystal oscillator) frequency stability: +/- 0.28ppm @ 30.72MHz (i.e. +/- 672Hz @ 2.4GHz)

TRx8Mod in RRH mode (TRx8Mod connected to a baseband module or eNB over CPRI): frequency stability depends on baseband module/eNBs built in reference oscillators (reference clock will be recovered from CPRI connection)

Dimensions

Height 2.89 inch (73.5 mm) Length 6.67 inch (169.6 mm) Width 1.14 inch (29 mm) Environmental

Temperature

Operating: 0°C to +50°C Storage: –25°C to +60°C Humidity

10% to 90% non-condensing Operating Voltage

+12 VDC



3 Interfaces and Control LEDs

This chapter describes the functionalities of the module's interfaces, front panel LEDs and

boot mode switches.

3.1 Interfaces The module provides several connectors, which can be used to connect the module to the

outside world. Figure 3-1 shows the positions of these connectors.

Figure 3-1 NAMC-SDR rear side and front panel

callout Description Reference

1 AMC Backplane Connector J6 Backplane Connector 170 pin

3.1.1 AMC Connector

2 Programmable Logic JTAG Connector ribbon cable FPC connector 10 pin

3.1.2 Programmable Logic JTAG Connector

3 microSD card slot 3.1.3 microSD Card slot

4 10/100/1000 Mb/s Ethernet Connector RJ45

3.1.5 Ethernet Connector

5 Micro-USB-B Connector 3.1.4 Micro-USB-B Connector

6 QSFP Module Connector (QSFP1) 3.1.6 QSFP Module Connector

7 RF Transmitter 1-8 3.1.9 RF Transmitter Connectors

8 RF Receiver 1-8 3.1.10 RF Receiver Connectors

9 Reference Clock Output 3.1.7 Reference Clock Output

10 External Reference Clock Input for BB PLL 3.1.8 Reference Clock Input ( BB PLL)

11 External TX LO input 3.1.11 External TX LO Connector

12 External RX LO input 3.1.12 External RX LO Connector

13 Alternate Reference Clock Input for AD9361 Transceivers

3.1.14 Reference Clock Input (Transceivers)

14 Trigger Output 3.1.13 Trigger Output Connector

Table 3-1: NAMC-SDR connectors



3.1.1 AMC Connector [Figure 3-1, callout 1]

The module connects to the uTCA chassis through a 170 pole AMC plug connector (J6).

3.1.2 Programmable Logic JTAG Connector [Figure 3-1, callout 2]

JTAG connection to XC7Z045 AP SoC (U1) can established via the PL JTAG connector J1.

Connector J1 is located on the rear side of the module near U1. The PL JTAG connector is a

fpc connector therefore a special ribbon cable and adapter board provided by Fraunhofer

Heinrich Hertz Institute is needed to connect U1 to an external JTAG emulator.

3.1.3 MicroSD Card Slot [Figure 3-1, callout 3]

The module includes a secure digital input/output (SDIO) interface to provide user-logic

access to general-purpose nonvolatile micro SDIO memory cards. MicroSD cards up to 64GB

are supported. To boot from a microSD card, insert a card with a bootable image and set the

boot mode switches (see 3.3 Boot mode Switches) to microSD card position.

3.1.4 Micro-USB-B Connector [Figure 3-1, callout 5]

The module contains a Silicon Labs CP2103GM USB-to-UART bridge device, which allows a

connection to a host computer through the USB connector. The CP2103GM is powered by

the USB 5V provided by the host PC when the USB cable is plugged into the USB port on the

module. Silicon Labs provides royalty-free Virtual COM Port (VCP) drivers for the host

computer. These drivers permit the CP2103GM USB-to-UART bridge to appear as a COM

port to communications application software (for example, TeraTerm or PuTTy) that runs on

the host computer. The VCP device drivers must be installed on the host PC prior to

establishing communications with the module.

3.1.5 Ethernet Connector [Figure 3-1, callout 4]

The module uses a Marvell Alaska PHY device (88E1116R) for Ethernet communications at 10 Mb/s, 100 Mb/s, or 1,000 Mb/s. The module supports RGMII mode only. The PHY connection to a user-provided Ethernet cable is through a Halo HFJ11-1G01E RJ-45 connector with built-in magnetics.



3.1.6 QSFP Module Connector [Figure 3-1, callout 6]

The module contains a quad small form-factor pluggable (QSFP) connector and cage

assembly QSFP1 that accepts QSFP or SFP+ modules. This interface can be configured by the

firmware for CPRI, OBSAI, 1 GbE and 10 GbE.

3.1.7 Reference Clock Output [Figure 3-1, callout 9]

The module also provides a SSMC connector for a reference clock output. This clock is a

programmable clock from the onboard clock generator CDCM6208.

3.1.8 Reference Clock Input ( base band PLL) [Figure 3-1, callout 10]

The module provides a SSMC connector for an external reference clock source for the base

band PLL. This input connects to the onboard jitter attenuation chip Si5324 (see chapter 4).

User application can select the external reference input by program the SI5324 chip through

an I2C interface or by the si5324 maintenance tool (chapter 7.6.1). The input voltage should

not exceed 600mVpp.

3.1.9 RF Transmitter Connectors [Figure 3-1, callout 7]

The module provides SSMC connectors for the eight transmitter output channels. The

mapping of the transmitter channel connectors to the transceivers shown in table 3-2.

Transceiver NR. Name TX Channel

1 PHY0 TX1 / TX2

2 PHY1 TX3 / TX4

3 PHY2 TX5 / TX6

4 PHY3 TX7 / TX8 Table 3-2: transmitter output connectors mapping



3.1.10 RF Receiver Connectors [Figure 3-1, callout 8]

The module provides SSMC connectors for the eight receiver input channels. The mapping of

the receiver channel connectors to the transceivers shown in table 3-3.

Transceiver NR. Name RX Channel

1 PHY0 RX1 / RX2

2 PHY1 RX3 / RX4

3 PHY2 RX5 / RX6

4 PHY3 RX7 / RX8 Table 3-3: receiver input connectors mapping

3.1.11 External TX LO Connector [Figure 3-1, callout 11]

The module provides a SSMC connector for feeding in an external TX LO signal. The use of

the external TX LO input is optional and depends on the firmware version. See chapter 6.4

for more information.

3.1.12 External RX LO Connector [Figure 3-1, callout 12]

The module provides a SSMC connector (J22) for an External RX LO signal. The use of the

External RX LO is optional and depends on the provided firmware. See chapter 6.4 for more

information.

3.1.13 Trigger Output Connector [Figure 3-1, callout 14]

The module provides a SSMC connector (J20) which is connected to a programmable GPIO

port of the FPGA. The functionality of this port is defined by the firmware version.

3.1.14 Alternative reference clock Input (Transceivers) [Figure 3-1, callout 13]

The module provides a SSMC connector (J21) to feed in an external reference clock source

for the AD9361 transceivers. This input can be used when customer application requires

other reference clock specifications compared to the onboard reference clock from digital

interface card. The input can be activated by setting the Zynq's SoC gpio port 198 (see

chapter 7.6.5).



3.2 Front Panel LEDs

Figure 3-2 module front panel

Hot Swap LED [Figure 3-2, callout 16]

A Hot Swap Controller allows the board to be safely inserted and removed from a live

backplane. The Hot Swap LED, “H/S”, is blue and provides basic feedback to the user on the

Hot Swap state of the AMC.

Fault LED [Figure 3-2, callout 20]

Red color. Indicates a severe IPMB Controller fault.

Status LED [Figure 3-2, callout 17] Indicates onboard cdcm6208 base band PLL status (see chapter 4). Green: PLL is locked. Red: PLL unlocked.

User Programmable LEDs

[Figure 3-2, callout 19]

The functionality of the LEDs 1-4 is programmable and depends on the firmware version.

Ethernet PHY Status LEDs [Figure 3-2, callout 18]

The two Ethernet PHY status LEDs are located inside the RJ45 Ethernet jack J10. The on/off

state for each LED is software dependent and has no specific meaning at Ethernet PHY

power on. Refer to the Marvell 881116R Alaska Gigabit Ethernet transceiver data sheet for

details concerning the use of the Ethernet PHY status LEDs. They referred to in the data

sheet as LED0 and LED1. See the data sheet and other product information for the Marvell

881116R Alaska Gigabit Ethernet Transceiver.



3. 3 Boot mode Switches The module supports four different boot modes. At delivery state boot mode is set to QSPI boot mode. The module supports these configuration options: • boot from Quad-SPI flash memory (default) • boot from microSD card • boot from JTAG cable connector J1 (standard jtag mode) • boot from JTAG cable connector J1 (independent jtag mode)

Boot up from microSD Card or from JTAG cable connector is described in [FHG2]. The configuration option (Boot mode) is selected by setting SW1, SW2 and SW4 as shown in Table 3-4. SW1, SW2 and SW4 are indicated by callout 15 in Figure 3-3.

Figure 3-3 boot mode switches

Boot Mode SW1 SW4 SW2

JTAG mode 0 0 0

Independent JTAG mode 1 0 0

QSPI mode (1) 0 0 1

microSD card 0 1 1

Table3-4: Switches SW1, SW2 and SW4 Configuration Option Settings

Note1: Default switch setting



4 Clock Generation and Referencing

Figure 4-1 shows the digital interface card's base band clocks and references.

Figure 4-1: base band clocks and references

The Base Band PLL (CDCM6208) needs a stable reference signal to lock. There are two

reference sources available in the system. An onboard TXCO reference oscillator connected

to the SEC_REF input and the Silicon labs chip Si5324 connected to the PRI_REF input. The

SI5324 works primarily as a jitter attenuator but can also be used to switch reference inputs

between ext. ref input and internal cpri core reference clock (optional).

After power-up the onboard TXCO reference oscillator (30.72MHz) supplies the reference

clock. If the user applies a signal (10MHz) to the external reference connector [Figure 3-1,

callout 10] the firmware will automatically switch to this reference source. When a CPRI

connection (optional) over QSFP front panel connector is used, the system will automatically

switch to the recovered CPRI clock (recclk) from the XC7Z045 AP SoC. The expected

frequency at the external reference input is determined by the firmware (see 7.7 Default

firmware settings, default is 10MHz) the frequency of the recovered CPRI clock is 30.72MHz.

The BB PLL provides the following clock frequencies:

122,88MHz for the CPRI core

30.72MHz for the PL (PHY cores)

10 MHz for the external reference output [Figure 3-1, callout 9]

30.72MHz for the uTCA Backplane (AMC connector)

30.72MHz for the RF board

The firmware provides tools to control the CDCM6208 and SI5324 chips (see 7.6

Maintenance tools).



5 Getting Started

Required components to setup up the module:

MicroTCA chassis

desktop PC with free USB port or Ethernet port

micro USB cable or Ethernet cable

Installation of the module inside an uTCA chassis is required for normal operation. When the module is used inside an uTCA chassis (that is, plugged into an AMC slot), power is provided from the uTCA chassis to the module over the AMC Backplane connector. Note: If no uTCA chassis available, the module can also be powered through the 2 pin Power Connector J5. Fraunhofer Heinrich Hertz Institute provides an adapter cable for powering the module from a 12V external power supply.

5.1 Power-on NAMC-SDR module Power down the uTCA Chassis.

Adjust the boot mode switches [Figure 3-3] of the NAMC-SDR module to the desired mode.

Plug the module into a vacant slot of the MicroTCA chassis.

Switch on the MicroTCA chassis

Push the module's handle switch at the front panel of the module.



5.2 Setup a connection A Connection to the NAMC-SDR module can be established in two ways. 1. Connection via USB cable using the module's usb/uart bridge connector. 2. Connection via Ethernet cable connector (SSH). Connect to the NAMC-SDR module via serial interface (usb/uart bridge):

if not already done, install a device driver for cp2103 usb-uart-bridge on your desktop PC

connect the micro USB connector [Figure 3-1, callout 5] to the desktop PC via a micro USB cable and start a appropriate terminal program like TeraTerm or PuTTY

choose the following settings for the terminal program: port: corresponding serial port connected to cp2103 driver, e.g. COM3 or ttyUSB speed: 115200 bit/s, data bits: 8, parity: none, stop bits: 1, flow control: none.

Connect to the NAMC-SDR module via Ethernet interface (SSH):

connect the Ethernet connector (eth0) [Figure 3-1, callout 4] to the desktop PC via a Ethernet cable and start a appropriate terminal program like PuTTY. optional: the firmware supports a second Ethernet interface (eth1) connected to the MicroTCA backplane. The user can use this interface by connecting an Ethernet cable to the MCH Ethernet uplink port.

choose the following settings for the terminal program: connection type: SSH

IP address: see configuration for eth0 or eth1 [Configure the network interfaces] port: 22

If a connection is successfully established the login prompt will occur in the terminal program. login as:

5.3 Login credentials To login enter the following credentials: user name: root password: NAMC_SDR


https://www.silabs.com/products/mcu/Pages/USBtoUARTBridgeVCPDrivers.aspx


5.4 Network interfaces configuration

By default the module comes with two Ethernet interfaces: eth0 and eth1. The eth0 interface is connected to the RJ45 connector at the front panel whereas eth1 interface is connected to MicroTCA MCH via backplane connector. After a login to the linux system, the configuration status of the network interfaces can be displayed by entering

ifconfig -all

command. An example for eth0 interface is shown below:

Address 172.16.48.24 Net mask 255.255.0.0 Gateway 172.16.0.1

To change the default settings for eth0 and eth1 interfaces the configuration file '/mnt/interfaces' must be modified. An example of the file '/mnt/interfaces' with ip configuration settings for eth0 and eth1 is shown below: auto lo iface lo inet loopback # auto eth0 iface eth0 inet static address "10.64.4.253" netmask "255.255.255.0" gateway "10.64.4.1" hwaddress ether 00:12:E9:10:20:FD auto eth1 iface eth1 inet static address "172.16.48.253" netmask "255.255.0.0" gateway "172.16.0.1" hwaddress ether 00:12:E9:10:30:FD

After system reboot the Linux OS will automatically configure the network interfaces with the settings in the '/mnt/interfaces' file.



6 Radio frequency frontend

6.1 Overview The radio frequency front-end of the Module is based on four AD9361 transceivers from

Analog Devices [AD1]. Each transceiver has a specific name, as shown in Figure 6-1.

Figure 6-1 radio frequency front-end with front panel cables

The firmware controls the AD9361 transceivers through linux IIO device drivers [IIO

interface]. Each transceiver incorporates 2 transmitters and 2 receivers. Table 6-2 shows the

mapping between physical transceivers and device names in the linux OS.

Table 6-2: transceiver mapping

Transmitter outputs

Receiver Inputs

Transceiver name

Linux device name

Tx1, Tx2 Rx1, Rx2 PHY0 iio:device0






6.2 Block diagram Figure 6-3 shows the block diagram of the radio frequency front-end

Figure 6-3: radio frequency front-end block diagram

6.3 Functional description The radio frequency front-end card expands the digital interface card to a fully functional 8

Antenna radio head targeting Massive MIMO applications. For this aim the radio frequency

front-end card is equipped with four Analog Devices AD9361 rf agile transceivers. The

necessary baseband data processing and generation is performed by the digital interface

card. The transceivers must be supplied with a reference clock to generate the internal data

clocks, sample clocks and LO frequencies. By default, the reference clock for the AD9361

transceivers is provided by the reference clock source (CDCM6208) on the digital interface

card. For more flexibility, the user can also use an external RF reference clock input [Figure

3-1, callout 13] by switching the onboard MUX ICS854S01 chip. The ADCLK846 clock

distribution chip supplies all four transceivers with this reference clock.

For applications with fixed rf phase requirements the module offers also the opportunity to

use a common external LO signal as input for all AD9361 transceivers (see chapter 6.4). For

this option, the customer have to develop additional vhdl code and software.


https://www.idt.com/document/dst/ics854s01i-datasheet


6.4 external LOs usage With the delivered firmware image each AD9361 Transceiver uses its own internally

generated LO source to convert the baseband signals to the rf domain. For several

applications however (e.g. Beam forming) it would be necessary to have a common LO

source for all AD9361 Transceivers. For this purpose the NAMC-SDR module provides 2

external LO input connectors [ Figure3-1 , callout 11 and callout 12 ]. The TX LO connector

can be used to feed in a common LO signal for the transmit path of all 4 AD9361

Transceivers. For a common LO signal in the receive path the RX LO connector is designated.

Each external LO Input drives a separate fan-out buffer HMC987LP5E (see radio frequency

front-end block diagram) which distributes the external LO signal to the four AD9361

Transceivers.

When an external LO is used the input frequency must be twice as much the desired

transceiver output RF frequency. The range of the EXT LO signal is from 140 MHz to 8 GHz,

covering the RF tune frequency range of 70 MHz to 4 GHz. The input power must be in the

range of +3dBm up to +6dBm. In addition the external LO source must be referenced by the

10 MHz reference clock output of the module [Figure3-1 , callout 9]. Furthermore when

using the EXT LO, both inputs must be driven, even if the RX and TX frequencies are the

same. LO sources are either both internal or both external, a mixture is not allowed.

See chapter7.8 for more information on how to activate external LO inputs by software .



7 Firmware

The firmware for the module was developed with the following tools

Xilinx Vivado 2014.2 (development software for FPGAs and SoCs) [Xil1]

Petalinux 2014.4 (development software for implementation of Embedded Linux

Systems on SoC). Linux kernel version 3.17 [Xil2]

Xilinx SDK 2014.2 (development software for creating embedded applications on Xilinx's

microprocessors)[Xil3]

to get information about the current firmware version, login and enter:

cat /etc/fwversion

The following information will be shown:

name of the flashed firmware

related SVN version numbers:

bit file version, petalinux file version, firmware.tar.gz version

7.1 Firmware description The integrated Processing system on Xilinx SoC (xc7z045) runs an embedded Linux OS

(petalinux2014.4). The OS configures and controls the IP cores in the fpga and the devices in

the radio frequency front-end by means of linux device drivers [AD2]. The fpga design

contains the PHY interface block with four independent axi_ad9361 IP cores, a DMA

interface block for transferring data between the Linux OS and the PHY interface and a CPRI

interface for real-time data streaming [Figure 7-1] . The design is based on the FMCOMMS5

Design by Analog Devices [AD5].

Figure 7-1: block diagram SoC design



The linux system allows monitoring and adjustment of the AD9361 transceiver parameters

via command line, self-provided user applications or matlab scripts. Detailed instructions are

given on the Wiki page of Analog Devices [AD2].

7.2 File system structure The module's system memory consists of 1GByte DDR SDRAM and a 64Mbyte QSPI Flash

memory. An optional microSD card can be used to expand the non-volatile memory space to

a maximum of 64GByte.

The root file system of the Linux OS is located in a ram disk, which is generated during

system boot up. Therefore any changes made on the root file system at runtime will be lost

when the module is powered down because the ram disk is placed in DDR-SDRAM volatile

memory. The only exception from this rule is the /mnt folder which is mounted to the QSPI

non-volatile flash memory spare partition /dev/mtdblock3. While the onboard QSPI Flash

memory size is 64MByte in total the first 3 partitions (25.8Mbytes) are occupied by the

module's firmware. Thus the remaining size for the /dev/mtdblock3 partition mounted to

/mnt folder is 0x2760000 i.e. 41.2Mbytes.

Files in /mnt folder will be restored after power on. Any data which is supposed to be

permanent present on the module should be stored in the /mnt folder or on the optional

microSD card.

For more information on file system structure enter df command at command prompt.

Typical output of df command is shown below:

root@NAMC-SDR:~# df

Filesystem 1K-blocks Used Available Use% Mounted on

devtmpfs 64 0 64 0% /dev

tmpfs 516500 24 516476 0% /run

tmpfs 516500 40 516460 0% /var/volatile

/dev/mtdblock3 40320 9504 30816 24% /mnt

For information on QSPI flash memory partitions run cat /proc/mtd command:

root@NAMC-SDR:~# cat /proc/mtd

dev: size erasesize name

mtd0: 00e00000 00020000 "boot"

mtd1: 00020000 00020000 "bootenv"

mtd2: 00a80000 00020000 "kernel"

mtd3: 02760000 00020000 "spare"



7.3 Linux Industrial I/O Subsystem The Industrial I/O subsystem is intended to provide support for devices that in some sense

are analog to digital or digital to analog converters (ADCs, DACs). A typical device falling into

the IIO category would be connected via SPI or I2C. The firmware uses the iio subsystem to

access the AD9361 transceivers via iio device drivers. Access to devices controlled by the iio

subsystem is provided by the following linux system path:

/sys/bus/iio/devices/

Detailed information on the Industrial I/O interface can be found here: [AD8].

7.3.0 List of installed IIO Devices The Firmware creates several IIO subsystem devices at system startup. The following table

shows these IIO devices and their corresponding hardware devices.

IIO device hardware device Description Interface type

iio:device0 ad9361-phy0 AD9361 Transceiver 0 SPI, ADI Linux Driver




iio:device4 zynq_xadc Xilinx XADC Xilinx Linux Driver

iio:device5 xadc HHI XADC extension HHI Linux Driver

iio:device6 cf-ad9361-dds-core-lpc0 DAC IP CORE Transceiver 0 AXI, ADI Linux Driver




iio:device10 cf-ad9361-lpc0 ADC IP CORE Transceiver 0 AXI, ADI Linux Driver



iio:device13 cf-ad9361-lpc3 ADC IP CORE Transceiver 3 AXI, ADI Linux Driver Table7-3-0: List of installed IIO devices

7.3.1 Libiio Libiio is a library that has been developed by Analog Devices to ease the development of

software interfacing linux Industrial I/O devices. The library abstracts the low-level details of

the hardware, and provides a simple yet complete programming interface that can be used

for advanced projects. Details are described on the Libiio wiki page [AD3].



7.3.2 IIO DMA interface This interface instantiates a data connection between the Zynq processing system and the

AD9361 transceivers. Instead it is usually used to transmit/receive a limited amount of

subsequent IQ samples to/from the AD9361 transceivers. The maximum amount of

subsequent IQ samples is limited by the current sampling frequency and the linux DMA

Buffer size, which is 16MByte. Due to the firmware samples all eight antennas

simultaneously the module produces 32 Bytes per sample clock (8 antennas x 2 IQ samples x

2Bytes/sample). The maximum possible length of subsequent samples is given by the DMA

Buffer size divided by the amount of necessary Bytes per sampling clock (16MBytes/32Bytes

= 524288 samples).

e.g.: with a sampling rate of 30.72 MSPS the maximum achievable time of subsequent

samples is 17.066ms.

Note: This interface is not intended to be used as a continuous data streaming interface.

7.3.3 IIO tools The firmware comes with several software tools to access and control the iio devices in the

system. These tools are described in the following subchapters.

Tool Name Functionality

iiod Server interface to IIO devices

iio_info Info about all iio devices installed in the iio subsystem

iio_tx_stream Transmitter data streaming test program

iio_readdev Receiver data sampling test program

iio_mcs AD9361 multi chip synchronization

iio_reg Read and write function to all iio devices registers

iio_webserver Receiver diagnostic program over web interface Table7-3-3:List of IIO tools

7.3.3.1 iiod The IIO daemon server uses the Libiio library for establishing a network connection to the

module's IIO devices. It creates an iio context at the “local” backend (i.e. the NAMC-SDR

module) and shares it on the network to remote client applications. Possible remote client

applications are e.g. iio_readdev (see chapter 7.3.3.4) or Analog Devices IIO System Object

for Matlab (see chapter 7.12). The iiod server program must be launched on the module

before a remote application is started otherwise the connection establishment will fail.



7.3.3.2 iio_info This helper program returns information about the installed IIO devices (see chapter 7.3.0)

and their current attribute settings.

7.3.3.3 iio_tx_stream This program provides the opportunity to stream customer defined IQ samples to the

transmitters. The customer data stream is loaded into a DMA Buffer and will be cyclically

passed to the transmitters. The IQ data has to be formatted as binary data file. The

document “USER_GUIDE_IIOstreamer” [FHG3] describes how to generate and stream IQ

data to the module's transmitters. Further information how to transfer data to the

transceivers with Matlab is given in chapter 7.12

note: The amount of possible subsequent samples is limited (see 7.3.2 IIO DMA interface).

7.3.3.4 iio_readdev The inverse functionality compared with iio_tx_stream can be achieved with this program. It

puts the user in the position to read subsequent IQ samples from all receivers. The samples

of all receivers are continuously passed to the DMA Buffer which can be readout by the

program. The output of the program will be piped to the console or can be saved to a file.

The iio_device must be always 'cf-ad9361-lpc0'. For more information see Analog Devices

iio_readdev Wiki page.

note: The buffer size and the amount of samples is limited (see 7.3.2 IIO DMA interface).

7.3.3.5 iio_mcs A multi chip synchronization (MCS) sequence is automatically executed during system

startup. The MCS synchronizes all four AD9361 transceivers in the baseband domain. For

more information of MCS see the Analog Device Wiki page [AD7]. RF phase synchronization

is not supported by default, see chapter 6.4. The iio_mcs program must be executed

whenever a AD9361 transceiver parameter has been changed.

7.3.3.6 iio_reg This program provides read or write access to the SPI or I2C registers of the installed IIO

devices.

iio_reg <device> <register> [<value>]


https://wiki.analog.com/resources/tools-software/linux-software/libiio/iio_readdev

https://wiki.analog.com/resources/tools-software/linux-software/libiio/iio_readdev


7.3.3.7 iio_webserver Iio_webserver can be used for RX data diagnostic over Ethernet link. The program uses the

TCP port 9080. To connect a browser with the module the customer has to enter the

module's IP address followed by the port number e.g. 172.16.48.156:9080 .

7.4 Debug Filesystem The firmware implements the linux Debug file system to provide a low level direct register

access to several onboard hardware devices. The path for these settings is

/sys/kernel/debug/

7.5 CPRI interface (optional) The standard interface for data streaming is the Common Public Radio Interface (CPRI™).It

provides a connection between the module and a mobile radio base station. The firmware

implements a Xilinx CPRI IP core [Xil4] for this purpose. The core supports line rates from

614.4Mb/s up to 9830.4Mb/s and can transmit up to eight antenna streams simultaneously

(LTE20 TM3). The configuration of line rate, number of antenna streams and operation

mode depends on the firmware (see chapter 7.7). The CPRI interface is connected to the

QSFP connector at the front panel [Figure 3-1, callout 1]. An additional SFP+ module

(10Gbit/s) is needed for operating the cpri interface.



7.6 Maintenance tools The firmware comes with several control and maintenance tools to provide the user with status information of the module specific hardware devices and IP cores. The following table shows these tools and their corresponding hardware devices:

Tool Name Device

si5324 SI5324 jitter attenuator and reference clock switch

cdcm6208 CDCM6208 clock synthesizer

cpri CPRI IP core configuration

ad9361 AD9361 transceivers

gpio Zynq SoC general purpose IOs Table7-6: List of maintenance tools

The maintenance tools are based on shell scripts. They can be executed with the following syntax structure:

sh ~/[toolname] [options] To show the options of each tool type:

sh ~/[toolname] The maintenance tools are described in the following subchapters. CAUTION! changing register values with these tools can cause erroneous firmware behavior.

7.6.1 si5324 Provides low-level register access to the Silicon Labs jitter attenuator chip Si5324. Further options are e.g. a full register dump, getting internal pll status information and getting reference clock inputs settings. Options for device calibration and device reset are also available. syntax: si5324 [w r dump status default reset cal setclkin getclkin] [reg_addr] [value] examples:

sh ~/si5324 status returns information about internal pll status and reference clocks.

sh ~/si5324 w 0x03 0x21 write value 0x21 to register 3. Information about the register mapping of the device is given in the datasheet (Si5324).


https://www.silabs.com/documents/public/data-sheets/Si5324.pdf


7.6.2 cdcm6208 Provides low-level register access to the Texas Instrument low jitter clock generator CDCM6208. Further options are e.g. a full register dump, getting pll status information and frequency divider settings. syntax: cdcm6208 [w r d c div status ] [reg_addr divider] [value]

examples:

sh ~/cdcm6208 status returns information about pll status and reference clocks.

sh ~/cdcm6208 w 0x02 0x5A write value 0x5A to register 2.

Information about the register mapping is given in the datasheet (CDCM6208 ).

7.6.3 cpri (optional) Provides low-level register access to the optional Xilinx cpri IP core. Further options are e.g. a full register dump, setting linerate and core reset. syntax: cpri [write read dump reset linerate] [reg_addr rate] [value] examples:

sh ~/cpri dump returns IP core register dump.

sh ~/cpri write 0x02 0x00000041 write value 0x00000042 to register 2.

Information about the register mapping is given in the datasheet (Xilinx CPRI core ).

7.6.4 ad9361 Provides low-level register access to the ad9361 transceivers.

syntax:

ad9361 [w r] phy_addr reg_addr [value]

example:

sh ~/ad9361 r 0 0x02 returns value of phy0, register 2

Information about the register mapping is given by AD9361 Register Map Reference Manual

UG-671 (AD9361 Register Map).


http://www.ti.com/lit/pdf/SCAS931

https://forums.xilinx.com/xlnx/attachments/xlnx/ultrascale/5059/1/pg056-cpri_v87.pdf

https://www.google.de/url?sa=t&rct=j&q=&esrc=s&source=web&cd=2&cad=rja&uact=8&ved=0ahUKEwjMyon369nYAhVEzaQKHfjeBqcQFgg5MAE&url=http%3A%2F%2Fopencran.org%2Fdownload%2FAD9361_Register_Map_Reference_Manual_UG-671.pdf&usg=AOvVaw2qXtfBZqrFKgMdAf2F2_y2


7.6.5 gpio Sets directions and values of the Zynq SoC general purpose I/Os. 32 gpios are available for

user defined actions. The functionality of the gpios depends on the firmware version. Some

gpios are under Linux OS and/or device driver control and can't be changed by this tool.

Enter

cat /sys/kernel/debug/gpio

to get information about gpios which are already used by the system. The Linux OS maps the

gpios 0..31 to a virtual gpio range starting with the base address 192. For example the gpio

number 2 in the vhdl design will be mapped to gpio194 under Linux OS.

syntax:

gpio <nr> direction value

example:

sh ~/gpio 194 out 1 sets gpio number 194 (gpio 2 in vhdl design) as output with value 1.



7.7 Default firmware settings The following default configuration settings are made by the firmware at system start up:

configuration of the baseband clock synthesizer chip CDCM6208 reference clock input: onboard 30.72MHz TCXO reference clock output frequency: 10 MHz cpri reference clock: 122.88MHz PL system clk: 30.72MHz to get status information use the command sh cdcm6208 status

configuration of the jitter attenuation chip Si5324 by default onboard reference oscillator is selected external reference input is programmed to 10MHz to get status information use the command sh si5324 status

CPRI core Line rate 2.457 Gb/s

2 antenna streams (LTE 20 TM3) to get information use the command sh cpri status

Ethernet The firmware implements two 1Gb eth interfaces to get information use the command ifconfig

configuration of the AD9361 transceivers Sample rate: 30.72MSPS RF Bandwidth: 18 MHz Gain control mode: slow attack FDD mode 2rx_2tx mode PHY 0: rx_LO_frequency: 2.3 GHz, tx_LO_Frequency: 2.35GHz PHY 1: rx_LO_frequency: 2.4 GHz, tx_LO_Frequency: 2.45GHz PHY 2: rx_LO_frequency: 2.5 GHz, tx_LO_Frequency: 2.55GHz PHY 3: rx_LO_frequency: 2.6 GHz, tx_LO_Frequency: 2.65GHz



7.8 Enabling external LOs CAUTION! The general configuration of all four AD9361 PHYs (e.g. bandwidth, sample rate) must be

done before the herein described next steps are made.

For correct external LO operation the user must enable both fan-out buffers HMC987 in the

radio frequency front-end. For this purpose the software modules hhi_trx8mod_txbuf and

hhi_trx8mod_rxbuf must be loaded:

modprobe hhi_trx8mod_txbuf

modprobe hhi_trx8mod_rxbuf

In the next step the external LO functionality in the AD9361 iio driver must be enabled for rx and tx path by writing a '1' to the appropriate iio driver files. RX LO must be always enabled before TX LO:

echo 1 > /sys/bus/iio/devices/iio:device0/rx_external_lo_en echo 1 > /sys/bus/iio/devices/iio:device0/tx_external_lo_en echo 1 > /sys/bus/iio/devices/iio:device1/rx_external_lo_en echo 1 > /sys/bus/iio/devices/iio:device1/tx_external_lo_en echo 1 > /sys/bus/iio/devices/iio:device2/rx_external_lo_en echo 1 > /sys/bus/iio/devices/iio:device2/tx_external_lo_en echo 1 > /sys/bus/iio/devices/iio:device3/rx_external_lo_en echo 1 > /sys/bus/iio/devices/iio:device3/tx_external_lo_en

In the last step the baseband synchronization must be renewed by executing the iio_mcs program: iio_mcs note: these settings are irreversible at runtime. For deactivating the external LOs the module must be rebooted.

7.9 NTP (Network Time Protocol) Client The firmware supports the use of the network time protocol to set system's date and time.

The ntp client will be automatically executed at system startup if a 'ntp.conf' file is found in

the /mnt folder. After a successful update of the system's date and time, the ntp client

terminates himself automatically. The firmware will set the real-time clock chip to the new

date and time also. An example for a ntp.conf file is given below:



# block queries from outside restrict -4 default kod notrap nomodify nopeer noquery restrict 127.0.0.1 # enter ntp server ip addresses here, the system needs the IP address, DNS is not supported # ntp servers must be accessible from local subnet server 192.134.23.21 # examples for other ntp servers , # server 0.de.pool.ntp.org # server 1.de.pool.ntp.org # server 2.de.pool.ntp.org # server 3.de.pool.ntp.org

Since the firmware does not supports dns service the ntp server adress in ntp.conf file must

be given in ip address format. Note also that the ntp server must be reachable from the local

subnet in which the NAMC-SDR module resides.

7.10 Auto execute In some cases it could be necessary to start applications or user-defined shell scripts

automatically at system boot-up. For this purpose the firmware seeks for an auto execution

script in the /mnt folder when the linux system reaches runlevel 5. The filename of the auto

execution script must be 'autoexec'.

7.11 Self-provided user applications With the Xilinx SDK Tool the user can develop C application and test them directly on the module, see the documentation “TRx8Mod Application Development and Debugging Guide” [FHG4] http://www.wiki.xilinx.com/Create+Linux+Application

7.12 Matlab Interface The IIO System Object from Analog Devices provides an interface for exchanging data over

Ethernet between the NAMC-SDR module's AD9361 transceivers and Matlab. The Wiki page

[AD6] describes how to install the Libiio and the IIO System Object. All requirements which

are necessary to use the Matlab interface are listed. The document [FHG3] describes how to

generate and stream IQ data with Matlab.



8 Firmware Generation and/or Modification

This chapter describes how to install and work with the Vivado Design Suite 2014.2 and

Petalinux 2014.4 (development software for implementation of Embedded Linux Systems on

SoC).

8.1 Vivado Design Suite With this tool, the user can develop new designs for the SoC or modifying the delivered

design. Since the firmware was developed with the Vivado version 2014.2 the user has to

follow the installation instructions of the Xilinx UG937 [Xil5] for this version. The Xilinx

UG973 describes the requirements, the download, the installation and the license

management.

8.1.1 Getting started https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug940-vivado-

tutorial-embedded-design.pdf

8.1.2 Packaged Vivado design The FPGA design is provided to the user as zip file: NAMC_SDR_basic_design.zip .

The unpacked zip file includes the filesystem:

namc_sdr_design/

bd/

system_bd.tcl

system_wrapper.vhd

constrs/

toplevel.xdc

ip_repo/

library/

spi_codec/

srcs/

toplevel.vhd

NAMC_SDR_basic_design.tcl

bd : contains the scripted block design and the associated HDL wrapper file

constrs: contains the constraints file, toplevel.xdc

ip_repo: includes IP cores, which not provided by Xilinx

ip_repo/library: includes all used Analog Devices IP core files

srcs: contains the toplevel file, toplevel.vhd


https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug940-vivado-tutorial-embedded-design.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug940-vivado-tutorial-embedded-design.pdf


To generate and modify the provided FPGA design the user has to start the Vivado Design Suite 2014.2 and run the Tcl Script in the Tcl console: source {path_to_design_folder /namc_sdr_design/NAMC_SDR_basic_design.tcl}

Vivado generates the project NAMC_SDR_basic_design.xpr in the correspondent folder:

namc_sdr_design/

NAMC_SDR_basic_design /

NAMC_SDR_basic_design.cache

NAMC_SDR_basic_design.srcs

NAMC_SDR_basic_design.xpr

Before the user modify the design, the user has to validate the block design and to run

Synthesis, Implementation and Generate Bitstream to prove the error free function of the

design. NAMC_SDR_basic_design.run is generated.

Now the user can modify the design. The stored design can be opened in Vivado by clicking

the ‘Open Project ‘ icon or the Tcl command:

open_project {path_to /namc_sdr_design/ NAMC_SDR_basic_design/NAMC_SDR_basic_design.xpr }

8.1.3 Built bit stream and tcl script to be cont'd

8.2 Petalinux This tool was used to develop the embedded Linux system. The used version is 2014.4 . The

petalinux tool has to be installed on a Linux workstation. The Xilinx UG1144 [Xil2] mentions

all requirements and guides through the installation.

8.2.1 Getting started to be cont'd



8.2.2 Built project A board support package (bsp) is provided to the user. The bsp includes the hw-discription

generated by the NAMC_SDR_basic_design (packaged Vivado design).

8.2.3 Generate firmware to be cont'd



Appendix A: References

[AD1] AD9361 RF Agile Transceiver

[AD2] AD9361 Linux device driver

[AD3] Libiio

[AD4] IIO Oscilloscope

[AD5] AD9361 HDL Reference Designs

[AD6] IIO System Object for Matlab

[AD7] AD9361 multi chip sync

[AD8] Linux Industrial I/O Subsystem

[Xil1] Xilinx Vivado Design Suite

[Xil2]Xilinx Petalinux Tools Documentation

[Xil3] Xilinx Software Development Kit

[Xil4] Xilinx CPRI LogiCORE IP

[Xil5] Xilinx ug973-vivado-release-notes-install-license

[FHG1] FHGUG901V1.0

[FHG2] FHGUG810V1.1

[FHG3] USER_GUIDE_IIOstreamer

[FHG4] FHGUG803V1.2

[FHG5] FHGUG806V1.0-1


http://www.analog.com/en/products/rf-microwave/integrated-transceivers-transmitters-receivers/wideband-transceivers-ic/ad9361.html

https://wiki.analog.com/resources/tools-software/linux-drivers/iio-transceiver/ad9361

https://wiki.analog.com/resources/tools-software/linux-software/libiio

https://wiki.analog.com/resources/tools-software/linux-software/iio_oscilloscope

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl

https://wiki.analog.com/resources/tools-software/linux-software/libiio/clients/matlab_simulink

https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms5-ebz/multi-chip-sync

https://wiki.analog.com/software/linux/docs/iio/iio

https://www.xilinx.com/products/design-tools/vivado.html

https://www.xilinx.com/support/documentation/sw_manuals/petalinux2014_4/ug1144-petalinux-tools-reference-guide.pdf

https://www.xilinx.com/products/design-tools/embedded-software/sdk.html

https://www.xilinx.com/support/documentation/ip_documentation/cpri/v8_2/pb012-cpri.pdf

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2014_2/ug973-vivado-release-notes-install-license.pdf


Appendix B: Fraunhofer Resources

For support resources such as Manuals, Schematics, Documentation and Downloads see the Fraunhofer Heinrich Hertz Institute website at:

http://www.hhi.fraunhofer.de/fields-of-competence/wireless-communications-and-

networks/research-areas/next-generation-wireless-systems-and-architectures/sdr-

radio-frontend.html

Contact:

Dipl. Ing. Andreas Forck

Wireless Communication and Networks

[email protected]

Tel +49 30 31002-658

Mobile +49 162 2323430

Fraunhofer Heinrich Hertz Institute

Einsteinufer 37, 10587 Berlin, Germany

www.hhi.fraunhofer.de


http://www.hhi.fraunhofer.de/fields-of-competence/wireless-communications-and-networks/research-areas/next-generation-wireless-systems-and-architectures/sdr-radio-frontend.html



mailto:[email protected]



Appendix E: Regulatory and Compliance

Information

This product is designed and tested to conform to the European Union directives and standards described in this section.

Declaration of Conformity To view the Declaration of Conformity online, please visit:

Directives 2006/95/EC, Low Voltage Directive (LVD)

2004/108/EC, Electromagnetic Compatibility (EMC) Directive

Standards

EN standards are maintained by the European Committee for Electro technical Standardization (CENELEC). IEC standards are maintained by the International Electro technical Commission (IEC).

Electromagnetic Compatibility

EN 55022:2010, Information Technology Equipment Radio Disturbance Characteristics

– Limits and Methods of Measurement

EN 55024:2010, Information Technology Equipment Immunity Characteristics – Limits

and Methods of Measurement

This is a Class A product. In a domestic environment, this product can cause radio interference, in which case the user might be required to take adequate measures.

Safety IEC 60950-1:2005, Information technology equipment – Safety, Part 1: General

requirements



EN 60950-1:2006, Information technology equipment – Safety, Part 1: General

requirements

Markings This product complies with Directive 2002/96/EC on waste electrical and electronic equipment (WEEE). The affixed product label indicates that the user must not discard this electrical or electronic product in domestic household waste.

This product complies with Directive 2002/95/EC on the restriction of hazardous substances (RoHS) in electrical and electronic equipment.

This product complies with CE Directives 2006/95/EC, Low Voltage Directive (LVD) and

2004/108/EC, Electromagnetic Compatibility (EMC) Directive.


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