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www.vedic-vlsi.com
IEEE Titles and Research & Development Projects for students of
M.Tech in VLSI Design M.Tech in Digital Electronics and Communication Systems M.Tech in Digital Systems and Computer Electronics
Network Security & Cryptographic Sciences
20121) Modification of DiffieHellman Key Exchange Algorithm for Zero Knowledge Proof 2) A Novel Architecture for VLSI Implementation of RSA Cryptosystem 3) An Implementation of AES Algorithm Based on FPGA 4) A Hybrid Reconfigurable Cryptographic Processor with RSA and SEA
20115) FPGA implementation of AES algorithm 6) Design of new security algorithm: Using hybrid Cryptography architecture
7) Construction
of
Optimum
Composite
Field
Architecture
for
Compact High-Throughput AES S-Boxes.
20108) Using
a
Pipelined
S-Box
in
Compact
AES
Hardware
Implementations9) A Hybrid Encryption Algorithm Based on DES and RSA in Bluetooth
Communication 10) 11) 12) 13) 14) FPGA implementation of SHA-224/256 algorithm oriented An Improved RC4 Stream Cipher Design of SHA-1 Algorithm based on FPGA Enhancing RC4 algorithm for WLAN WEP protocol An RC4-based hash function for ultra-low power devices Digital Signature
200915) A Design and Implementation of High-Speed 3DES Algorithm
System
200816) 17) 18) FPGA Implementation(s) of a Scalable Encryption Algorithm Effective Uses of FPGAs for Brute-Force Attack on RC4 Ciphers Cost-Efficient SHA Hardware Accelerators
Design for Testability201219) Efficient built-in self-repair strategy for embedded SRAM with
selectable redundancy
20)
BIST using Cellular Automata as test pattern generator and
response compaction21) ALU based address generation for RAMs
201122) 23) 24) Configurable architecture for memory BIST Optimizing memory BIST Address Generator implementations A Novel Access Scheme for Online Test in RFID Memories
201025) Modeling and Simulation of Multi-operation Microcode-Based Built-
In Self Test for Memory Fault Detection and Repair 26) 27) New Microcode's Generation Technique for Programmable Built-in Self-Detection/Correction Architecture for Motion Memory Built-In Self Test Estimation Computing Array
200928) Power optimization of linear feedback shift Register (LFSR) for
low power BIST
200829) An Accumulator-Based Compaction Scheme for Online BIST of
RAMs
Digital Signal Processing2012
30) 31)
A High Speed FIR Filter Architecture Based On Novel Higher Study On The FPGA Implementation Algorithm Of Effective FIR
Radix Algorithm. Filter Based On Remainder Theorem.32) Area-Efficient Parallel FIR Digital Filter Structures for Symmetric
Convolutions Based on Fast FIR Algorithm
201133) Design and implementation of low power digital FIR filter high pass filter
based on low power multipliers and adders on Xilinx FPGA34) VLSI implementation of nonlinear variable cutoff
algorithm 35) Distributed Arithmetic for FIR Filter Implementation on FPGA
201036) New Reconfigurable Architectures for Implementing FIR Filters with
Low Complexity 37) 38) New Approach to Look-Up- Table Design and Memory- Based Novel input coding technique for High precision LUT based Realization of FIR Digital Filter Multiplication for DSP Applications
200939) High speed parallel architecture for cyclic convolution based
on FNT
200840) A Reusable Distributed Arithmetic Architecture for FIR Filtering
Bus Protocols201241) 42) VHDL Implementation of UART with Status Register. Optimal Implementation OF UART-SPI Interface In SOC.
201143) 44) 45) 46) 47) 48) Data Transactions on System-on-Chip Bus Using AXI4 Protocol. Design and Implementation of High Performance AHB
Reconfigurable Arbiter for On chip Bus Architecture Design and Implementation of APB Bridge based on AMBA 4.0. Design and Simulation of UART Serial Communication Module Building an AMBA AHB compliant Memory Controller FPGA Implementation of RS232 to Universal
Based on VHDL.
Serial Bus converter.
200749) Implementation of a Multi-channel UART Controller Based on FIFO
Technique and FPGA
Digital Electronics201250) High speed signed multiplier for Digital Signal Processing
applications
51) 52) 53)
Design and Implementation of Two Variable Multiplier Using Design and Implementation of a High Performance Multiplier High Speed Modified Booth Encoder Multiplier for Signed and
KCM and Vedic Mathematics using HDL Unsigned Numbers54) On Modulo 2^n+1 Adder Design
55)
Low Power and Area Efficient Carry Select Adder
201156) 57) 58) Disposition (reduction) of (negative) partial product for Radix 4 Design of low power and high speed configurable booth Design of Low Power Column Bypass Multiplier using FPGA
Booth's Algorithm multiplier
201059) 60) 61) 62) Fixed-width CSD multipliers with minimum mean square error Analysis of results obtained with a new proposed low area low A High Bit Rate Serial-Serial Multiplier With On-the-Fly
power high speed fixed point adder Accumulation by Asynchronous Counters A New VLSI Architecture of Parallel MultiplierAccumulator Based on Radix-2 Modified Booth Algorithm
2009
63)
An
Optimized
Design
for
Serial-Parallel
Finite
Field
Multiplication over GF (2m) Based on All-One Polynomials
200864) 65) A Novel carry-look-ahead approach to a unified BCD and Arithmetic Unit for Finite Field GF (2^ {m})
Binary adder/Subtractor
200366) Minimization of Switching Activities of Partial Products for Multipliers
Designing Low-Power
General Purpose Processors201267) CIARP: Crypto Instruction-Aware RISC Processor
201168) 69) 70) 16-Bit RISC Processor Design for Convolution Application RISC-based architecture for computer hardware introduction A Novel Low Power and High Speed Wallace Tree Multiplier for
RISC Processor
201071) Architecture for Faster RAM Controller Design with Inbuilt
Memory
72) True
Random
Number
Generation
in
Block
Memories
of
Reconfigurable Devices 73) 74) An Efficient Non-Blocking Data Cache for Soft Processors AXI Compliant DDR3 Controller
200975) DDR3 Base Look up Circuit for High Performance Network
processing
200776) An Interrupt Controller for FPGA based Microprocessors
Digital Communications201277) FPGA Implementation of Encoder for (15, k) Binary BCH Code Using
VHDL and Performance Comparison for Multiple Error Correction Control. 78) 79) 80) A Novel Approach for Parallel CRC generation for high speed Memory Efficient Column-layered Decoder Design for NonUnified Architecture for Reed-Solomon Decoder Combined With application. binary LDPC Codes. Burst-Error Correction.
201181) 82) A Reduced-Complexity Architecture for LDPC for Layered
Decoding Reduced-Complexity Decoder Architecture Non-Binary LDPC Codes
201083) A Pipelined CRC Calculation Using Lookup Tables 84) Retimed two-step CRC computation on FPGA
85) 86) 87)
RS encoder design based on FPGA Design and Implementation of Reed-Solomon Encoder in An Energy Efficient Layered Decoding Architecture for LDPC
CMMB System Decoder
200988) 89) High-Throughput Layered LDPC Decoding Architecture Multi-Gb/s LDPC Code Design and Implementation
200890) 91) 92) An FPGA Implementation of 30Gbps Security Module for GPON A High-Speed Viterbi Decoder GSM-Based Remote Sensing and Control System Using FPGA
Systems
200793) 94) Applying CDMA Technique to Network-on-Chip VLSI Architecture for Layered Decoding for irregular LDPC
codes
200695) High Speed CRC implementation using Pipelining, Unfolding
and Retiming
Digital Image Processing201196) A Novel Design of CAVLC Decoder With Low Power and High
Throughput Considerations
2010
97) 98)
Forward Computations for Context-Adaptive Variable-Length High speed CAVLC encoder suitable for field programmable
Coding Design platforms
200999) An Efficient Hardware Architecture for Multimedia Encryption
and Authentication using the Discrete Wavelet Transform
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