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PowerFLAT 5x6
AM15540v2
5678
1 2 3 4
Top View
D(5, 6, 7, 8)
G(4)
S(1, 2, 3)
FeaturesOrder code VDS RDS(on) max. ID PTOT
STL110N10F7 100 V 6 mΩ 107 A 136 W
• Among the lowest RDS(on) on the market• Excellent FoM (figure of merit)• Low Crss/Ciss ratio for EMI immunity• High avalanche ruggedness
Applications• Switching applications
DescriptionThis N-channel Power MOSFET utilizes STripFET F7 technology with an enhancedtrench gate structure that results in very low on-state resistance, while also reducinginternal capacitance and gate charge for faster and more efficient switching.
Product status link
STL110N10F7
Product summary
Order code STL110N10F7
Marking 110N10F7
Package PowerFLAT 5x6
Packing Tape and reel
N-channel 100 V, 5 mΩ typ., 107 A, STripFET F7 Power MOSFET in a PowerFLAT 5x6 package
STL110N10F7
DS9392 - Rev 6 - March 2020For further information contact your local STMicroelectronics sales office.
www.st.com
1 Electrical ratings
Table 1. Absolute maximum ratings
Symbol Parameter Value Unit
VDS Drain-source voltage 100 V
VGS Gate-source voltage ±20 V
ID(1)Drain current (continuous) at TC = 25 °C 107 A
Drain current (continuous) at TC = 100 °C 75 A
IDM(1)(2) Drain current (pulsed) 428 A
ID(3)Drain current (continuous) at TC = 25 °C 21 A
Drain current (continuous) at TC=100 °C 14 A
IDM(2)(3) Drain current (pulsed) 84 A
PTOT(1) Total power dissipation at TC = 25 °C 136 W
PTOT(3) Total power dissipation at Tpcb = 25 °C 4.8 W
EAS(4) Single pulse avalanche energy 490 mJ
TJ Operating junction temperature range-55 to 175 °C
Tstg Storage temperature range
1. This value is rated according to Rthj-c.
2. Pulse width limited by safe operating area.3. This value is rated according to Rthj-pcb.
4. Starting TJ = 25 °C, ID = 18 A, VDD = 50 V.
Table 2. Thermal resistance
Symbol Parameter Value Unit
Rthj-case Thermal resistance junction-case 1.1 °C/W
Rthj-pcb(1) Thermal resistance junction-pcb 31.3 °C/W
1. When mounted on an FR-4 board of 1 inch², 2oz Cu, t < 10 s.
STL110N10F7Electrical ratings
DS9392 - Rev 6 page 2/14
2 Electrical characteristics
(TC = 25 °C unless otherwise specified)
Table 3. On/off states
Symbol Parameter Test conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source breakdown voltage VGS = 0 V, ID = 250 µA 100 V
IDSS Zero gate voltage drain currentVGS = 0 V, VDS = 100 V 1
µAVGS = 0 V, VDS = 100 V, TC = 125 °C(1) 10
IGSS Gate body leakage current VDS = 0, VGS = 20 V 100 nA
VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 2.5 4.5 V
RDS(on) Static drain-source on‑resistance VGS = 10 V, ID= 10 A 5 6 mΩ
1. Defined by design, not subject to production test.
Table 4. Dynamic
Symbol Parameter Test conditions Min. Typ. Max. Unit
Ciss Input capacitance
VDS = 50 V, f = 1 MHz, VGS = 0 V
- 5117 -
pFCoss Output capacitance - 992 -
Crss Reverse transfer capacitance - 39 -
Qg Total gate charge VDD = 50 V, ID = 21 A, VGS = 0 to 10 V
(see Figure 13. Test circuit for gatecharge behavior)
- 72 -
nCQgs Gate-source charge - 30 -
Qgd Gate-drain charge - 17 -
Table 5. Switching times
Symbol Parameter Test conditions Min. Typ. Max. Unit
td(on) Turn-on delay time VDD = 50 V, ID = 10 A,
RG = 4.7 Ω, VGS = 10 V
(see Figure 12. Test circuit for resistiveload switching times andFigure 17. Switching time waveform)
- 25 - ns
tr Rise time - 36 - ns
td(off) Turn-off delay time - 52 - ns
tf Fall time - 21 - ns
Table 6. Source-drain diode
Symbol Parameter Test conditions Min. Typ. Max. Unit
VSD(1) Forward on voltage ISD = 21 A, VGS = 0 V - 1.2 V
trr Reverse recovery time ISD = 21 A, di/dt = 100 A/µs,
VDD = 80 V, TJ = 150 °C
(see Figure 14. Test circuit for inductiveload switching and diode recovery times)
- 77 ns
Qrr Reverse recovery charge - 150 nC
IRRM Reverse recovery current - 4.3 A
1. Pulsed: pulse duration = 300 µs, duty cycle 1.5%.
STL110N10F7Electrical characteristics
DS9392 - Rev 6 page 3/14
2.1 Electrical characteristics (curves)
Figure 1. Safe operating area
ID
10
1
0.1 1 VDS(V) 10
(A)
Operat
ion in
this
area i
s
Limite
d by m
ax R
DS(on)
100ms 1s 0.1
Tj=175°C Tpcb=25°C Single pulse
10ms
AM16083v1
Figure 2. Thermal impedance
Single pulse
δ=0.5
0.05
0.02
0.01
0.1
0.2
K
tp(s) 10 -4
10 -2
10 -1
10 -3
10 -3 10 -2 10 -1 10
Zth = K Rthj-pcb
0 10 1
AM16096v1
Figure 3. Output characteristics
ID
80
40
20
0 2 VDS(V) 4
(A)
6 4V
7V
60
5V
6V
8
100
120
140
160
0
AM16084v1
VGS = 8, 9, 10 V
Figure 4. Transfer characteristics
ID
60
40
20
0 0 4 VGS(V) 8
(A)
2 6
10
30
50
70 VDS=2V
AM16085v1
Figure 5. Gate charge vs gate-source voltage
GADG020320200919QVG
12
10
8
6
4
2
00 10 20 30 40 50 60 70 80 90 Qg (nC)
ID = 21 AVDD = 50 V
VDS(V)
Figure 6. Static drain-source on-resistance
RDS(on)
4.98
4.96
4.94 2 6 ID(A)
(mΩ)
4 8
5.00
VGS=10V
10 12
5.02
5.04
5.06
14 16 18 20
AM16087v1
STL110N10F7Electrical characteristics (curves)
DS9392 - Rev 6 page 4/14
Figure 7. Capacitance variations
C
3000
2000
1000
0 0 20 VDS(V)
(pF)
10 30
Ciss
Coss Crss
40 50 60 70 80
4000
5000
6000
AM16088v1
Figure 8. Normalized gate threshold voltage vstemperature
VGS(th)
0.7
0.6
0.5
0.4 -75 -25 TJ(°C)
(norm)
-50
0.8
50 0 25 75
ID=250µA
100 125 150
0.9
1
1.1
1.2
AM16089v1
Figure 9. Normalized on-resistance vs temperature
RDS(on)
1.8
1.2
0.8
0.4 TJ(°C)
(norm)
0.6
1
1.4
1.6
2
-75 -25 -50 50 0 25 75 100 125 150
ID=10 A VGS=10 V
AM16090v1
Figure 10. Source-drain diode forward characteristics
VSD
2 6 ISD(A)
(V)
4 12 8 10 0.4
0.5
0.6
0.7
TJ=-55°C
TJ=175°C
TJ=25°C
0.8
0.9
14 16 18 20
AM16092v1
Figure 11. Normalized V(BR)DSS vs temperature
V(BR)DSS
-50 0 TJ(°C)
(norm)
-25 75 25 50 100 0.94
0.96
0.98
1
1.02
1.04ID=1mA
AM16091v1
STL110N10F7Electrical characteristics (curves)
DS9392 - Rev 6 page 5/14
3 Test circuits
Figure 12. Test circuit for resistive load switching times
AM01468v1
VD
RG
RL
D.U.T.
2200μF VDD
3.3μF+
pulse width
VGS
Figure 13. Test circuit for gate charge behavior
AM01469v1
47 kΩ1 kΩ
47 kΩ
2.7 kΩ
1 kΩ
12 V
IG= CONST100 Ω
100 nF
D.U.T.
+pulse width
VGS
2200μF
VG
VDD
Figure 14. Test circuit for inductive load switching anddiode recovery times
AM01470v1
AD
D.U.T.S
B
G
25 Ω
A A
B B
RG
GD
S
100 µH
µF3.3 1000
µF VDD
D.U.T.
+
_
+
fastdiode
Figure 15. Unclamped inductive load test circuit
AM01471v1
VD
ID
D.U.T.
L
VDD+
pulse width
Vi
3.3µF
2200µF
Figure 16. Unclamped inductive waveform
AM01472v1
V(BR)DSS
VDDVDD
VD
IDM
ID
Figure 17. Switching time waveform
AM01473v1
0
VGS 90%
VDS
90%
10%
90%
10%
10%
ton
td(on) tr
0
toff
td(off) tf
STL110N10F7Test circuits
DS9392 - Rev 6 page 6/14
4 Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages,depending on their level of environmental compliance. ECOPACK specifications, grade definitions and productstatus are available at: www.st.com. ECOPACK is an ST trademark.
4.1 PowerFLAT 5x6 type C package information
Figure 18. PowerFLAT 5x6 type C package outline
Bottom view
Side view
Top view
8231817_typeC_Rev20
STL110N10F7Package information
DS9392 - Rev 6 page 7/14
Table 7. PowerFLAT 5x6 type C package mechanical data
Dim.mm
Min. Typ. Max.
A 0.80 1.00
A1 0.02 0.05
A2 0.25
b 0.30 0.50
C 5.80 6.00 6.20
D 5.00 5.20 5.40
D2 4.15 4.45
D3 4.05 4.20 4.35
D4 4.80 5.00 5.20
D5 0.25 0.40 0.55
D6 0.15 0.30 0.45
e 1.27
E 5.95 6.15 6.35
E2 3.50 3.70
E3 2.35 2.55
E4 0.40 0.60
E5 0.08 0.28
E6 0.20 0.325 0.45
E7 0.75 0.90 1.05
K 1.05 1.35
L 0.725 1.025
L1 0.05 0.15 0.25
θ 0° 12°
STL110N10F7PowerFLAT 5x6 type C package information
DS9392 - Rev 6 page 8/14
Figure 19. PowerFLAT 5x6 recommended footprint (dimensions are in mm)
8231817_FOOTPRINT_simp_Rev_20
STL110N10F7PowerFLAT 5x6 type C package information
DS9392 - Rev 6 page 9/14
4.2 PowerFLAT 5x6 packing information
Figure 20. PowerFLAT 5x6 tape (dimensions are in mm)
(I) Measured from centreline of sprocket hole to centreline of pocket.
(II) Cumulative tolerance of 10 sprocket holes is ±0.20.
(III) Measured from centreline of sprocket hole to centreline of pocket
Base and bulk quantity 3000 pcsAll dimensions are in millimeters
8234350_Tape_rev_C
Figure 21. PowerFLAT 5x6 package orientation in carrier tape
Pin 1 identification
STL110N10F7PowerFLAT 5x6 packing information
DS9392 - Rev 6 page 10/14
Figure 22. PowerFLAT 5x6 reel
STL110N10F7PowerFLAT 5x6 packing information
DS9392 - Rev 6 page 11/14
Revision history
Table 8. Document revision history
Date Revision Changes
03-Dec-2012 1 First release.
12-Dec-2013 2
Modified: PTOT value and Figure 1 in cover page
Modified: ID, IDM and PTOT values in Table 2
Added: EAS value in Table 2
Modified: all values in Table 3
Modified: IDSS, IGSS and ID for RDS(on)
Updated: the entire typical values in Table 5, 6 and 7
Updated: Figure 13, 14, 15 and 16
Minor text changes
25-Mar-2014 3
Updated title and features on cover page.
Added PTOT value at TC = 25 °C in Table 2: Absolute maximum ratings.
Updated Section 4: Package mechanical data.
20-Aug-2014 4
Modified: title, features and description
Modified: Figure 2 and 3
Updated: Section 4: Package mechanical data.
Minor text changes
17-Sep-2018 5
Removed maturity status indication.
Updated title and description on cover page.
Updated Table 1. Absolute maximum ratings and Table 6. Source-drain diode.
Updated Section 4.1 PowerFLAT™ 5x6 type C package information.
Minor text changes
03-Mar-2020 6Updated Figure 5. Gate charge vs gate-source voltage.
Minor text changes.
STL110N10F7
DS9392 - Rev 6 page 12/14
Contents
1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4.1 PowerFLAT 5x6 type C package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.2 PowerFLAT 5x6 packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
STL110N10F7Contents
DS9392 - Rev 6 page 13/14
IMPORTANT NOTICE – PLEASE READ CAREFULLY
STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to STproducts and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. STproducts are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement.
Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design ofPurchasers’ products.
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Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2020 STMicroelectronics – All rights reserved
STL110N10F7
DS9392 - Rev 6 page 14/14