Muon System Electronics Upgrade Meeting Summary

Alessandro Cardini / INFN Cagliari

Roma, October 10, 2014 A. Cardini / INFN Cagliari 2

nSYNC Architecture

TDC + Histogram builder: • 4 bit TDC (1.5 ns resolution @ 40 MHz)• 16 bins of 224 entries each. The counts stop when any of

the bins saturates. Dead time free in hit capture.

Muon Trigger TELL40 Interface: • Sends synchronized hits every machine cycle (40 MHz).• Prog. buffer depth to guarantee the synchronization

between different nSYNC sending data through the same GBT

TDC ZS: • Zero Suppression of TDC’s data not related to hit events.

TDC TELL40 Interface: • Sends synchronized ZS TDC data every machine cycle (40

MHz).• Prog. buffer depth to guarantee the synchronization

between different nSYNC sending data through the same GBT

I2C Interface: • Configure through the ECS.• Triple-voted configuration

Roma - 08/10/14S. Cadeddu - INFN Cagliari 3

S. Cadeddu - INFN Cagliari 4

nSYNC: alcuni punti (quasi) fermi

• Tecnologia:– Al momento UMC 130 nm– In attesa di notizie/decisioni dal CERN sulla TSMC 130 nm

• 48 canali– 1 GBT per nSYNC => 4 link indipendenti per nODE– 1 GBT_TFC per nODE– 1 GBT_SCA per nODE

• Clock– 40 MHz di sistema (da dove?)– 80/160/320 MHz per interfacce GBT (quale frequenza?; Il clock

generato dal GBT stesso?)

• Interfaccia ECS– I2C o SPI (?)

Roma - 08/10/14

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• nSYNC @ 48 channels

• 4 GBTx for hit+ TDC data– Slave GBT– Widebus 112 bits

• 16 bits for header• 48 bits for data hits• 48 bits for TDC data

– 12 out of 48 channels (25% occupancy)

– Truncation event by event

• 1 GBTx forTFC/ECS– MasterGBT

• 1 GBT-SCA

• 2 VTTx

• 1 VTRx

nODE NOW

nSYNC

48In

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Trig

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TD

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VTTx

GBTx

GBTx

VTTx

GBTxECS

VTRxGBTSCA

nSYNC

48In

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t ch

Trig

hit

TD

C o

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nSYNC

48In

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t ch

Trig

hit

TD

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nSYNC

48In

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t ch

Trig

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TD

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GBTx

GBTx

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• Livelli logici usati– SLVS e CMOS

• Input clock– Power-up

• Ha bisogno di un reference clock per effettuare la procedura di startup del chip e di inizializzazione del link

• 3 opzioni1. Low-jitter external clock opzione consigliate per i GBT slave2. External clock+internal XPLL opzione consigliate per i GBT slave3. Internal XPLL in XOSC mode (usa un quarzo incapsulato nel package) opzione

consigliate per i GBT master

• La scelta viene effettuata tramite un pin esterno tra opt. 1 e 2/3 e con un registro interno tra opt.2 e 3

• Alla fine della procedure di power-on ( 2ms) vengono generati dei segnali di ready– rxRdy (receiver ready): the receiver part of the GBTX is ready for operation– txRdy (transmitter ready): the transmitter part of the GBTX is ready for operation

– Dopo l’init del link ottico il clock del GBTx è sincrono con:• il clock estratto dai dati del link ottico se il GBTx lavora in modalità duplex• il reference clock se il GBTx lavora in modalità Simplex-TX

GBTx clock

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• Occorre scegliere uno schema che– Garantisca la massima flessibilità– Minimizzi il numero di input verso l’nSYNC

– Nota: bisogna capire se/come sincronizzare il clock con i comandi del TFC

GBTx clock

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• 4 bit Header (H) field (2 types)• 2 bit Internal Control (IC) field used to control and monitor the GBTX operation

– Its use is strictly reserved for the GBTX control. • 2 bit External Control (EC) field to implement a slow control channel (e.g. for the GBT-SCA)

– its use is not restricted to this application and can be used for generic data transmission applications.

• 112 bit Data (D) field for generic transmission of data

GBTx wide frame format

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• Recommended communication links within a FE module

TFC+ECS

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• List of mandatory monitoring counters in an FE module

ECS interface

PCIe40 Firmware• In Rome2 the PCIe40 firmware development environment is

ready

• Minidaq boad expected by the end of the month – currently under test in Marseille

• Then:– start Minidaq standalone testing– Useful environment to start developing new ECS software (M. Carletti)– Will purchase few GBT test board (with VTTRx, GBT & GBT-SCA)

Roma, October 10, 2014 A. Cardini / INFN Cagliari 11

MiniDaq MiniDaq GBT test b.

Valerio Bocci 2014

New Service Board Module(multiple GBT old Backplane)

CLK40

BC Pulse

Test/pulse

SCLSDA_INSDA_OUTTest/PulseRESET

ttl/lvds converter

Test/pulse

Test/pulse

Test/pulse

3xLVDS I2c

each ELMB

test pulselogic

1

2

3

1

2

3

1

2

3

1

2

3

GBT-SCA

Long line I2CFE converter

FlashFPGA

IGLOO2Actel FlashFPGA

E-Link 80 Mbits/s

12 x I2Clines

I2C

Long line I2CFE converter

Long line I2CFE converter

Long line I2CFE converter

Valerio Bocci 2014

New Pulse Distribution Module single GBT

GBT

2 LVDS

40 MHzMachine

CLKBC counter

2 LVDS

SyncBC

pulse

GBT Fiber

BCPulse

Generator

I2C

16 xE-Link

80Mbits/s

IGLOO2Actel FlashFPGA

Valerio Bocci 2014

New Custom Backplane

PDM

SLOT

80 Mbits/s E-LINK

New Custom Backplane routing 80 Mbits/s E-Link LinesAnd Service line

Valerio Bocci 2014

EB Igloo2

Cardiacs

LVDS

Patch bypass lvds

SB

LVDS Test of the new IGLOO2 Flash FPGA

LVDS Test using IGLOO2 bypassing SB

• Service Board

• IGLOO2 Evaluation Board

• Microcontroller Board to drive standard I2C

Removing HW Muon LLT option

• The final design of the nSYNC ASIC and of the nODE board depend also on how we are planning to implement the Muon LLT

• A SW-only muon LLT will allow an hardware simplification and an important money saving (fewer pins on the nSYNC, fewer optical link on the nODE) because we could remove the output lines to the LLT

• In addition, further changes to the current muon system layout are only possible in the case of a full software LLT

• Discussions have already started during an electronics upgrade meeting on June 27th, 2014; there are no opposition in principle (SW LLT is already the baseline)

• In Orsay we decided to approve this choice at next TB in December. A documents describing advantages/disadvantages will be prepared together with Julien C.

Orsay, 16/09/2014 A. Cardini / INFN Cagliari 16