Muon Port Card, Optical Link,

Muon Sorter Upgrade Status

M.Matveev

Rice University

December 17, 2009

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

2

Present Optical Link System Present optical links to CSC Track Finder run at 1.6Gbps

(one link per LCT)

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

3

New Optical Link Requirements 18..24 LCTs from MPC to SP per 1 or 2 bunch crossings

- 21 (24) LCTs from 24 peripheral crates with the new TMBs

- 18 LCTs from all other crates Preserve and enhance sorting capabilities of the Port Card 32-bit LCT (present format) Same link partitioning at the SP input

(ME1/ME1/ME2/ME3/ME4) All optical links should fit single Track Finder crate Radiation tolerant serializer Use existing TTC components and clock distribution paths

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

4

Use of the 2nd Bunch Crossing

Introduces the dead time. How critical is it? How to determine that the extra LCT belongs to the

previous BX?

- Use unique Wire Group ID=255 (valid values are 0..159)

arriving from TMB in the first frame ?

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

5

Proposed Link Architecture Use discrete Texas Instruments TLK2501 serializer on MPC ● Space and power consumption are not a problem on MPC

● Well understood and proven device

● Don’t need to change anything in the synchronization procedure

● Better radiation tolerance than embedded FPGA SERDES

● Coupled with 12-channel parallel optical transmitter Use embedded deserializers in the front FPGA on SP ● Solves the problem of limited space and excessive heat dissipation

● Inexpensive XC5VLX50T could be a good choice for the front FPGA

● Deserializer core compatible with the TLK2501 needs to be created Increase transmission frequency from 80MHz to 120MHz ● QPLL2 ASIC delivers either 40/80/160MHz (default) or 40/60/120MHz low-jitter clocks, depending on quartz. We can use QPLL2-produced clean 120MHz clock on MPC board to drive the SER. We can use the present QPLL2-based custom clock daughter board sitting on top of SP to produce the 120MHz clock for the DESER and front FPGA.

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

6

Muon Port Card Block Diagram

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

7

Sector Processor’s Front Section

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

8

Clock Options 3 “old” TLK2501 links:

- 80MHz from the CCB or internal QPLL 12 “new” TLK2501 links:

- 80MHz or 120MHz from internal QPLL

- At 80MHz the MPC may deliver 12 LCTs in one bunch crossing or 24 LCTs in two bunch crossings

- At 120MHz the MPC may deliver 18 LCTs in one bunch crossing or up to 36 LCTs in two bunch crossings

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

9

Latency TLK2501 latency:

• Tx+Rx: (34..38 bit times)+(76..107 bit times) = 110..145 bit times

• Min/Max transmitter latency at 80MHz = 21..24 ns

• Min/Max transmitter latency at 120MHz = 14..16 ns Xilinx Virtex-5LXT latency:

• Tx: 4-9.5T (T – period of TXUSRCLK)

Rx: 8.5-13.5T (T – period of RXUSRCLK)

• Rx latency = 106..169 ns @ 80MHz

70..112 ns @ 120MHz

• Need to take into account the max number which includes the 8B/10B encoding/decoding delay

Total latency for TLK2501 + V5LXT would be:

~ 190 ns at 80MHz, or ~4.5BX larger than present link

~ 125 ns at 120MHz, or ~3BX larger than present link

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

10

Optical Interface 12-channel parallel optical transmitter/receiver, SNAP12 industry standard

- Pluggable package, 100 pin array

- 49 x 17 x 11 mm in size

- 2.5 Gbps/channel typical

(6.25Gbps available)

- 1.2W typical power dissipation

- Up to 500 m low-loss MMF

- Several vendors (Avago Technologies,

Reflex Photonics, Emcore, Zarlink)

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

11

TMB Interface Same backplane pin assignment as MPC2004 Replace National GTLP18T612 receivers with Texas

Instruments SN74GTLPH16912 (same as ones on Muon Sorter)

Minor improvements in schematic design and layout TMB2005 uses 2 Fairchild GTLP16612 transmitters to send

LCTs to Port Card. This part seems to be obsolete. Do we have ~160 spares for new TMBs to assure the same delays?

Use 2 frames of 2 BX to deliver “winner” bits back to TMB On a firmware level the TMB-to-MPC timing should be the

same for the old and new TMBs

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

12

VME Interface Use the same approach as existing MPC2004:

- 1 main register and VME handshake in discrete logic

- all the rest in FPGA Will be compatible with the MPC2004 as much as possible

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

13

Sorter “12 LCTs out of 18” Target device: XC5VLX110-2FF1760

- Existing TF mezzanine board

- Middle speed grade

- < 40% resource usage

- ~5BX latency for sorter “12 out of 18”

~3.5BX latency for sorter “3 out of 18”

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

14

Sorter “12 LCTs out of 18”: Simulation

3.5BX = 87 ns

“Old” outputs “3 best out of 18” are multiplexed at 80MHz“New” outputs “12 best out of 18” are multiplexed at 120MHz

33 ns

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

15

FPGA Pin Count 9TMB x 32 bit @ 80MHz + 9 “winners” = 297 inputs/outputs VME + CCB interfaces => 150 inputs/outputs 12 TLK2501 x 16 bits = 192 outputs (12 new links) 3 TLK2501 x 16 bits = 48 outputs (3 old links)

Total: ~700 inputs/outputs

Existing Track Finder Virtex-5 Mezzanine card (~780 i/o pins) should be OK.

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

16

MPC2010 Design Status Schematic design is almost complete One Virtex-5 mezzanine in hand (thanks to Alex Madorsky) Two pairs of Zarlink ZL60101/102 12-channel optical

transmitters/receivers ($405/$368 each) and mating sockets ($16 each) are in hand

Optical fibers can be ordered from Dataaccessories.com or CablesToGo.com ($530..$900 per 100 m)

Custom components needed (common with the new TMB and SP?) - CERN designed QPLL2 ASIC - 120.24MHz and 160.32MHz quartz oscillator (CERN) - email from Jan Troska: We have the QPLL chips in the quantities that you mention (few dozens

to few hundreds).  Their cost is 10CHF each. The crystals have to be ordered from an outside manufacturer for quantities exceeding 10, on a 16-18 week lead time with MOQ 200.  For prototyping I can provide you with a few (<10) that work at 160MHz (cost 16CHF each).  We have never produced large quantities of 120MHz crystals, so there you take a risk and might have trouble ordering small quantities.

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

17

Proposed R&D Plan Build a full size prototype of the Muon Port Card in 2010 SNAP12 transmitter and receiver are electrically incompatible

- same 100-pin receptacle/socket, but different pin assignment Future MPC won’t be able to accommodate the SNAP12

receiver for testing purposes due to lack of i/o’s Options for the optolink receiver:

- Full size SP prototype with five SNAP12 receivers

- Smaller 6U prototype with one SNAP12 receiver, FPGA and

VME interface

- Small mezzanine board with one SNAP12 receiver and one

front FPGA

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

18

Muon Sorter Upgrade According to our R&D Proposal submitted in October 2007,

the Muon Sorter upgrade is envisaged for phase 1, along with the Sector Processor

SP-to-MS Interface: - Stay with 3 muons/SP, 36 muons/CSCTF? - Same backplane? MS-to-GMT interface: - GMT upgrade plans are unknown, but likely will follow the

CMS trigger upgrade path - 4 muons per CSC system? MS processing logic: - Upgrade to existing V5 mezzanine FPGA? ■ May reduce sorting latency from 2 BX to 1 BX Connection to/from Tracker Trigger?

17 December

2009

EMU Electronics Upgrade Meeting, Rice University, 17-18 December 2009

19

Conclusion

- Straightforward evolutional design of the new MPC and optolink

- Proven clock sources and synchronization procedure

- 12-channel parallel Tx/Rx will allow to reduce the number of

optical cables from three to one per MPC and greatly relax

the SP front panel

- 3..5 BX latency increase for the optolink

- Discrete SER is more robust solution for radiation environment

- Can use existing mezzanine board with Virtex-5 FPGA

- All components are available