Multilevel Inverter with Reduced Number of Switches for ... · PDF fileInternational Journal of Engineering Technology, Management and Applied Sciences August 2015, Volume 3, Issue

International Journal of Engineering Technology, Management and Applied Sciences

www.ijetmas.com August 2015, Volume 3, Issue 8, ISSN 2349-4476

177 Ramesh P N, Thomas Joseph

Multilevel Inverter with Reduced Number of Switches for Grid

Connected PV System

Ramesh P N M.TECH student

EEE Department, SJCET Palai

Thomas Joseph Assistant Professor

EEE Department, SJCET Palai

Abstract- Solar energy is one of the renewable energy

which is used to generate electricity with the help of PV

arrays. DC-DC converter is used to step up the DC

voltage from PV arrays and then it is connected to an

inverter for AC applications. Conventional inverters have

many issues like non sinusoidal output, high total

harmonic distortion (THD), high switching stress and

more number of switches. So multilevel inverter (MLI)

have gained much importance over conventional inverters

for high voltage and high power applications, due to the

increased number of voltage levels producing less number

of harmonics. A cascaded asymmetric multilevel inverter

is proposed which contains minimum number of switches

and can be employed in AC applications using solar

energy. The propose topology consists of 25 output levels

using 10 switches with near sinusoidal output, thereby

reducing gate driver circuitry and optimizing circuit

layout. Asymmetric multilevel inverter is more

advantageous than symmetric multilevel inverter in

obtaining more number of output levels using same

number of voltage sources. The other advantages of

proposed topology are low voltage stress and reduced

THD. The THD for proposed inverter circuit is only

4.98%. Key words: grid connected, photovoltaic (PV), pulse

width modulated(PWM) inverter. Multilevel Inverter;

Total Harmonic Distortion; Cascaded Asymmetric.

I. INTRODUCTION

THE DEMAND for renewable energy has increased significantly over the years because of shortage of fossil fuels and greenhouse effect. Among various types of renewable energy sources, solar energy and wind energy have become very popular and demanding due to advancement in power electronics techniques. Photovoltaic (PV) sources are used today in many applications as they have the advantages of being maintenance and pollution free. PV inverter, which is the heart of a PV system, is used to convert dc power obtained from PV modules into ac power to be fed into the grid. Improving the output waveform of the inverter reduces its respective harmonic content and, hence, the size of the filter used and the level of electromagnetic

interference (EMI) generated by switching operation of the inverter. In recent years, multilevel inverters have become more attractive.

Fig. 1. Carrier and reference signals.

Inverters are power electronic devices that convert DC power into AC power. Available in wide power ratings that range from certain VA to several MVA, they find application in home appliances, photovoltaic power supplies, and uninterrupted power supplies etc. The AC output available from an inverter should have less distortion in order to obtain a good power quality. To obtain low distortion on the output voltage waveforms, the conventional inverters are switched at very high frequency ranging from few KHz up to 100 KHz . Multilevel inverters include diode clamped converter, flying capacitors, cascaded and H-bridge MLI . This MLI help to achieve near sinusoidal output waveforms with reduced THO. As the number of output levels increase, harmonics decrease. The disadvantage of conventiona l MLI is that if more number of output levels are required, then more number of components are needed and due to this complexity increases in gate driver circuits. At present the most famous hardware implementable topologies are cascaded H-bridge and the diode clamped. The drawback of symmetric MLI can be overcome by asymmetric MLI. Multilevel inverters employ different modulation technique for getting a better output voltage with minimum harmonic distortion. Sinusoidal Pulse Width Modulation , Selective Harmonic Elimination, Space Vector Modulation techniques are some of the




commonly used modulation techniques for multilevel inverters.

II. FIVE-LEVEL INVERTER TOPOLOGY The proposed single-phase five-level inverter topology is shown in Fig. 2. The inverter adopts a full-bridge configuration with an auxiliary circuit. PV arrays are connected to the inverter via a dc–dc boost converter. Because the proposed inverter is used in a grid-connected PV system, utility grid is used instead of load. The dc–dc boost converter is used to step up inverter output voltage Vinv to be more than √2 of grid voltage Vg to ensure power flow from the PV arrays into the grid . A filtering inductance Lf is used to filter the current injected into the grid. The injected current must be sinusoidal with low harmonic distortion. In order to generate sinusoidal current, sinusoidal PWM is used because it is one of the most effective methods. Sinusoidal PWM is obtained by comparing a high-frequency carrier with a low-frequency sinusoid, which is the modulating or reference signal. The carrier has a constant period; therefore, the switches have constant switching frequency. The switching instant is determined from the crossing of the carrier and the modulating signal.

Fig. 2 Single-phase five-level inverter topology.

III. OPERATIONAL PRINCIPLE OF THE

PROPOSED INVERTER

Fig. 3 Ideal five-level inverter output voltage Vinv.

Because PV arrays are used as input voltage sources, the voltage produced by the arrays is known as Varrays. Varrays is boosted by a dc–dc boost converter to exceed √2Vg. The voltage across the dc-bus capacitors is known as Vpv. The operational principle of the proposed inverter is to generate five level output voltage, i.e., 0, +Vpv/2, +Vpv, −Vpv/2, and –Vpv as in Fig. 3. As shown in Fig. 2, an auxiliary circuit which consists of four diodes and a switch S1 is used between the dc-bus capacitors and the full-bridge inverter. Proper switching control of the auxiliary circuit can generate half level of PV supply voltage, i.e., +Vpv/2 and −Vpv/2. Two reference signals Vref1 and Vref2 will take turns to be compared with the carrier signal at a time. If Vref1 exceeds the peak amplitude of the carrier signal Vcarrier, Vref2 will be compared with the carrier signal until it reaches zero. At this point onward, Vref1 takes over the comparison process until it exceeds Vcarrier. This will lead to a switching pattern, as shown in Fig. 4. Switches S1–S3 will be switching at the rate of the carrier signal frequency, whereas S4 and S5 will operate at a frequency equivalent to the fundamental frequency. Table I illustrates the level of Vinv during S1–S5 switch on and off.

Fig. 4 Switching pattern for the single-phase five-

level inverter.




IV .MODULATION TECHNIQUES OF MLI Multilevel PWM methods uses high switching frequency carrier waves in comparison to the reference waves to generate a sinusoidal output wave, much like in the two-level PWM case. To reduce harmonic distortions in the output signal phase-shifting techniques are used. There are several methods that change disposition of or shift multiple triangular carrier waves. The number of carrier waves used is dependent to the number of switches to be controlled in the inverter. A . Multimodulating phase shifted PWM.

Fig.5. Double refe rence single carrier modulation technique

Fig.6. Multicarrier level shifted modulation techniquesThe Phase Shifted PWM, shown in Fig 5, is a multicarrier modulation strategy that has all carrier waves phase shifted from each other. There is one triangular carrier wave for each full bridge module, phase shifted with 180°n in between them, with an amplitude of the magnitude of the total DC voltage. The carrier waves are modulated by the actual voltage level in the appropriate module. For the five-level with two modules there are two triangular carrier waves, one for each module. There are also two reference waveforms for the two legs in each inverter modules that are phase shifted 180° from each other. Both reference waves are compared with both carrier waves, one reference wave is for

modulation of the left full-bridge module leg switches (dashed reference wave) and the other reference wave to modulate the right full-bridge module leg switches (solid reference wave). Close to 2ms in the plots it can be seen that the first triangular wave crosses one reference wave downwards, controlling the right leg switches of the modules, turning that modules output voltage from 0 kV to -0.5 kV. Closely after the second carrier wave crosses the same reference wave (the one that controls the right leg switches in the modules) upwards turning the output voltage from -0.5 kV to 0 kV. Comparisons with other reference wave work in the same wave, but then controlling switches in the modules left legs. As the plots suggest the two modules share the workload for all levels, no module is strictly connected to one voltage level in the output. B. Multicarrier level shifted modulation techniques In Phase Distortion PWM (PDPWM), Figure 6., all carrier waves are in phase. A great acknowledgment for this technique is that it is generally accepted as the method that creates the lowest harmonic distortion in line-to-line voltage. PDPWM modulation is built up of m-1 carrier waves, two for each full-bridge module, one below zero and one above zero for every module. Each module then modulates one voltage level. Which level one full-bridge module modulates can be changed for balancing purposes. For the five-level inverter, the module with highest charge within its source is modulated by the carrier waves two and three in if counting the carrier waves from top to bottom. The other module, with lower charge, would then be controlled by carrier waves one and four. Since waves two and three are closest to zero the first module, with higher charge, will be connected to the load first every half cycle, for both positive and negative output voltages. This will lead to a higher workload for this module. More generally, the two triangular waves close to zero (one wave with positive voltage and one with negative voltage) can control the module with the highest charge if active power is to be transferred. The positive carrier then modulated the full-bridge modules left leg for positive output voltages and the negative carrier the right leg for negative output voltages. Other modules should be controlled by two carrier waves further away from zero, one from each side of zero voltage at the same position (second wave above and second wave below zero, for example). The carrier waves




amplitudes should be modulated by the voltage level in the full-bridge module it controls, much like with the carrier wave modulation for PSCPWM, so that correct output voltages are generated during the correct time spans.

V. CONVENTIONAL 5-LEVEL CASCADED HBRIDGE INVERTER

Cascaded H-Bridge configuration has recently become very popular in high-power AC supplies and adjustable-speed drive applications. A cascade multilevel inverter consists of a series of H-bridge (single-phase full bridge) inverter units. Each H-bridge unit has its own dc source. Each SDC (separate D.C. source) is associated with a single-phase full-bridge inverter. The ac terminal voltages of different level inverters are connected in series. Fig. 1 shows a single phase structure of a cascaded H-bridge inverter with separate D.C. sources. Through different combinations of the four switches, S1-S4, each converter level can generate three different voltage outputs, +Vdc, -Vdc and zero. To obtain +Vdc switches S1 and S4 are turned on. On turning on S2 and S3 together we get the output –Vdc. On turning the switches S1 and S2 together or S3 and S4 together or S1, S2, S3, S4 simultaneously we get the output 0. The AC outputs of different full-bridge converters are connected in series such that the synthesized voltage waveform is the sum of the individual converter outputs. In this topology, the number of output-phase voltage levels is defined by M= 2N+1, where „M‟ is the no of levels and „N‟ is the number of DC sources.

Fig.7.conventional 5-level cascaded H-bridge

inverter

VI. PROPOSED MULTILEVEL INVERTER The proposed topology of multilevel inverter is employed by cascaded arrangement of two basic cells. Here the Fig.8 shows MLI where 25 output levels are obtained by using only 10 switches. This arrangement can be further augmented by cascading' P' number of basic cells in series. As the number of output levels is increased the output approaches close to sinusoidal waveform. This topology contains two cascaded basic cells. Each cell consists of two equal voltage sources. The voltage sources of second basic cell are in ratio of l:5 with respect to voltage sources of first basic cell. This topology helps to generate 25 output levels. This arrangement is defined as asymmetric MLI because of unequal voltage sources in two respective basic cells.

If 'P' numbers of basic cells are cascaded for this particular topology then the output levels will be 5

P

and value of maximum voltage level is equal to (Vdc ) (5-5-

(P-l) ) /2

Similarly if voltage sources of P cascaded cells are equal to the voltage sources of other basic cells that is in l: 1 ratio then the arrangement is defined as symmetric MLI.

Vll= Vl2 = V21= V22= VPI= VP2= Vdc (4) This arrangement would generate 4P+ 1 output levels and value of maximum output voltage level is 2P X V dc .

Fig.8 Proposed MLI with 10 switches




The diodes are arranged as shown in the Fig.8. Total number of diodes for one basic cell is 4. So if 'P' cascaded basic cells are used then the total number of diodes required is given by 4P (anti-parallel diodes across switch are not considered). Here in proposed topology total 8 diodes are used.

VII. OPERATION OF PROPOSED MLI The operation of the proposed MLI is illustrated from the switching states in TABLE-III below. The path of current flow is shown in Fig.9 and Fig. 10, for positive level and negative level respectively. Zero output voltage is represented with two switching states. Switches SIS and S25 are select switches of two respective basic cells. These switches help to add number of output levels. When all basic cells are cascaded in series, output voltages of each basic cell are added together to achieve [mal output voltage across MLI.

Fig.9 Current flow path during positive output levels

Fig.10 Current flow path during negative output

levels

VIII. SIMULATION RESULTS The THD comparison between multimodulating and multicarrier PWM techniques for five level inerter is conducted and obtained that for the multi carrier based PWM technique has lower THD compared to that of the multimodulating PWM technique.

Fig.11 Harmonic spectrum of multimodulating

PWM technique

Fig.12 Harmonic spectrum of multicarrier PWM

technique By comparing both the PWM techniques the DC component of multicarrier is half of that of the multi modulating PWM technique also the THD is less for the multicarrier PWM technique.




The simulation for proposed topology is done using 10 switches and the voltage sources in second basic cell are equal to each other but in 1:5 ratios with voltage sources in first basic cell. FFT window is used for harmonic spectrum analysis in MATLAB

Fig.13 SIMULINK model of proposed topology

Fig. 14 Output Voltage

Fig.15 FFT analysis of 25 level inverter using 10

switches The main advantage is that THD is 4.98% which is less than S % and output is almost near-sinusoidal waveform.

IX. CONCLUSION A Cascaded multilevel inverter is proposed which requires minimum number of switches with increased output levels where, output waveform is near-sinusoidal. Compared with conventional multilevel inverters, it requires less number of components to achieve same number of output levels. Overall THD is very low and thus the quality of output waveform is improved. Also this asymmetric multilevel inverter is more advantageous over symmetric multilevel inverter using same number of switches, for producing more number of output levels. Due to the use of fewer switches, optimized circuit layout and packaging is possible. Thus less cost is required to implement the proposed inverter. When sinusoidal pulse width modulation (SPWM) technique is installed THD value will reduce even further. Here the multicarrier modulating techniques is used for the gate pulse generation of each switch, due to this the THD is comparatively less. This topology can be successfully installed for solar based ac applications References

[1] Jeyraj Selvaraj and Nasrudin A. Rahim, Senior

Member, IEEE, “Multilevel Inverter For Grid-

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[4] P.Vaishnavi1, Dr.R.Seyezhai2, “Analysis of PWM

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Multilevel Inverter with Reduced Number of Switches for ... · PDF fileInternational Journal of Engineering Technology, Management and Applied Sciences August 2015, Volume 3, Issue