Multilevel inverter Modulation schemes to eliminate Common-Mode Voltages

IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 36, NO. 6, NOVEMBER/DECEMBER 2000 1645

Multilevel Inverter Modulation Schemes to EliminateCommon-Mode Voltages

Haoran Zhang, Member, IEEE, Annette von Jouanne, Senior Member, IEEE, Shaoan Dai, Student Member, IEEE,Alan K. Wallace, Fellow, IEEE, and Fei Wang, Senior Member, IEEE

Abstract—It is well known that conventional two-levelpulsewidth modulated (PWM) inverters generate high-fre-quency common-mode voltages with high . Similarly,commonly used multilevel inverter modulation schemes generatecommon-mode voltages. Common-mode voltages may cause motorshaft voltages and bearing currents and conducted electromagneticinterference (EMI). Premature motor bearing failures and elec-tronic equipment malfunctions have been reported to be directlyrelated to bearing currents and EMI. In this paper, approaches toeliminating common-mode voltage when using multilevel PWMinverters are presented. It is shown that inverters, which have anodd number of levels, will generate zero common-mode voltage byswitching among certain states. Therefore, motor bearing currentswill be eliminated and conducted EMI will be reduced. Bothsinusoidal PWM and space-vector modulation (SVM) schemes arediscussed and detailed comparative simulation results betweenconventional and novel modulation schemes are provided. Thevalue of the proposed technique is demonstrated experimentallyby applying the novel SVM approach to a conventional multilevelinverter.

Index Terms—Common-mode voltages, modulation schemes,motor drive, multilevel converter, multilevel inverter.

I. INTRODUCTION

CONVENTIONAL two-level pulsewidth modulated(PWM) inverters and multilevel PWM inverters generate

common-mode voltage within the motor windings which mayresult in motor and drive application problems [1]–[3]. Thecommon-mode voltage enables motor shaft voltage to build upthrough electrostatic couplings between the rotor and the statorwindings and between the rotor and the frame, resulting inexcessive bearing currents when the shaft voltage exceeds thedielectric capability of the bearing grease. It has been found thatbearing currents may cause premature motor bearing failures.At the same time, the common-mode voltage will cause a muchlarger common-mode leakage current to flow into the groundvia electrostatic coupling between the stator windings and thegrounded frame. Since this current will eventually flow back to

Paper IPCSD 00–030, presented at the 1998 Industry Applications SocietyAnnual Meeting, St. Louis, MO, October 12–16, and approved for publication inthe IEEE TRANSACTIONS ONINDUSTRY APPLICATIONSby the Industrial DrivesCommittee of the IEEE Industry Applications Society. Manuscript submittedfor review October 15, 1998 and released for publication June 19, 2000.

H. Zhang is with Texas Instruments Incorporated, Tucson, AZ 85706 USA(e-mail: [email protected]).

A. von Jouanne, S. Dai, and A. Wallace are with the Department of Electricaland Computer Engineering, Oregon State University, Corvallis, OR 97331-3211USA (e-mail: [email protected]; [email protected]; [email protected]).

F. Wang was with GE Industrial Systems, Salem, VA. He is now with the GEChina Technology Center, Shanghai, China (e-mail: [email protected]).

Publisher Item Identifier S 0093-9994(00)10423-2.

the input terminals through the ground conductor and the powermains, it will cause significant common-mode electromagneticinterference (EMI) emission. In addition, the leakage currentmay cause false tripping of ground current relays installed forprotection. There have been a number of mitigation techniquessuggested for the bearing current problem and conducted EMI.However, few of them have addressed the common-modevoltage directly and successfully and none of them have beenfound within the context of multilevel PWM inverters. In [4],a dual-bridge inverter (DBI) is presented to generate zerocommon-mode voltage. Although the motor shaft voltage andthe resulting bearing currents are eliminated successfully, adouble-winding (i.e., a dual voltage) induction motor becomesnecessary. The DBI has also been shown to be able to reduceconducted EMI significantly [5]. In [6], an active filter is pro-posed to cancel the common-mode voltage and reduce groundcurrent and conducted EMI, however, a common-mode trans-former of significant size has to be used. Besides these effortsdevoted to new inverter topologies, a space-vector algorithmwas also proposed to minimize the neutral-to-ground voltageof the motor stator winding to by synchronizing theswitching sequence of the rectifier and inverter, which limitsthe current control capabilities [7].

Multilevel inverters have received increased interest dueto their operational advantages [8]–[17]. Three-level PWMinverters, usually in the form of either diode-clamped multilevelinverters (DCMLIs) or flying-capacitor multilevel inverters(FCMLIs), are typically considered for medium-voltage level(2300/4160 V) drives to reduce the voltage rating of the powerswitching devices as well as the harmonic components of theoutput voltages. However, commonly used modulation schemesstill result in nonzero common-mode voltages [8]–[17]. In thispaper, two modulation schemes are suggested for the controlof multilevel inverters to eliminate common-mode voltages.It will be shown that a three-level inverter will not generatecommon-mode voltages when the inverter output voltagesare limited within certain of the available switching states.The same concept could be extended to other odd numbermultilevel inverters. At medium voltage levels, such controlledmultilevel inverters will still provide reduced device voltageratings and improved harmonic characteristics over two-levelinverters, whereas, at low voltage levels (230 V/460 V),three-level inverters could be considered mainly for the purposeof cancellation of common-mode voltages. Simulation resultsusing Matlab are provided in this paper to verify the concept,and experimental results confirm the value of the proposedswitching-state algorithm.

0093–9994/00$10.00 © 2000 IEEE

1646 IEEE TRANSACTIONS ON INDUSTRY APPLICATIONS, VOL. 36, NO. 6, NOVEMBER/DECEMBER 2000

Fig. 1. Output stage of an NPC inverter.

Fig. 2. Possible switching states of a three-level inverter.

II. M ODULATION SCHEMES FORCOMMON-MODE VOLTAGE

ELIMINATION

The output stage of conventional two-level PWM invertersconsists of three phase legs with two switches on each leg. Theoutput of each phase is either or . Therefore,the combinations of the three-phase output voltages result in8 ( for ) switching states, i.e., , ,

, , , , , and. To be more clear, represents the following output

voltage: , , and . Since thecommon-mode voltage is defined as ,it is not zero for all of the above switching states.

The first three-level diode-clamped voltage-source inverter,the neutral-point-clamped (NPC) inverter, was first proposedby Nabeaet al. [8]. Fig. 1 shows the output stage of the NPCvoltage-source inverter (VSI). It consists of 12 switches, 12 an-tiparallel-connected freewheeling diodes, six clamp diodes, anda split dc bus via two capacitors. There are two important fea-tures of the NPC-VSI compared to conventional two-level in-verters. First, four switches are used in series for each inverterleg instead of two, allowing the off-state switches to sustain only

Fig. 3. Seven states with zero common-mode voltage.

Fig. 4. Synthesis of the reference voltage vectorV .

half of the dc-bus voltage instead of the full voltage. Second,the output voltage of each phase has three levels, i.e., ,0, and . An increased number of voltage levels resultsin increased switching states. In this case, the NPC-VSI has 27

states as shown in Fig. 2 [9]. Among these switching states,there are seven states that will result in zero common-mode volt-ages. They are , , , , , ,and (0 0 0), i. e., – (see Figs. 3 and 4). It is obvious that thecommon-mode voltage of the NPC inverter is zero for all theabove seven states. Therefore, by limiting the switching statesonly to those listed above, an NPC inverter will not generatecommon-mode voltage. This idea could be equally applied toFCMLIs and higher level inverters. However, since only voltagelevels of odd numbers contain the state of zero output voltage(0 0 0), even number level inverters (i. e., two, four, six levels,etc.) cannot be controlled in this way to achieve common-modevoltage cancellation.

Like conventional inverters, the main purpose of the controlof multilevel inverters is to synthesize the output voltage as closeas possible to the desired waveform, e.g., sinusoidal waveforms.

ZHANG et al.: MULTILEVEL INVERTER MODULATION SCHEMES 1647

Fig. 5. Sine-triangle intersection (SPWM) waveforms for a three-levelinverter.

Fig. 6. Sine-triangle (SPWM) for common-mode voltage cancellation.

Many modulation schemes have been developed with consid-erations to harmonic generation and switching loss minimiza-tion. However, the traditional sinusoidal PWM (SPWM) and thespace-vector modulation are still considered good choices formultilevel PWM inverters due to the resulting overall inverterperformance. Therefore, detailed investigation into both modu-lation schemes to achieve common-mode voltage elimination ispresented in the following sections.

A. Voltage Space-Vector PWM

Any three-phase quantities, e.g., three-phase voltages orcurrents, can be represented by a space vector in the– planevia Park’s transformation. The vector starts from the origin andends at a certain point so that the length and the phase angleof the vector together represent the instantaneous values of theparticular three-phase quantities. If the three-phase quantitiesare sinusoidal functions of time and are symmetrical (bal-anced), the vector will be rotating at a constant angular velocity

Fig. 7. Three-level inverter with conventional SPWM.

Fig. 8. Three-level inverter with SPWM with common-mode voltagecancellation.

and has a constant length and, thus, the locus of the vectorforms a circle. In other words, a rotating voltage vector canrepresent three-phase sinusoidal voltages mathematically. If thethree-phase quantities are not symmetrical, Park’s transforma-tion gives not only , components, but also a zero-sequencecomponent that is the mean value of the three-phase quantities.As far as the output voltages of a PWM-VSI are concerned,this zero-sequence component is the common-mode voltage ofthe inverter.

The basic idea of voltage space-vector modulation is to con-trol the inverter output voltages so that their Park representa-tion approximately equals the reference vector, which is thePark representation of the desired three-phase voltage [13]. Inthe case of a three-level inverter, the 27 switching states create19 voltage vectors, including a zero vector as shown in Fig. 2.These voltage vectors divide the– plane into 24 triangularsections. When the reference voltage vector falls in one of thesesections, adjacent voltage vectors are selected to synthesize the


Fig. 9. Three-level inverter with SVM.

Fig. 10. Three-level inverter with SVM with common-mode voltagecancellation.

desired voltage vector based on the time-averaging principle,resulting in three-phase PWM waveforms. If the synthesizedvoltage vector is a good approximation to the reference vector,the three-phase PWM voltages should be good approximationsto the desired three-phase voltages.

Since three-level inverters have many more switching statesthan two-level inverters, the algorithm for the determination ofwhich triangular section belongs to and the selection of theswitching states and switching pattern are more difficult. How-ever, they become quite straightforward if coordinate transfor-mation is used. Fig. 3 shows the synthesis algorithm of an arbi-trary reference voltage in – – reference frame using ap-propriate space vectors and coordinate transformations. First ofall, the whole voltage vector space is divided into six equal sec-tors, I-VI, by the dotted lines. By the examination of the phase

Fig. 11. Voltage spectra of a two-level inverter with SVM(m = 1:15).

Fig. 12. Voltage spectra of a two-level inverter with SPWM(m = 1).

angle of , the sector wherein resides can be easily lo-cated. As an example shown in Fig. 3, the reference vectoris inside sector I. To synthesize , it is also necessary to de-termine which triangular section it belongs to in the– plane.To obtain this information, coordinate transformations could beused. In the shown example, since is in sector I, it is ap-propriate to transform the vector in– – into in – –using the following equation:

(1)

It is again straightforward to locate the exact triangle whereinresides by looking at the phase angle of . In this ex-

ample, it is the triangle defined by vector , and . Itshould be noted that, whichever triangle is located, it belongsto the hexagon centered at. By acknowledging this, a simplecontrol algorithm similar to that of the conventional two-levelSVM is obtained, which also features low harmonic distortionin the PWM output voltage waveforms.


Fig. 13. Voltage spectra of a three-level inverter with SVM(m = 1:15).

Fig. 14. Voltage spectra of a three-level inverter with SPWM(m = 1).

For example, a reference voltage in sector I will be synthe-sized by and two of – , which define the hexagon cen-tered at . Similarly, and two of the six vectors that de-fine the hexagon centered at could synthesize another ref-erence voltage vector, which is located in sector II. In general,any reference voltage within the boundary defined by the outerhexagon in – – coordinate, , should be first allocated intoone of the six smaller hexagons. For the voltage reference withineach hexagon, it should be expressed as in – – refer-ence frame and then synthesized using the same switching pat-tern and timing calculation as those for a two-level inverter. Itshould be noted that, according to Figs. 2 and 3, bothand

have two states. When synthesizing a voltage in sector I, forexample, both state and state of are used andonly state of is used. However, when synthesizing avoltage vector in sector II, both state and stateof are used and only the state of is used. The re-dundant zero states and are never used.

Fig. 15. Voltage spectra of a three-level inverter with SVM and common-modevoltage cancellation(m = 1).

Fig. 16. Voltage spectra of a three-level inverter with SPWM andcommon-mode voltage cancellation(m = 0:87).

Fig. 4 shows the maximum obtainable voltages of the NPCSVM in – domain. The largest voltage vectors are– .However, if a three-phase balanced voltage set is to be synthe-sized using the SVM scheme described above, the maximumvoltage vectors will be – , the amplitude of which is thesame as that of a two-level SVM. Since the modulation index isdefined as

(2)

where is the magnitude of the fundamental component ofthe phase-to-neutral voltage, the maximum modulation indexwith linear modulation is, therefore, [13]:

(3)

This control algorithm has resulted in significantly improvedoutput voltage waveforms compared with two-level SVMinverters. However, using most of the 27 states or all the 19


voltage vectors to synthesize the PWM output voltage inevitablygenerates nonzero common-mode voltages. To eliminate thecommon-mode voltage, only the above-mentioned seven vectors

– out of 19 voltage vectors should be used to synthesize theoutput voltage. Similar to the SVM for two-level PWM inverters,thesixnonzerovectors – dividethe – plane intosixsectorsas shown in Fig. 4. If, for instance, the reference vector sits inthe sector defined by vectors and , the switching state ofthe NPC inverter should be selected alternatively among thosecorrespondingtovectors , ,and .

From the time-averaging principle, the time duration for eachstate is determined by the following equation:

(4)

In the above equation, all vectors are constant and ,therefore, the volt-second equation is obtained

(5)

Given and , , can be calculated from thesecond equation. The time for zero state is given by

(6)

It should be pointed out that the maximum modulation index forthis modulation scheme is times that of the conventionaltwo- level SVM according to Fig. 4. It can be verified from (3)that the maximum modulation index in this case is ,which is the same as that with SPWM for two-level inverters.

B. SPWM

SPWM has been widely used in conventional two-levelinverters due to its simplicity and low harmonic distortion char-acteristics. For similar reasons, this method has been extendedto multilevel inverter control. It has been suggested thattriangle carrier signals should be used for an-level inverter andonlyonesinusoidalmodulationsignal foreachphase[10], [11].

Fig. 5 shows the waveforms of sine-triangle intersection(SPWM) and the resulting phase-to-neutral voltage for an NPCinverter. Two carriers together with three modulation signalshave been used to obtain SPWM control (only one modulationsignal is shown). The intersection of the sinusoidal signal withthe upper triangle signal results in the positive PWM phasevoltage, whereas the intersection of the sinusoidal and the lowertriangle signals results in the negative PWM phase voltage.

AlthoughthisSPWMmethodprovideslowharmoniccontentinthe output voltages, it does not guarantee that the switching statesof the inverter are within those seven states which would result inzero common-mode voltage. An alternative SPWM scheme canbe used which does not generate nonzero common-mode volt-ages. Similar to the SPWM for two-level inverters, this methodemploys one triangle carrier signal and three balanced sinusoidalmodulation signals (i.e., , , and ). At first, two of thethree modulation signals, e.g., and , are compared withthe carrier signal resulting in two intermediate PWM signalsand foronephase(notshown).Then,subtractionoffromcreatesthePWMsignal for thesamephase,asshowninFig.6.Thesamealgorithmshouldbeappliedtotheother twophases.

Fig. 17. Multilevel inverter common-mode voltage with conventional SVM:dc-link voltage= 750 V; f = 1:0 Hz; modulation index= 0:175.

Fig. 18. Multilevel inverter common-mode voltage with modified SVM:dc-link voltage= 750 V; f = 1:0 Hz; modulation index= 0:175.

To summarize, we have the following equations:

(7)

Therefore, the common-mode voltage is equated as

(8)

It is important to note that this SPWM scheme guaranteesthat the switching happens only among those states with zerocommon-mode voltage.


III. SIMULATION RESULTS

The concept of common-mode voltage cancellation usingthree-level inverters is proven by simulation in Matlab. Figs. 7and 9 show the phase-to-neutral, the phase-to-phase, and thecommon-mode voltages of a three-level inverter using bothconventional SPWM and SVM. The peak-to-peak value ofthe common-mode voltage is as high as 1/3 of the dc-linkvoltage. However, common-mode voltage cancellation usingthe suggested SPWM and SVM is obtained, as shown in Figs. 8and 10, respectively.

In addition, frequency spectra are obtained as a result of thefast Fourier transform (FFT) on the output voltages with max-imum fundamental component under linear modulation condi-tion. Figs. 11 and 12 show the frequency spectra of the outputvoltage of a two-level inverter using both SVMand SPWM , respectively. These results serveas bases of comparison for the proposed modulation schemes.The frequency spectra for a three-level inverter with both SVMand SPWM are shown in Figs. 13 and 14, respectively. Com-pared to two-level inverters, three-level inverters with the estab-lished modulation schemes have significantly reduced harmoniccomponents while maintaining the same maximum modulationindexes. Figs. 15 and 16 are voltage spectra of the proposedthree-level SVM and SPWM for common-mode voltage can-cellation. Fig. 15 shows that the proposed three-level SVM withcommon-mode voltage cancellation has the same modulationindex as that of SPWM without common-mode voltage cancel-lation . However, the harmonic components of theoutput voltage are lower than those obtained from two-level in-verters but higher than those from three-level inverters with con-ventional SPWM and SVM. On the other hand, the modulationindex of three-level SPWM with common-mode voltage cancel-lation is limited to . The harmonic con-tent of its output voltage is close to that generated by three-levelinverters with SVM and common-mode voltage cancellation.

IV. EXPERIMENTAL RESULTS

In order to investigate the validity of the proposed schemesand their practical capabilities, experimental results were ob-tained by applying the proposed modified SVM approach toa conventional multilevel (three level) inverter with a nominaldc-link voltage of 750 V. The load was a 15-hp 150-r/min 460-V5-Hz synchronous motor. For comparison purposes, the con-ventional SVM approach was also used with a switching fre-quency of 500 Hz. To apply the modified SVM scheme withcommon-mode voltage cancellation to the conventional mul-tilevel inverter hardware, an effective switching frequency of1000 Hz was necessary, due to the available timer configura-tion. The experimental results of the conventional and modifiedcases are shown in Figs. 17–24. Figs. 17 and 21 show consider-able common-mode voltage, with modulation indexes of 0.175and 0.58, respectively. In comparison, Figs. 18 and 22 show sig-nificant common-mode voltage reduction, in agreement with thesimulation results considering the practical hardware and switchconstraints.

For conventional modulators operating with low modula-tion indexes, i.e., below 0.433, only the space vectors in theinner hexagon (see Fig. 2) are used, resulting in a three-levelline-to-line waveform as shown in Fig. 19. For the modified

Fig. 19. Multilevel inverter line-to-line voltage with conventional SVM:dc-link voltage= 750 V; f = 1:0 Hz; modulation index= 0:175 (onlythe space vectors of the inner hexagon are used, resulting in a three-levelwaveform).

Fig. 20. Multilevel inverter line-to-line voltage with modified SVM: dc-linkvoltage= 750 V; f = 1:0 Hz; modulation index= 0:175 (the space vectorsof the inner and outer hexagon are used, resulting in a five-level waveform).

SVM shown in Fig. 20 with a modulation index of 0.175, sincethe states that generate common-mode voltage are not used,space vectors from the outer hexagon are also used, resultingin a five- level waveform. Figs. 23 and 24 show the line-to-linevoltages with modulation indexes of 0.58, for the conventionaland the modified SVM, respectively.

V. CONCLUSIONS

Common-mode voltage generated by conventional PWM in-verters has been found to be a major cause of premature motorbearing failures due to the resulting leakage currents through thebearings. Similarly, the resulting current through the parasiticcapacitance between the motor windings and the frame adds tothe total leakage current through the ground conductor resulting


Fig. 21. Multilevel inverter common-mode voltage with conventional SVM:dc-link voltage= 750 V; f = 3:33 Hz; modulation index= 0:58.

Fig. 22. Multilevel inverter common-mode voltage with modified SVM:dc-link voltage= 750 V; f = 3:33 Hz; modulation index= 0:58.

in increased conducted EMI and false tripping of relays. It hasbeen proven experimentally in previous work that cancellationof the common-mode voltage will eliminate the bearing currentsand reduce the conducted EMI significantly. In this paper, it isshown through simulation and experimental results that multi-level PWM inverters with modified modulation schemes willnot generate common-mode voltages. Both SVM and sinusoidalSPWM are analyzed based on three-level inverters. This conceptcan be applied to both medium—voltage (2300/4160 V) multi-level inverter applications as well as low-voltage applications toeliminate the common-mode voltage and improve the reliabilityof motor drive systems.

ACKNOWLEDGMENT

The authors would like to thank GE Industrial Systems,Salem, VA, for the use of the multilevel inverter hardware toobtain the experimental results.

Fig. 23. Multilevel inverter line-to-line voltage with conventional SVM:dc-link voltage= 750 V; f = 3:33 Hz; modulation index= 0:58.

Fig. 24. Multilevel inverter line-to-line voltage with modified SVM: dc-linkvoltage= 750 V; f = 3:33 Hz; modulation index= 0:58.

REFERENCES

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[4] A. von Jouanne and H. Zhang, “A dual-bridge inverter approach to elim-inating common mode voltages and bearing and leakage currents,”IEEETrans. Power Electron., vol. 14, pp. 43–48, Jan. 1999.

[5] H. Zhang and A. von Jouanne, “Suppressing common-mode conductedEMI generated by PWM drive systems using a dual-bridge inverter,” inProc. IEEE APEC’98, vol. 2, 1998, pp. 1017–1020.

[6] S. Ogasawara, H. Ayano, and H. Akagi, “An active circuit for cancella-tion of common-mode voltage generated by a PWM inverter,” inProc.IEEE PESC’97, vol. 2, 1997, pp. 1547–1553.

[7] A. M. De Broe, A. L. Julian, and T. A. Lipo, “Neutral-to-groundvoltage minimization in a PWM-rectifier/inverter configuration,” inProc. PEVD’96, 1996, pp. 564–568.


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Haoran Zhang (S’98–M’99) received the B.E.E.degree from Tsinghua University, Beijing, China,the M.E.E. degree from the Institute of ElectricalEngineering, Chinese Academy of Sciences, Beijing,China, and the Ph.D. degree in electrical engineeringfrom Oregon State University, Corvallis, in 1985,1988, and 1998, respectively.

From 1988 to 1995, he was an Assistant Professorin the Department of Control Engineering, Harbin In-stitute of Technology, Harbin, China. He is currentlyan IC Design Engineer with Texas Instruments Incor-

porated (formerly Burr-Brown Corporation), Tucson, AZ. His research interestsinclude power electronics, adjustable-speed drives, and power management in-tegrated circuits.

Annette von Jouanne (S’94–M’95–SM’00)received the B.S. and M.S. degrees in electricalengineering with an emphasis in power systemsfrom Southern Illinois University, Carbondale, andthe Ph.D. degree in electrical engineering/powerelectronics from Texas A&M University, CollegeStation, in 1990, 1992, and 1995, respectively.

While at Texas A&M University, she also workedwith Toshiba International Industrial Divisionand International Power Machines on joint uni-versity/industry research. In 1995, she joined the

Department of Electrical and Computer Engineering, Oregon State University,Corvallis, where she is currently an Associate Professor, working primarilyon power electronic converters, power quality, adjustable-speed drive (ASD)ride-through, and investigating and mitigating the adverse effects of applyingASDs to ac motors. She is also the Co-Director of the Motor Systems ResourceFacility (MSRF), an EPRI/OSU Center for motors and drives research andtesting.

Dr. von Jouanne received the 2000 IEEE Industry Applications Society(IAS) Outstanding Young Member Award, the IAS Magazine Prize PaperAward, and the National Science Foundation CAREER Award. Since 1997,she has also served as an Associate Editor of the IEEE TRANSACTIONS ON

INDUSTRIAL ELECTRONICS. She is a Registered Professional Engineer in theState of Washington.

Shaoan Dai (S’00) received the B.S. and M.S.degrees from Harbin Institute of Technology,Harbin, China, in 1987 and 1990, respectively. Heis currently working toward the Ph.D. degree in theDepartment of Electrical and Computer Engineering,Oregon State University, Corvallis.

He was an Assistant Professor and then an Asso-ciate Professor in the Department of Control Engi-neering, Harbin Institute of Technology, from 1990to 1996 and from 1996 to 1999, respectively. His in-terests are focused on power electronics, adjustable-

speed drives, and control engineering.

Alan K. Wallace (M’78–SM’84–F’00) received theB.Eng. and Ph.D. degrees in electrical power engi-neering from the University of Sheffield, Sheffield,U.K., in 1963 and 1966, respectively.

From 1966 to 1967, he was with Imperial Chem-ical Industries, working on the application of digitalcomputers to process control. In 1967, he joined theUniversity of Nottingham, Nottingham, U.K., wheretaught electrical machine design and power systemanalysis until 1974. From 1974 to 1984, he was en-gaged in design and development of propulsion sys-

tems in the mass transit industry in Canada. He worked with Spar Aerospaceof Toronto and Canadair Services and was Manager of Power Distribution forthe Urban Transportation Development Corporation, Kingston, ON, Canada.In 1984, he joined the Department of Electrical and Computer Engineering,Oregon State University, Corvallis, where he currently teaches and conductsresearch. He is also the EPRI/OSU Director of the Motor Systems Resource Fa-cility (MSRF). From 1991 to 1992, he was a Visiting Research Fellow at theUniversity of Cambridge, Cambridge, U.K. His interests are primarily in ad-justable-speed drives, variable speed generation, linear motor applications totransportation, and power electronic applications.

Dr. Wallace is a member of the Institution of Electrical Engineers, U.K., andfrom 1988 to 1991, he was an Associate Editor of the IEEE TRANSACTIONS ON

POWER ELECTRONICS.

Fei (Fred) Wang (S’85–M’91–SM’99) received theB.S. degree from Xi’an Jiaotong University, Xi’an,China, and the M.S. and Ph.D. degrees from the Uni-versity of Southern California, Los Angeles, in 1982,1985, and 1990, respectively, all in electrical engi-neering.

He was a Research Scientist in the Electric PowerLaboratory, University of Southern California, from1990 to 1992. He joined the GE Power Systems En-gineering Department, Schenectady, NY, as an appli-cation engineer in 1992. From 1994 to 2000, he was

a Senior Development Engineer with GE Industrial Systems, Salem, VA. He iscurrently Manager of the Electrical Systems Technologies Program at the GEChina Technology Center, Shanghai, China. His interests and responsibilitiesare in the areas of power electronics, controls, electric machines, and motordrives.

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Multilevel inverter Modulation schemes to eliminate Common-Mode Voltages