multilevel inverter

2014 IEEE Students Conference on Electrical, Electronics and Computer Science

978-1-4799-2526-1/14/$31.00 2014 IEEE

A New Simplified Multilevel Inverter Topology for Grid-Connected Application

Sandeep. N Prachi Salodkar P. S. Kulkarni M.Tech Student Ph.D Scholar Associate Professor Department of Electrical Engineering Department of Electrical Engineering Department of Electrical Engineering VNIT Nagpur, India VNIT Nagpur, India VNIT Nagpur, India [email protected] [email protected] [email protected]

Abstract Multilevel inverter performance is high compared to the conventional two level inverters due to their reduced harmonic distortion, lower electromagnetic interference. However the main drawback of multilevel inverter is increased number of switches, complex pulse width modulation control and balancing of capacitor voltages. This paper proposes a single phase seven level inverter for grid connected system. The proposed inverter topology consists of fewer components with low complexity gate drives and control signals. An LC filter is used to limit the switching current ripple by providing high attenuation of harmonic and high dynamic performance. This paper also presents the most relevant control and modulation methods by a new reference/carrier based PWM scheme employing three similar reference signals with an offset of magnitude equal to the amplitude of the carrier signal. The entire system is numerically simulated using MATLAB/SIMULINK and the simulation results are presented.

Index Terms LC filter, multilevel inverter, sinusoidal pulse width-modulated, topology.

I. INTRODUCTION Power conversion using multilevel converters was first

introduced more than twenty years ago. The general idea involves usage of higher number of semiconductor switches to perform the power conversion with small voltage steps. There are several advantages with this approach as compared to that of the conventional power conversion technique. Different topologies are presented in the literature as multilevel converters [1] show some of the characteristics in common which lead to some of these clear advantages.

Reduction in the voltages applied to the main power switches, enabling operation at higher load voltages

Transient voltages automatically limited Production of higher power quality waveform, improved

electromagnetic compatibility They draw input current with very low distortion. The main disadvantage associated with the multilevel

configurations is their circuit complexity, which requires high number of power switches that must be controlled in a precisely determined sequence by a dedicated (and complex) Pulse width Modulation (PWM) circuit. They also require great number of dc levels for the production of smaller voltage steps, which are provided by isolated voltage sources or by an array of capacitive voltage dividers. Availability of isolated voltage sources is bit a difficult, and keeping the capacitive divider

network under balance further increases the complexity of PWM circuitry. To overcome this voltage-balancing problem, need of another multilevel converter may arise [2]. In recent years, new converter topologies and unique modulation techniques are the result of increased interest toward the research of multilevel power conversion. Multilevel converter systems are generally classified as cascade inverters, diode-clamping inverters, and flying-capacitor inverters. There are also some combination of the above mentioned topologies which comprises of three-level diode-clamped converter cascaded with two level converter known as cascade 3/2 converter and combination of five-level neutral point converter with a three-level cascade converter known as 5/3 multilevel inverter [3]. Multilevel converters have found widespread applications in industry. They can be used in traction applications in the transportation industry, grid integration of renewable-energy sources [4], flexible ac transmission systems (FACTS) and vehicle propulsion system.

The topology proposed in this paper is symmetrical since the values of all the DC link voltage sources are equal. However there are few asymmetrical topologies that require voltage sources of different values [5]. This asymmetry results in the need of dc voltage sources having a specific relation between them and also the difference in rating of the semiconductor switches is a major drawback. Some of the topologies like the one proposed in [6] suffers from complexities involved in balancing the capacitor.

This paper presents an overview of a new seven level inverter topology which has been developed from the reversing voltage (RV) topology presented in [7]. The new converter topology used in the power stage offers an important improvement in terms of lower component count and reduction

Fig. 1. Schematic of proposed single phase seven-level inverter.

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of layout complexity when compared to conventional topologies. As only part of the power stage switches operates at high frequency and the number of switches conducting current is less results in simpler and more reliable control system for inverter and also the efficiency of inverter is more.

II. PROPOSED INVERTER TOPOLOGY

A. Circuit Description In conventional multilevel inverters, the power switches are

operated to produce a high- frequency waveform in both positive and negative polarities. However there is no need to use all the switches for production of bipolar levels. This is the basic idea that has been put into practice by the proposed topology. The output voltage is synthesized by two stages namely level generator which is responsible for the generation of levels requires in positive polarity and secondly the polarity generator stage which is responsible for generating the polarity of the output voltage. The power semiconductor switches employed in the level generator should have high switching frequency capability for generating the required levels. Whereas the power switches employed for polarity generation operates at the line frequency. The positive levels generated by the level generator is fed to a full-bridge inverter (polarity generator) which will generate the required polarity of the output voltage. By duplicating the center stage as shown in Fig. 1, this topology can be easily extended to higher voltage levels.

B. Power Stage Operation The switching sequences for the generation of positive

levels (0, Vdc/3, 2Vdc/3, Vdc) named as level 0, level 1, level 2, level 3 are as shown in Table I. According to the table there are four possible switching states to control the inverter. The required output positive voltage levels produced by the level generator are generated as follows:

1) Zero output level: Switches 2S , 4S , 6S are ON which short circuits the input terminal ab of the polarity generator resulting in the generation of zero voltage (level 0). Fig. 2 shows the current paths that are active at this stage.

2) One-third positive output level: Switches 2S , 4S , 5S are ON, connecting the terminal a to Vdc/3 and terminal b to ground. All other high frequency controlled switches are OFF resulting in the generation of Vdc/3 (level 1). Fig. 3 shows the current paths that are active at this stage.

3) Two-third positive output level: Switches 2S , 3S are ON, connecting the terminal a to 2Vdc/3 formed by the sum of two equal capacitor voltages and terminal b to ground. All other high frequency controlled switches are OFF resulting in the generation of 2Vdc/3 (level 2). Fig. 4 shows the current paths that are active at this stage.

4) Maximum positive output level: Switch 1S is ON, connecting the terminal a to Vdc formed by the sum of three capacitor voltages and terminal b to ground. All other high frequency controlled switches are OFF resulting in the generation of Vdc( level 3). Fig. 3 sho-

ws the current paths that are active at this stage.

Fig. 2. Switching sequence required to generate output voltage level zero.

Fig. 3. Switching sequence required to generate output voltage level 1.



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TABLE I SWITCHING COMBINATION REQUIRED TO GENERATE

EACH OUTPUT VOLTAGE LEVEL

Level 0 1 2 3

Active Switches 2-4-6 2-4-5 2-3 1

C. Number of Components Required One of the important advantages of the proposed topology

is that it requires less number of high-switching frequency power semiconductor components. Thus the reliability of the converter is increased. It can be clearly seen that the number of components of the power stage is lower than that of other topologies like the diode clamped and the neutral point clamped configurations, and a new and highly improved multilevel stage. It will further decrease tremendously with the increase in number of voltage levels. Table II shows the comparison of number of components required for different seven level inverter topologies

TABLE II

NUMBER OF COMPONENTS REQUIRED FOR SINGLE PHASE SEVEN-LEVEL INVERTER TOPOLOGIES

. Multilevel inverter Type

NPC cascaded Flying Capacitor

Proposed topology

Main Switches 12 12 12 10 Main Diodes 12 12 12 10 DC bus capacitors 6 3 6 3 Total number 30 27 30 23

III. MULTILEVEL PWM MODULATION During One half cycle of the output frequency of 50 Hz the

inverter operates through three states. PWM gating signals are generated by comparing three reference signals ( ref1V , ref2V , and ref3V ) with a carrier signal ( carrierV ) [8]. The reference signals have the same frequency equal to line frequency and same amplitude. They are in phase with each other with an offset value equal to the amplitude of the carrier signal. Three reference signals will be compared with the carrier signal at a time turn by turn. If ref1V exceeds the peak of the carrier signal carrierV , ref2V will take the turn and will be compared with the carrier signal until it exceeds the peak of carrierV . Then onwards ref3V will take turn and will be compared with carrier signal until it reaches zero. Once ref3V reaches zero, ref2V will be compared again until it reaches zero. The onwards ref1V will be compared with carrierV . The three states are described as follows:

State 1: 1t

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DC link voltage Vdc : 300 VoltsC1-C2-C3 : 3300F Switching frequency : 10 kHz Filter inductor : 5mH Filter capacitor : 2F Filter damping resistor : 2

For modulation index greater than 0.66, the phase angle displacement is determined by

11

12

3 2

4 1

sin

sin2

c

m

c

m

AA

AA

=

= = =

(2)

The switching pattern adopted in the proposed inverter, and the output voltage levels according to the switch on off conditions is as shown in Fig. 6. It also shows the five regions that makes up one half cycle of the inverter output. Fig. 7 shows the decision signals produced by the comparators .C1 represents the comparison output between ref1V and carrierV . C2 represents comparison output between ref2V and

carrierV and C3 represents comparison output between ref3V and carrierV . The gating signals are constructed by adding portions of the PWM decision signals produced by the comparators together through appropriate logic gates. From Table I, the gating signals for high frequency switches can be derived to match the output voltage level shown in Fig. 6. Having the three comparator outputs and the output regions defined it is possible to define the switching signal for each high frequency switch. The PWM signals for all the six switches are as shown in Fig. 8. The gating signal for output polarity generator stage, which changes the polarity of inverter output voltage, is simple. Low-frequency output polarity generator works in two modes: forward and reverse modes. In forward mode, switches 7S and 8S are ON generating positive polarity output. In reverse mode switches 9S and 10S will be ON generating negative polarity output. The switching function of Fig. 8 are given by

1S = 33 RC (3)

2S = 1S

3S = 33422 )( RCRRC ++

4S = )( 54212 RRRRC +++

5S = )()( 422511 RRCRRC +++

6S = )( 511 RRC +

Where + is a logical OR, is a logical AND and - is logical inverse (NOT). The overall efficiency of converter is dependent on the number of switches involved in producing each voltage levels. In a seven-level cascaded topology six switches conduct the inverter current at every instance. However, in the proposed topology the number of switches which conduct current ranges from three switches (for generating level 3) to five switches conducting for other level, while two of the switches are from polarity generator of the inverter. Therefore, the number of switches that conduct current in the proposed topology is lower than that of the cascade inverter that reduces the switching losses and hence it has a better efficiency.

IV. SIMULATION RESULTS In order to verify the proposed inverter topology and the

PWM switching pattern, simulations are performed by using MATLAB/SIMULINK. An output LC filter is used to remove the remove high frequency switching ripples and the design of filter components is done in the same way of tuning filter values as given in [9]. The resonance frequency is considered to be 30 times the line frequency (50 Hz). The PWM switching signals are generated by comparing three reference signals against a triangular carrier signal. The multilevel inverter specification and its associated parameters are as shown in Table III.

TABLE III

MULTILEVEL INVERTER SPECIFICATIONS

The waveform of the proposed multilevel inverter with an

output filter and a series R-L load of 150 and 30mH respectively are shown in Fig. 9.

Fig. 9. From top: Output voltage of level generator (100 V/div), output voltage (200 V/div) and output current (1 A/div) for Ma=0.8.

Fig. 10. Current waveform THD for seven levels of output voltage of Fig. 9.

(4)

(5) (6) (7)

(8)

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Fig. 11 corresponds to modulation index ( aM ) between 0.33 and 0.66. In this range, only ref1V and ref2V gets compared with the triangular carrier wave which results in the generation of output voltage having only five levels.

Fig. 11. From top: Output voltage of polarity generator (100 V/div), and output current (0.5 A/div) for Ma=0.6.

Fig. 12. Current waveform THD for five levels of output voltage of Fig. 11.

For modulation index ( aM ) less than 0.33, only ref1V will be compared with the triangular carrier wave which results in the generation of output voltage having only three levels as shown in Fig. 13.

Fig. 13. From top: Output voltage of polarity generator (50 V/div), and output current (0.25 A/div) for Ma=0.2.

Fig. 14. Current waveform THD for three levels of output voltage of Fig. 13.

Comparing the THD values of the current for three different modulation index shows that the THD reduces with the increase in number of output voltage levels.

V. CONCLUSION In this paper a new inverter topology which has superior

performance, offering improved output waveforms and lower THD over conventional topology in terms of number of switches required, cost, control system and reliability. The number of power semiconductor switches required for the proposed inverter is same as RV topology. However the number of current conducting switches for generation of level 2 and level 3 is lesser than the RV topology results in improved performance of the inverter proposed, in terms of its efficiency. The operating principles and the switching functions are analyzed. The complexity of PWM for this topology is low since it only needs to generate gating pulses for generation of positive level only. The inverter generates a 7-level output waveform for modulation index above 0.66, a 5-level output waveform for modulation index between 0.33-0.66, and a 3-level output waveform for modulation index less than 0.33. The results obtained clearly shows the effectiveness of the proposed topology as a multilevel inverter with reduced number of switches and carriers for PWM.

ACKNOWLEDGMENT The authors would like to thank the authorities of VNIT, Nagpur for providing facilities to carry out the research work.

REFERENCES [1] J. Rodriguez, J. S Lai, and F. Z. Peng Multilevel inverters: A

survey of topologies, controls, and applications, IEEE Trans. Ind. Electron., vol. 49, no. 4, pp. 724-738, Aug. 2002.

[2] L. M. Tolbert, F. Z. Peng and T. G. Habetler Multilevel Converters for Large Electric Drives, IEEE Trans. Ind. Appl., vol. 35, no. 1,pp. 36-44, Jan. 1999.

[3] T. L. Skvarenina, The Power Electronics Handbook. Boca Raton, FL: CRC Press, 2002.

[4] J. M. Carrasco, J. T. Bialasiewicz, R. C. P. Guisado, and J. I. Leon, Power-Electronic Systems for the Grid Integration of Renewable Energy Sources: A Survey, IEEE Trans. Ind. Electron., vol. 53, no. 4, pp. 1002-1016, Aug. 2006.

[5] E. Beser, B. Arifoglu, S. Camur, and E. K. Beser, Design and application of a single phase multilevel inverter suitable for using as a voltage harmonic sources, J. Power Electron., vol. 10, no. 2, pp. 138145, Mar. 2010.

[6] R. Stala, Application of balancing circuit for dc-link voltages balance in a single-phase diode-clamped inverter with two three-level legs, IEEE Trans. Ind. Electron., vol. 58, no. 9, pp. 4185-4195, Sep. 2011.

[7] E. Najafi, and A. H. M. Yatim, Design and Implementation of a New Multilevel Inverter Topology, IEEE Trans. Ind. Electron., vol. 59, no. 11, pp. 4148-4154, Nov. 2012.

[8] N. A. Rahim, K. Chaniago, and J. Selvaraj, Single-Phase Seven-Grid-Connected Inverter for Photovoltaic System, IEEE Trans. Ind. Electron., vol. 58, no. 6, pp. 2435-2443, Jun. 2011.

[9] M. Liserre, F. Blaabjerg, and S. Hansen, Design and Control of an LCL-Filter-Based Three-Phase Active Rectifier, IEEE Trans. Ind. Appl., vol. 51, no. 5, pp. 1281-1291, Sep. 2005.

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