Multifunction silicon MMIC's for frequency conversion applications

IFFF TRANSACTION\ O N MICROWAVE THEORY AND TECHNIQUES, VOL. 38, NO. 9, SEPTEMBER 1990 1191

Multifunction Silicon MMIC's for Frequency Conversion Applications

Abstract -Recent advances in silicon bipolar IC technology have produced devices with 10-20 GHz f7 and f,,, and excellent yields at MSI levels ( = 100 devices). Thus cost-effective multifunction silicon MMIC's can now be developed for many commercial RF/microwave systems. In this work, the modeling, design, and testing of two silicon MMIC's for frequency conversion applications are illustrated in detail. The first product is a wide-hand frequency doubler with conversion gain, 20 dBc rejection of harmonics, and a 2 GHz bandwidth. The second product is a wide-band vector demodulator (or image reject mixer) that utilizes an on-chip digital frequency divider to generate 0" and 90" LO phases from 0.05-1.5 GHz. Both products operate from a single 5 V supply, are load-insensitive, require no external baluns, and are packaged in tiny 180 mil hermetic packages. These frequency conversion MMIC's and others currently under development have been prototyped on the analog silicon transistor array sturCHIP"'-l, which is also described.

I. INTRODUCTION ILICON BIPOLAR IC technologies have now pro- S duced many monolithic microwave products for appli-

cations well above 1 GHz [1]-[3]. In general, silicon MMIC's can offer higher reliability, reduced size, reduced power consumption, and lower cost (in sufficient volumes) when compared with traditional hybrid circuit approaches. Silicon MMIC's have also proved to be more cost-effective solutions than equivalent GaAs MMIC's for most commercial applications below 5 GHz [l].

The silicon MMIC's presently available have consisted primarily of single-function generic RF/microwave components. Multifunction MMIC's are now becoming a production reality as microwave silicon bipolar processes mature and yields increase. Designing and testing these multifunction MMIC's present many new challenges. For example, the multiple functions must ideally be dc-coupled on-chip to reduce the packaging complexity. Also, RF wafer sort testing is generally required due to the poor dc-RF correlation of many complex multifunction MMIC's.

The design of multifunction silicon MMIC's is very dependent on accurate circuit simulation of both the devices and packages since "breadboarding" with hybrid approaches has poor correlation to the final MMIC performance. Even with accurate device and package models though, the design and manufacture of fully customized

Manuscript received December 14, 1989; revised March 12, 1990. The authors are with Advanced Bipolar Products, Avantek, Inc.,

IEEE Log Number 9036831. 39201 Cherry St., Newark, CA 94560.

I_.I I POLYIMIDE DIELECTRIC I I

I

Fig. 1. Cross section of the ISOSAT-I1 process.

silicon MMIC's require substantial nonrecurring costs and development time. Thus, the frequency conversion MMIC's described in this work have been prototyped initially on Avantek's first semicustom product, the starCHIP'"-l analog transistor array. Semicustom silicon MMIC arrays offer a cost-effective compromise for small volumes which combines many of the performance advantages of full-custom IC's with the flexibility of hybrid circuits.

11. PROCESS OVERVIEW Fig. 1 gives an overall cross section of transistors, resis-

tors, and interconnects available with the ISOSAT""-II technology. The bipolar devices feature 0.6 p m nitride self-aligned emitters on a 2 p m emitter-base pitch. The fully ion-implanted structure has shallow emitters and active base widths below 100 nm. These devices have a peak fT of 10 GHz and a peak f,, of 20 GHz for a standard collector profile that allows typical BVcEo > 15 V and BVcBo > 25 V. Other available collector profiles for digital applications (or 5 V analog) feature f T to 20 GHz with BVcEo - 5 V.

Parasitics are minimized throughout the process. A global buried layer and deep collector plug keep collector resistance low. The global buried layer also provides a good RF ground plane at a depth of only a few microme- ters below the metal interconnections on the die. Poly- imide-filled trench isolation minimizes collector-substrate capacitance and a 2-pm-thick field oxide greatly reduces the parasitic capacitance of first metal and thin-film polysilicon resistors. The thick field oxide isolates the parasitic collector-base sidewall junction and increases the device breakdown voltages. This process features a

0018-9480/90/0900-1191$01 .OO 01990 IEEE

1192

Parameter Meadurement Minimum Typical Condition Value Value

IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 38, NO. 9, SEPTEMBER 1990

Maximum Value

F i g . 2. Layout of the starCHIP-1 analog transistor array.

VBE(ON)

BVCBO

IC = 5 mA , VCB = 0 V 820 mV 30 V 35 V

IC = 10 p A 20 V 25 V BVCE~ IC = 10 p A (base open) 12 V 15 V

. BVEBO = Io pA 1.5 V 2 V

BVcs IC = 10 p A

TABLE I THIN-FILM POLYSILICON RESISTOR DATA

TABLE I1 TYPICAL HIGH-FREQUENCY TRANSISTOR DATA

200 -800 40420 100 loo0 46 10 -800 5 40820 10 190

Mise. 125-500 152 12 -800 .7 41425 12 25 400 4

"true" second metal capability (as bpposed to air bridges) TABLE 111 for layout ease while maintaining low parasitic capacitance due to its thick polyimide dielectric spacer.

111. THE STARCHIP-1 ARRAY TOPOLOGY The silicon semicustom array starCHIP- 1 contains 92

high-speed, low-noise npn transistors and 394 low-parasitic, thin-film resistors. Some thin-film capacitance can also be realized on-chip.

As shown in Fig. 2, the 40x60 mil die is organized into four symmetric tile arrays separated by tightly packed resistor/capacitor arrays and surrounded by 24 bond pads and 20 extra transistors. Each tile array contains 18 npn transistors and three variable resistor arrays. Resistors are easily combined in series and/or parallel to produce desired values. TypicaI resistor data are given in Table I. Practical resistor values vary from 5 C! to 10 kR. Four different transistor sizes are available, as summarized in Table 11. The transistors are arranged for easy layout as differential pairs, Gilbert cells, or Darlingtons. Some typi-

cal dc device characteristics are given in Table I11 for the most common transistor on the array (the 40420). Thin- film, on-chip capacitance is available by using metal 1 and the 1000 R polysilicon resistors separated by Si,N, and SO,. Practical values of capacitance are 0.2-5 pF with a dielectric strength of at least 40 V.

Adequate component spacing and a full two-level metal capability (2 y m line/space in metal 1) permit easy routing and high component utilization. The 24 low-para-

NEGUS AND WHOLEY: MULTIrUNCTlON SILICON MMIC 'S 1193

n m m _. -'.__)-_- - -

Fig. 3 Photograph of a blank starCHIP-l die.

TABLE IV TYPICAL SPICE GUMMEL-POON MODEL PARAMETERS

FOR 40420 DEVICE

.16 fA

15 mA 130 fF 30 R

XTB 1.8 RC 50 R

sitic 2 mil bond pads allow for flexible pin-outs, multiple in-package capacitors, and easy probing of critical internal circuit nodes. An SEM photo of the blank array is given in Fig. 3.

Design freedom is naturally restricted somewhat by fixed device sizes available on a given transistor array. For the starCHIP-1 array, ample variation in resistor values permits easy optimization of the available device sizes for peak R F performance. However, the power dissipation for a fully utilized array will inevitably be 50-100 mA and peak output powers will be on the order of 0-5 dBm. Lower power dissipation parts or higher output powers can be attained by transferring the design either to other arrays or to a full-custom layout.

IV. DEVICE AND PACKAGE MODELING In the design of silicon MMIC's, both small- and large-

signal analyses are routinely required [4]. Thus accurate device and package models are needed in a format appli- cable to a nonlinear circuit simulator such as SPICE.

The silicon bipolar devices on the array are modeled by the extended Gummel-Poon model of SPICE [51. Some important parameters for this model are summarized for the 40420 deyice in Table IV. The dc parameters are determined using extraction and optimization software on data collected by a dc source/monitor unit. The ac parameters require the addition of a vector network analyzer and capacitance meter.

Layout parasitics can be readily calculated for interconnects and thin-film resistors and back-annotated into the

Fig. 4. Photograph of the 180 mil hermetic packages.

I

Lead j

~

~

Fig. 5 . Electrical model of the 180 mil hermetic package.

TABLE V TYPICAL LUMPED-ELEMFNT MODEI VALUES FOR 180 M I L PACKAGE

Condition Package base AC grounded - Single bond wire, 1 mm long Adjacent leads Opposite leads Adjacent bonds Opposite bonds Package base AC grounded 2 mil bond pad Adjacent leads Opposite leads

SPICE netlist of a given design. Typical values are 0.017 fF /pm2 for metal 1 or polysilicon resistors and 0.006 fF/pm2 for metal 2. Thus, a 400 0 resistor as implemented on the array has a parasitic capacitance of about 7 fF and a 200 p m metal 1 line 4 p m in width has a parasitic capacitance of about 13 fF. Although these typical parasitics are significant, comparison with the device junction capacitances of the 40420 as shown in Table IV indicates that device parasitics dominate most designs on the array.

The products described in this work are packaged in the eight-lead 180 mil glass-metal package shown in Fig. 4. For circuit simulations, a simple electrical model of lumped elements is used as illustrated in Fig. 5. In this model the package leads and bonding wires are modeled by series inductors and shunt capacitors with coupling as shown. This model could be made more accurate with

1194 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 38, NO. 9, SEPTEMBER 1990

r-- - - - - - - - - - -~- - - - - - - - - - - - - - - - - - - - Output Ditferentiai AmMIer A3 ! M I !

I --_________------------------_---~ Fig. 6. Block diagram of wide-band frequency doubler.

~ input ampiiner A1 Dlstortion Amp A2 Gilbert Multlpiier M1

200 200 200

00

lX40220 ,~40420 , ail resistances in Ohms.

Fig. 7. Circuit schematic of frequency doubler input stage, distortion amplifier, and Gilbert cell multiplier.

extra elements (especially for frequencies above 5 GHz) but at the expense of increased computer simulation time. Fortunately, this simple model adequately predicts the most important effects of impedance mismatch, signal isolation, and effective ground loop delays. Actual ele- mental values for the model shown in Fig. 5 can be determined through numerical simulation and/or measurements on a network analyzer. Some typical model values for the 180 mil package of Fig. 4 are given in Table V.

V. WIDE-BAND FREQUENCY DOUBLER The basic conceptual operation of a wide-band fre-

quency doubler is shown in Fig. 6 [6], [7]. In this circuit an input amplifier A1 provides impedance matching, single to differential conversion, and appropriate dc level shifting for this monolithic design. The distortion amplifier A2 provides the inverse distortion of the LO quad in the Gilbert cell multiplier M1. Thus, the multiplication of f - and f by M1 produces an output 2 f which is linearly related to f in power. A final output amplifier A3 filters out the substantial common mode signal f and provides power gain and output impedance matching. The component functions from a single power supply VCC = 5 V and draws approximately 80 mA.

The actual circuit schematic for the input stage Al , distortion amplifier A2, and Gilbert cell multiplier M1 is given in Fig. 7. Note that for implementation on the starCHIP-1 array, the device size choices are limited and most design effort is spent on choosing the appropriate resistor values for device sizes chosen, as shown in Fig. 7.

I I I I , I 200 200

1x I I

i I l l

px SX I

w 1 1 I I I

vcspx yw px yw px

1 00

1X40220,~40420,4X40820,9X41425, ail resistances in Ohms.

Fig. 8. Circuit schematic of frequency doubler output stage

The input signal f is ac coupled by an external capacitor to a differential converter centered by the on-chip bias VBB = VCC- 1.3 V. An in-package but off-chip bypass capacitor of 50 pF is used for input termination. For low-frequency operation this point is connected to a package lead for a larger external bypass capacitor to VEE = 0 V. Current sources throughout the design are based on the bias line VCS shown in Fig. 7. Both VBB and VCS are generated on-chip using a modified band gap regula- tion circuit for excellent temperature and supply stability.

The distortion amplifier is similar to a standard linear differential amplifier except that active loads are used instead of resistors. The use of devices with collectors and bases shorted as shown in Fig. 7 provides a “predistor- tion” on the input signal which is ideally the inverse of the distortion that the nonlinear LO quad of the Gilbert cell multiplier will place on its input signal. The 200 R resistor above the active load devices serves only as a level shifter to keep the LO quad devices out of saturation and to minimize their collector-base capacitance. The multiplier ideally produces 2 f components and a dc offset on the 200 R load resistors, but the common-mode switching of the emitter-coupled pairs introduces a substantial f component, as indicated in Figs. 6 and 7.

Several design approaches can be taken to improve the ratio of 2 f to f output power. One approach is to increase the emitter resistors of these differential ampli- fiers and thus reduce the relative amount of current being switched common-mode by the LO quad devices. Unfor- tunately this also reduces the 2 f output gain. The gain can be restored by increasing the load resistors but this reduces the bandwidth of the multiplier and creates saturation problems for the LO quad due to dc offsets. The approach in this design is to optimize the multiplier for 2 f bandwidth and then use a differential output amplifier A3 (as illustrated in Fig. 8) to reject the common-mode signal f which is present in the otherwise differential outputs of the multiplier. The output amplifier of Fig. 8 also provides substantial 2 f power gain and output impedance matching, as shown.

NEGUS AND WHOLEY: MULTIFUNCTION SILICON MMIC'S 1195

The operation of the wide-band frequency doubler can be better understood by considering the SPICE-generated internal waveforms of Fig. 9. The bottom graph shows the actual input waveform seen by the doubler, fin, versus time for an input signal of about - 17 dBm at 1 GHz. The second graph shows the differential distortion amplifier output ( f - ' --p with reference to Figs. 6 and 7). Note that the inverse distortions must correlate extremely well since this signal is significant relative to thermal voltage V, and thus highly nonlinear. The third graph is one of the two outputs of the Gilbert cell multiplier, which obviously contains a substantial f component in addition to the 2 f component. The top graph is one of the differential outputs as delivered to a 50 R load (about -15 dBm). ,Clearly the output differential amplifier successfully removes most of the common-mode f component from the output. In summary, the simulations predict a 2 dB conversion gain, > 15 dBc rejection of the f , 3 f , and higher order components, and a 3 dB bandwidth of about 2.5 GHz output frequency.

This design has been successfully manufactured and assembled. Measured results of a typical part are given in Fig. 10, where the f , 2 f , and 3f output powers on a single output channel are plotted versus 2 f output frequency for an input power of - 10 dBm. The 3 dB bandwidth is seen to be approximately 2 GHz and at low frequencies the rejection of unwanted harmonics is greater than 20 dBc.

-50 404 0 1 2 3 4

2f Output Frequency (GHz)

Fig. 10. Measured harmonic output powers of frequency doubler versus 2 f frequency for constant input power of - 10 dBm.

Wafer sorting this complex multifunction MMIC required R F testing since the dc to RF correlation was very poor.

VI. WIDE-BAND VECTOR DEMODULATOR A second multifunction silicon MMIC implemented on

the starCHIP-1 array is the vector demodulator or image reject mixer illustrated in Fig. 11 181. In this circuit, a input of frequency 2fL0 is provided through a buffer amplifier to the clock input of a master/slave D flip-flop connected as an asynchronous toggle. The flip-flop di- vides the frequency by 2 and generates the four quadrature phases of fLo. These in turn differentially drive two

1196 IEEE TRANSACTIONS

I I I I .-

I RF Fig. 11. Block diagram of wide-band vector demodulator.

I INPUTBUFFER MASTER LATCH LO DRIVER I vcc I I I

I I

$00 loo 57

; VEE

w-40420, all msistancea In Ohms.

LO driver for vector demodulator.

1. Fig. 12. Circuit schematic of 2fL0 input buffer, master D latch, and

identical active mixers that ultimately produce the four quadrature IF outputs. Critical parameters are matching the mixer conversion gains and obtaining ideal quadrature separation of the outputs.

Fig. 12 shows the schematic of the 2fL0 input buffer and the master D latch of the flip-flop (slave latch is identical). The VBB and VCS bias lines are generated on chip by voltage dividers and resistor-ratioed current mir- rors. The 2fL0 buffer provides single to differential conversion, gives excellent limiting for a wide range of input powers, and achieves wide-band matching through 50 R resistors in shunt with the device bases. Necessary dc level shifting is accomplished by a resistive drop in the common-mode collector segment. The differential-mode collector resistors are kept small to provide sharp pulse edges for the clock input of the static frequency divider.

The master D latch shown in Fig. 12 (and the equivalent slave latch) are of standard emitter-coupled logic (ECL) configuration. Emitter follower outputs are used to provide adequate high-frequency drive to the LO inputs of the active mixers. Delays in the latches are significantly affected by the time constant 3R,Cj,, where R , is the collector load resistance (33 R in Fig. 12) and Cj, is the collector-base capacitance of the 40420 device. The excel-

ON MICROWAVE THEORY AND TECHNIQUES, VOL. 38, NO. 9, SEPTEMBER 1990

r

i T

I MIXER IF DRIVER I

/ vcc 200 2

I I I 1 I I VEE

I I I

2X-40420,4X-40820, all resistances In Ohms.

stage for vector demodulator.

+ I -

Fig. 13. Circuit schematic of Gilbert cell active mixer and IF output

lent matching of the load resistors on a single MMIC thus helps to minimize quadrature phase errors.

Fig. 13 shows the in-phase (I) active mixer driven by the LO(0") and LO(180") signals. The identical quadrature phase (Q) mixer (not shown) is driven by the LO(90") and LO(270") signals. These mixers are based on the Gilbert cell structure [9], where an RF signal is provided to a differential pair and multiplied by f 1 at fLO to produce double balanced mixer characteristics. As with the 2fL0 input buffer, shunt resistors are used to maintain wide- band impedance matching of the R F input. Emitter fol- lowers provide power gain for 50 R operation with wide- band matching provided by series resistors as shown in Fig. 13. Conversion gain balance of the two mixers is closely related to the ratios of the collector load resistor to the emitter resistor and to the current source resistors. Again the single-chip implementation of these multiple functions enhances the performance due to the excellent matching of thin-film resistors on a single silicon MMIC.

This vector demodulator has been successfully realized on a single array. The layout complexity approaches the practical maximum density for this particular array. Power supply (VCC-VEE) is only 5 V and total current is typically 80 mA. RF wafer testing was used out of neces- sity to sort the MMIC's. Typical packaged performance parameters were < 0.5 dB mixer gain imbalance and < 5" quadrature error, which corresponds to >25 dB image rejection. The 2fL0 input power can be as low as -20 dBm with minimal performance degradation and the PIN-ldB is approximately 0 dBm for the RF port.

The vector demodulator in combination with the previ- ously described frequency doubler can operate as a wide- band image reject mixer, as illustrated in Fig. 14. The measured conversion gain of each IF channel is plotted versus RF frequency in Fig. 14 for a fixed IF frequency of 70 MHz. Both the frequency doubler and the master/slave D flip-flop limit the LO frequency to approximately 1.5 GHz (or 2fL0 = 3 GHz). The measured 3 dB IF bandwidth was typically 850 MHz. Excellent gain balance and quadrature were obtained, as shown by the time-domain

1197

0

-5 Conversion Gain (dB)

-1 0

-1 5 0 0.5 1 1.5 2

RF (GHz) LO=RF-’IO MHz

W O ) IF(90) IF(180)

LO (-lOdBm) ..++E= IF(270) @++GI FREQUENCY

Fig. 14. Measured RF-IF conversion gain per channel for frequency doubler and vector demodulator combination as shown.

Fig. 15. Measured time-domain IF(0”) AND IF(90”) waveforms for vector demodulator.

measurements of the IF(0”) and IF(90”) channels in Fig. 15. These multifunction silicon MMIC’s greatly simplify receiver architectures that presently utilize two-stage up- conversion/down-conversions to eliminate image signals.

VII. COMPARISON wI’rI-1 FULL-CUSTOM MMIC’s As noted throughout this paper, both multifunction

MMIC’s were implemented on a semicustom array. De- sign and layout of each MMIC required approximately three to four weeks of one engineer’s time. Fabrication time (including ordering the three customization masks) was approximately three to four weeks as well. Thus the total cycle time for prototyping MMIC’s on the semicustom array was about seven weeks. In contrast, full-custom MMIC’s typically require two to three months for design and layout (due to the greater degrees of freedom available) and at least three months to order all 11 masks and fabricate the initial wafers. The main advantages of semicustom arrays are thus their faster development time and much lower nonrecurring expenses.

Full-custom design and layout offer several performance and manufacturing advantages. Because device sizes are not restricted, the design can be better opti- mized for reduced power consumption. Overall R F performance may be marginally improved owing to lower layout parasitics. The full-custom layout can also produce a substantially smaller die size in many cases. In addition, yield can be enhanced by using devices of lower performance (and higher yield) for noncritical areas of the circuit such as biasing and current sources. The substantially increased initial costs of full-custom design can be recovered in the long term if sufficient production volumes are required. Although each MMIC design must be examined individually, the break point in most cases is on the order of 10000 parts. In some cases, prototyping one or two design iterations on a semicustom array may still be advantageous before committing to a full-custom MMIC.

VIII. CONCLUSIONS The application of advanced silicon bipolar IC technol-

ogy to multifunction MMIC‘s has been demonstrated in this work. Both the wide-band frequency doubler and the wide-band vector demodulator offer compact size, a single 5 V power supply, and good input/output impedance matching. These multifunction silicon MMIC’s are ideal for high-volume commercial frequency conversion applications owing to their inherent low cost on a high-yield- ing, mature silicon process technology. The example MMIC’s in this work also illustrate the utility of the starCHIP-1 analog transistor array for systems below 5 GHz.

ACKNOWLEDGMENT The authors acknowledge the excellent work performed

by M. Dutta and the entire Pilot Line at Advanced Bipolar Products in fabricating the wafers used to proto- type these MMIC’s.

REFERENCES C. P. Snapp, “Practical silicon bipolar ICs for RF, microwave and lightwave applications,” in Proc. Wescon / 89 , Nov. 1989, pp. 282-287. J. Wholey, I. Kipnis, and C. P. Snapp, “Silicon bipolar double balanced active mixer MMICs for R F and microwave applications up to 6 GHz,” in IEEE M V - S h i . Microwave Symp. Dig., June 1989, pp. 281-285. I. Kipnis, J. F. Kukielka, J. Wholey, and C. P. Snapp, “Silicon bipolar fixed and variable gain amplifier MMICs for microwave and lightwave applications up to 6 GHz,” in IEEE MTT-S In?. Mi- crowaw Symp. Dig., June 1989, pp. 109-112. I. Kipnis and A. P. S. Khanna, “Large signal computer analysis and design of silicon bipolar MMIC oscillators and self-oscillating mixers,” IEEE Trans. Microwaue Theory Tech., vol. 37, pp. 558-564, Mar. 1989. I. Getreu, Modeling the Bipolar Transistor Tektronix Part No. 062- 2841-00, Beaverton, OR, 1976. A. Bilotti, “Applications of a monolithic analog multiplier,” IEEE J . Solid-State Circuits, vol. SC-3, pp. 373-380, Dec. 1968. P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. H. Kikushi, S. Konaka, and M. Umehira, “GHz-band monolithic modem ICs,” IEEE Trans. Microwave Theory Tech., vol. MTT-35, pp. 1277-1282, Dec. 1987.

New York: Wiley, 1984, pp. 598-600.

1198 IEEE T R A N S A ~ I O N S ON MICROWAVE THEORY AND TECHNIQUES, VOL. 38, NO. 9, SEPTEMBER 1990

[91 B. Gilbert, “A precise four-quadrant multiplier with subnanosec- ond response,” IEEE J. Solid-state Circuits, vol. SC-3, pp. 365-373, Dec. 1968.

Q

Kevin J. Negus (M’88) was born in Fredericton, N.B., Canada, in 1961. He received the B.A.Sc., M.A.Sc., and Ph.D. degrees from the Depart- ment of Mechanical Engineering, University of Waterloo, Waterloo, Ont., Canada, in 1984, 1985, and 1988, respectively.

During the period 1986-1987 he worked with the Fairchild Semiconductor Corporation Re- search Center in Palo Alto, CA, on the electrical interaction between high-speed ECL bipolar devices and their packages. Since 1988 he has

worked in the Advanced Bipolar Products group at Avantek, Inc., in Newark, CA. His current responsibilities include device modeling and development of semicustom products for gigahertz analog and digital applications.

Dr. Negus has published more than 20 papers on the analysis and measurement of bipolar devices and circuits, heat transfer in microelec- tronics, and mechanical stress. He holds one U.S. patent.

8

James N. Wholey was born in Palo Alto, CA, on November 21, 1946. He received the M.S.E.E. degree from Stanford University in 1973.

Since 1973 he has worked at Avantek, Inc., where he is currently a Principal Engineer in the Advanced Bipolar Products group in Newark, CA. His assignments have included process development, reliability engineering and analysis, microwave low-noise and power transistor design, and extensive silicon bipolar MMIC design and development. His present

interest is in the commercial product development of microwave bipolar circuits utilizing active-mixer-based frequency conversion techniques.

Mr. Wholey has published 11 papers and holds one U.S. patent.

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Multifunction silicon MMIC's for frequency conversion applications